diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c
index b582151..67f3327 100644
--- a/plat/qemu/qemu_bl1_setup.c
+++ b/plat/qemu/qemu_bl1_setup.c
@@ -41,10 +41,10 @@
  * does basic initialization. Later architectural setup (bl1_arch_setup())
  * does not do anything platform specific.
  *****************************************************************************/
-#ifdef AARCH32
-#define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
-#else
+#ifdef __aarch64__
 #define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_el3(__VA_ARGS__)
+#else
+#define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
 #endif
 
 void bl1_plat_arch_setup(void)
diff --git a/plat/qemu/qemu_bl2_mem_params_desc.c b/plat/qemu/qemu_bl2_mem_params_desc.c
index ba6a4db..a01f2dc 100644
--- a/plat/qemu/qemu_bl2_mem_params_desc.c
+++ b/plat/qemu/qemu_bl2_mem_params_desc.c
@@ -35,7 +35,7 @@
 	  .next_handoff_image_id = INVALID_IMAGE_ID,
 	},
 #else /* EL3_PAYLOAD_BASE */
-#ifdef AARCH64
+#ifdef __aarch64__
 	/* Fill BL31 related information */
 	{ .image_id = BL31_IMAGE_ID,
 
@@ -59,10 +59,10 @@
 	  .next_handoff_image_id = BL33_IMAGE_ID,
 # endif
 	},
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
 # ifdef QEMU_LOAD_BL32
 
-#ifdef AARCH64
+#ifdef __aarch64__
 #define BL32_EP_ATTRIBS		(SECURE | EXECUTABLE)
 #define BL32_IMG_ATTRIBS	0
 #else
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index b8ca895..4c97c8d 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -81,10 +81,10 @@
 	/* TODO Initialize timer */
 }
 
-#ifdef AARCH32
-#define QEMU_CONFIGURE_BL2_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
-#else
+#ifdef __aarch64__
 #define QEMU_CONFIGURE_BL2_MMU(...)	qemu_configure_mmu_el1(__VA_ARGS__)
+#else
+#define QEMU_CONFIGURE_BL2_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
 #endif
 
 void bl2_plat_arch_setup(void)
@@ -101,7 +101,7 @@
  ******************************************************************************/
 static uint32_t qemu_get_spsr_for_bl32_entry(void)
 {
-#ifdef AARCH64
+#ifdef __aarch64__
 	/*
 	 * The Secure Payload Dispatcher service is responsible for
 	 * setting the SPSR prior to entry into the BL3-2 image.
@@ -119,7 +119,7 @@
 static uint32_t qemu_get_spsr_for_bl33_entry(void)
 {
 	uint32_t spsr;
-#ifdef AARCH64
+#ifdef __aarch64__
 	unsigned int mode;
 
 	/* Figure out what mode we enter the non-secure world in */
diff --git a/plat/qemu/qemu_common.c b/plat/qemu/qemu_common.c
index aee8321..56bf953 100644
--- a/plat/qemu/qemu_common.c
+++ b/plat/qemu/qemu_common.c
@@ -132,11 +132,11 @@
 	}
 
 /* Define EL1 and EL3 variants of the function initialising the MMU */
-#ifdef AARCH32
-DEFINE_CONFIGURE_MMU_EL(svc_mon)
-#else
+#ifdef __aarch64__
 DEFINE_CONFIGURE_MMU_EL(el1)
 DEFINE_CONFIGURE_MMU_EL(el3)
+#else
+DEFINE_CONFIGURE_MMU_EL(svc_mon)
 #endif