refactor(tc): unify all the spmc manifests
The manifests describe the same hardware layout with only the secure
partitions being different. Factor it out so it can be shared and only
add the VM information separately.
This has some deliberate side effects: the test configuration gets the
full secure memory address space and drops the 0x7000000 region as that
was accidentally copied over from the FVP platform and doesn't apply to
TC.
Also optee unconditionally gets the smaller mem_size as it's been
working fine and simplifies the manifest.
Small touch up is that mem_size-s are now in hex but otherwise the same
number.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Iea23f9769235eea32afa374952b9a0e4f6d3e9a1
diff --git a/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
index 73314ee..b7f4fe0 100644
--- a/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
@@ -1,129 +1,17 @@
/*
- * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/dts-v1/;
-/ {
- compatible = "arm,ffa-core-manifest-1.0";
- #address-cells = <2>;
- #size-cells = <2>;
-
- attribute {
- spmc_id = <0x8000>;
- maj_ver = <0x1>;
- min_ver = <0x2>;
- exec_state = <0x0>;
- load_address = <0x0 0xfd000000>;
- entrypoint = <0x0 0xfd000000>;
- binary_size = <0x80000>;
- };
-
- hypervisor {
- compatible = "hafnium,hafnium";
- vm1 {
- is_ffa_partition;
- debug_name = "op-tee";
- load_address = <0xfd280000>;
- vcpu_count = <8>;
-#ifdef TS_SP_FW_CONFIG
- mem_size = <26738688>; /* 25MB TZC DRAM */
-#else
- mem_size = <30928896>; /* 29MB TZC DRAM */
-#endif
- };
-#ifdef TS_SP_FW_CONFIG
- vm2 {
- is_ffa_partition;
- debug_name = "internal-trusted-storage";
- load_address = <0xfee00000>;
- vcpu_count = <1>;
- mem_size = <2097152>; /* 2MB TZC DRAM */
- };
- vm3 {
- is_ffa_partition;
- debug_name = "crypto";
- load_address = <0xfec00000>;
- vcpu_count = <1>;
- mem_size = <2097152>; /* 2MB TZC DRAM */
- };
-#endif
- };
-
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
-
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x0>;
- enable-method = "psci";
- };
-
- /*
- * SPMC (Hafnium) requires secondary cpu nodes are declared in
- * descending order
- */
- CPU7:cpu@700 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x700>;
- enable-method = "psci";
- };
-
- CPU6:cpu@600 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x600>;
- enable-method = "psci";
- };
-
- CPU5:cpu@500 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x500>;
- enable-method = "psci";
- };
-
- CPU4:cpu@400 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x400>;
- enable-method = "psci";
- };
-
- CPU3:cpu@300 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x300>;
- enable-method = "psci";
- };
-
- CPU2:cpu@200 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x200>;
- enable-method = "psci";
- };
-
- CPU1:cpu@100 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x100>;
- enable-method = "psci";
- };
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0xfd000000 0x0 0x2000000>;
- };
+#include <tc_spmc_manifest.dtsi>
+#include <tc_spmc_common_sp_manifest.dtsi>
- memory@1 {
- device_type = "ns-memory";
- reg = <0x0 0x80000000 0x0 0x79000000>,
- <0x80 0x80000000 0x1 0x80000000>;
+&hafnium {
+ vm1 {
+ debug_name = "op-tee";
+ load_address = <0xfd280000>;
+ mem_size = <26738688>; /* 25MB TZC DRAM */
};
};