Merge "fix(arm): fix GIC macros for GICv4.1 support" into integration
diff --git a/Makefile b/Makefile
index 6a2eeca..5edd625 100644
--- a/Makefile
+++ b/Makefile
@@ -1270,7 +1270,7 @@
ENABLE_FEAT_GCS \
ENABLE_FEAT_VHE \
ENABLE_FEAT_MTE_PERM \
- ENABLE_MPAM_FOR_LOWER_ELS \
+ ENABLE_FEAT_MPAM \
ENABLE_RME \
ENABLE_SPE_FOR_NS \
ENABLE_SYS_REG_TRACE_FOR_NS \
@@ -1323,7 +1323,7 @@
AMU_RESTRICT_COUNTERS \
ENABLE_ASSERTIONS \
ENABLE_BTI \
- ENABLE_MPAM_FOR_LOWER_ELS \
+ ENABLE_FEAT_MPAM \
ENABLE_PAUTH \
ENABLE_PIE \
ENABLE_PMF \
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 0c1d657..a1fc12b 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -106,7 +106,7 @@
BL31_SOURCES += lib/extensions/sve/sve.c
endif
-ifneq (${ENABLE_MPAM_FOR_LOWER_ELS},0)
+ifneq (${ENABLE_FEAT_MPAM},0)
BL31_SOURCES += lib/extensions/mpam/mpam.c
endif
diff --git a/common/feat_detect.c b/common/feat_detect.c
index a1ffc39..be22c6e 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -169,7 +169,7 @@
check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), "DIT", 1, 1);
check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(),
"AMUv1", 1, 2);
- check_feature(ENABLE_MPAM_FOR_LOWER_ELS, read_feat_mpam_version(),
+ check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(),
"MPAM", 1, 17);
check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(),
"NV2", 2, 2);
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index 9b51dab..3d2783d 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -69,7 +69,7 @@
| | Date | after | |
| | | Release | |
+================================+=============+=========+=========================================================+
-| None at this time | | | |
+| STM32MP15_OPTEE_RSV_SHM | 2.10 | 3.0 | OP-TEE manages its own memory on STM32MP15 |
+--------------------------------+-------------+---------+---------------------------------------------------------+
Removal of Deprecated Drivers
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index cd70a22..654ddc5 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -397,7 +397,7 @@
support in GCC for TF-A. This option is currently only supported for
AArch64. Default is 0.
-- ``ENABLE_MPAM_FOR_LOWER_ELS``: Numeric value to enable lower ELs to use MPAM
+- ``ENABLE_FEAT_MPAM``: Numeric value to enable lower ELs to use MPAM
feature. MPAM is an optional Armv8.4 extension that enables various memory
system components and resources to define partitions; software running at
various ELs can assign themselves to desired partition to control their
@@ -408,7 +408,9 @@
access their own MPAM registers without trapping into EL3. This option
doesn't make use of partitioning in EL3, however. Platform initialisation
code should configure and use partitions in EL3 as required. This option
- defaults to ``0``.
+ defaults to ``2`` since MPAM is enabled by default for NS world only.
+ The flag is automatically disabled when the target
+ architecture is AArch32.
- ``ENABLE_MPMM``: Boolean option to enable support for the Maximum Power
Mitigation Mechanism supported by certain Arm cores, which allows the SoC
diff --git a/fdts/stm32mp13-bl2.dtsi b/fdts/stm32mp13-bl2.dtsi
index 2b23daf..06db796 100644
--- a/fdts/stm32mp13-bl2.dtsi
+++ b/fdts/stm32mp13-bl2.dtsi
@@ -3,15 +3,6 @@
* Copyright (c) 2022-2023, STMicroelectronics - All Rights Reserved
*/
-/omit-if-no-ref/ &i2c4_pins_a;
-/omit-if-no-ref/ &sdmmc1_b4_pins_a;
-/omit-if-no-ref/ &sdmmc1_clk_pins_a;
-/omit-if-no-ref/ &sdmmc2_b4_pins_a;
-/omit-if-no-ref/ &sdmmc2_clk_pins_a;
-/omit-if-no-ref/ &uart4_pins_a;
-/omit-if-no-ref/ &uart8_pins_a;
-/omit-if-no-ref/ &usart1_pins_a;
-
/ {
aliases {
#if !STM32MP_EMMC && !STM32MP_SDMMC
diff --git a/fdts/stm32mp13-pinctrl.dtsi b/fdts/stm32mp13-pinctrl.dtsi
index 323d5ba..6de9bb0 100644
--- a/fdts/stm32mp13-pinctrl.dtsi
+++ b/fdts/stm32mp13-pinctrl.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
+ /omit-if-no-ref/
i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('E', 15, AF6)>, /* I2C4_SCL */
@@ -16,6 +17,7 @@
};
};
+ /omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -29,6 +31,7 @@
};
};
+ /omit-if-no-ref/
sdmmc1_clk_pins_a: sdmmc1-clk-0 {
pins {
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
@@ -38,6 +41,7 @@
};
};
+ /omit-if-no-ref/
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins {
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */
@@ -51,6 +55,7 @@
};
};
+ /omit-if-no-ref/
sdmmc2_clk_pins_a: sdmmc2-clk-0 {
pins {
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */
@@ -60,6 +65,7 @@
};
};
+ /omit-if-no-ref/
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */
@@ -73,6 +79,7 @@
};
};
+ /omit-if-no-ref/
usart1_pins_a: usart1-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */
@@ -88,6 +95,7 @@
};
};
+ /omit-if-no-ref/
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
diff --git a/fdts/stm32mp131.dtsi b/fdts/stm32mp131.dtsi
index 2be39af..8bcf363 100644
--- a/fdts/stm32mp131.dtsi
+++ b/fdts/stm32mp131.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/clock/stm32mp13-clks.h>
@@ -276,23 +276,20 @@
};
fmc: memory-controller@58002000 {
- #address-cells = <2>;
- #size-cells = <1>;
compatible = "st,stm32mp1-fmc2-ebi";
reg = <0x58002000 0x1000>;
- clocks = <&rcc FMC_K>;
- resets = <&rcc FMC_R>;
- status = "disabled";
-
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
<4 0 0x80000000 0x10000000>; /* NAND */
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clocks = <&rcc FMC_K>;
+ resets = <&rcc FMC_R>;
+ status = "disabled";
nand-controller@4,0 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32mp1-fmc2-nfc";
reg = <4 0x00000000 0x1000>,
<4 0x08010000 0x1000>,
@@ -300,6 +297,8 @@
<4 0x01000000 0x1000>,
<4 0x09010000 0x1000>,
<4 0x09020000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
@@ -341,7 +340,7 @@
status = "disabled";
};
- usbh_ohci: usbh-ohci@5800c000 {
+ usbh_ohci: usb@5800c000 {
compatible = "generic-ohci";
reg = <0x5800c000 0x1000>;
clocks = <&rcc USBH>;
@@ -350,7 +349,7 @@
status = "disabled";
};
- usbh_ehci: usbh-ehci@5800d000 {
+ usbh_ehci: usb@5800d000 {
compatible = "generic-ehci";
reg = <0x5800d000 0x1000>;
clocks = <&rcc USBH>;
@@ -424,7 +423,7 @@
cfg0_otp: cfg0_otp@0 {
reg = <0x0 0x2>;
};
- part_number_otp: part_number_otp@4 {
+ part_number_otp: part-number-otp@4 {
reg = <0x4 0x2>;
};
monotonic_otp: monotonic_otp@10 {
@@ -470,7 +469,6 @@
ranges = <0 0x50002000 0x8400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
- pins-are-numbered;
gpioa: gpio@50002000 {
gpio-controller;
diff --git a/fdts/stm32mp15-bl2.dtsi b/fdts/stm32mp15-bl2.dtsi
index 53aeec5..18a4ba9 100644
--- a/fdts/stm32mp15-bl2.dtsi
+++ b/fdts/stm32mp15-bl2.dtsi
@@ -3,37 +3,8 @@
* Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved
*/
-/omit-if-no-ref/ &fmc_pins_a;
-/omit-if-no-ref/ &i2c2_pins_a;
-/omit-if-no-ref/ &i2c4_pins_a;
/omit-if-no-ref/ &i2c6;
-/omit-if-no-ref/ &qspi_bk1_pins_a;
-/omit-if-no-ref/ &qspi_bk2_pins_a;
-/omit-if-no-ref/ &qspi_clk_pins_a;
-/omit-if-no-ref/ &sdmmc1_b4_pins_a;
-/omit-if-no-ref/ &sdmmc1_dir_pins_a;
-/omit-if-no-ref/ &sdmmc1_dir_pins_b;
-/omit-if-no-ref/ &sdmmc2_b4_pins_a;
-/omit-if-no-ref/ &sdmmc2_b4_pins_b;
-/omit-if-no-ref/ &sdmmc2_d47_pins_a;
-/omit-if-no-ref/ &sdmmc2_d47_pins_b;
-/omit-if-no-ref/ &sdmmc2_d47_pins_c;
-/omit-if-no-ref/ &sdmmc2_d47_pins_d;
/omit-if-no-ref/ &spi6;
-/omit-if-no-ref/ &uart4_pins_a;
-/omit-if-no-ref/ &uart4_pins_b;
-/omit-if-no-ref/ &uart7_pins_a;
-/omit-if-no-ref/ &uart7_pins_b;
-/omit-if-no-ref/ &uart7_pins_c;
-/omit-if-no-ref/ &uart8_pins_a;
-/omit-if-no-ref/ &usart2_pins_a;
-/omit-if-no-ref/ &usart2_pins_b;
-/omit-if-no-ref/ &usart2_pins_c;
-/omit-if-no-ref/ &usart3_pins_a;
-/omit-if-no-ref/ &usart3_pins_b;
-/omit-if-no-ref/ &usart3_pins_c;
-/omit-if-no-ref/ &usbotg_fs_dp_dm_pins_a;
-/omit-if-no-ref/ &usbotg_hs_pins_a;
/ {
#if !STM32MP_EMMC && !STM32MP_SDMMC
diff --git a/fdts/stm32mp15-bl32.dtsi b/fdts/stm32mp15-bl32.dtsi
index 7b63f1b..6882224 100644
--- a/fdts/stm32mp15-bl32.dtsi
+++ b/fdts/stm32mp15-bl32.dtsi
@@ -3,37 +3,8 @@
* Copyright (c) 2020-2023, STMicroelectronics - All Rights Reserved
*/
-/omit-if-no-ref/ &fmc_pins_a;
-/omit-if-no-ref/ &i2c2_pins_a;
-/omit-if-no-ref/ &i2c4_pins_a;
/omit-if-no-ref/ &i2c6;
-/omit-if-no-ref/ &qspi_bk1_pins_a;
-/omit-if-no-ref/ &qspi_bk2_pins_a;
-/omit-if-no-ref/ &qspi_clk_pins_a;
-/omit-if-no-ref/ &sdmmc1_b4_pins_a;
-/omit-if-no-ref/ &sdmmc1_dir_pins_a;
-/omit-if-no-ref/ &sdmmc1_dir_pins_b;
-/omit-if-no-ref/ &sdmmc2_b4_pins_a;
-/omit-if-no-ref/ &sdmmc2_b4_pins_b;
-/omit-if-no-ref/ &sdmmc2_d47_pins_a;
-/omit-if-no-ref/ &sdmmc2_d47_pins_b;
-/omit-if-no-ref/ &sdmmc2_d47_pins_c;
-/omit-if-no-ref/ &sdmmc2_d47_pins_d;
/omit-if-no-ref/ &spi6;
-/omit-if-no-ref/ &uart4_pins_a;
-/omit-if-no-ref/ &uart4_pins_b;
-/omit-if-no-ref/ &uart7_pins_a;
-/omit-if-no-ref/ &uart7_pins_b;
-/omit-if-no-ref/ &uart7_pins_c;
-/omit-if-no-ref/ &uart8_pins_a;
-/omit-if-no-ref/ &usart2_pins_a;
-/omit-if-no-ref/ &usart2_pins_b;
-/omit-if-no-ref/ &usart2_pins_c;
-/omit-if-no-ref/ &usart3_pins_a;
-/omit-if-no-ref/ &usart3_pins_b;
-/omit-if-no-ref/ &usart3_pins_c;
-/omit-if-no-ref/ &usbotg_fs_dp_dm_pins_a;
-/omit-if-no-ref/ &usbotg_hs_pins_a;
/ {
aliases {
diff --git a/fdts/stm32mp15-pinctrl.dtsi b/fdts/stm32mp15-pinctrl.dtsi
index a1be447..70d1db1 100644
--- a/fdts/stm32mp15-pinctrl.dtsi
+++ b/fdts/stm32mp15-pinctrl.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
+ /omit-if-no-ref/
fmc_pins_a: fmc-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
@@ -31,6 +32,7 @@
};
};
+ /omit-if-no-ref/
i2c2_pins_a: i2c2-0 {
pins {
pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
@@ -41,6 +43,7 @@
};
};
+ /omit-if-no-ref/
qspi_clk_pins_a: qspi-clk-0 {
pins {
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
@@ -50,8 +53,9 @@
};
};
+ /omit-if-no-ref/
qspi_bk1_pins_a: qspi-bk1-0 {
- pins1 {
+ pins {
pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
@@ -60,16 +64,11 @@
drive-push-pull;
slew-rate = <1>;
};
- pins2 {
- pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
- bias-pull-up;
- drive-push-pull;
- slew-rate = <1>;
- };
};
+ /omit-if-no-ref/
qspi_bk2_pins_a: qspi-bk2-0 {
- pins1 {
+ pins {
pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
@@ -78,7 +77,21 @@
drive-push-pull;
slew-rate = <1>;
};
- pins2 {
+ };
+
+ /omit-if-no-ref/
+ qspi_cs1_pins_a: qspi-cs1-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
+ bias-pull-up;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ /omit-if-no-ref/
+ qspi_cs2_pins_a: qspi-cs2-0 {
+ pins {
pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
bias-pull-up;
drive-push-pull;
@@ -86,6 +99,7 @@
};
};
+ /omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
@@ -105,6 +119,7 @@
};
};
+ /omit-if-no-ref/
sdmmc1_dir_pins_a: sdmmc1-dir-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
@@ -120,6 +135,7 @@
};
};
+ /omit-if-no-ref/
sdmmc1_dir_pins_b: sdmmc1-dir-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
@@ -129,12 +145,13 @@
drive-push-pull;
bias-pull-up;
};
- pins2{
+ pins2 {
pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
bias-pull-up;
};
};
+ /omit-if-no-ref/
sdmmc2_b4_pins_a: sdmmc2-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
@@ -154,6 +171,7 @@
};
};
+ /omit-if-no-ref/
sdmmc2_b4_pins_b: sdmmc2-b4-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
@@ -173,6 +191,7 @@
};
};
+ /omit-if-no-ref/
sdmmc2_d47_pins_a: sdmmc2-d47-0 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
@@ -185,6 +204,7 @@
};
};
+ /omit-if-no-ref/
sdmmc2_d47_pins_b: sdmmc2-d47-1 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
@@ -197,6 +217,7 @@
};
};
+ /omit-if-no-ref/
sdmmc2_d47_pins_c: sdmmc2-d47-2 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
@@ -209,6 +230,7 @@
};
};
+ /omit-if-no-ref/
sdmmc2_d47_pins_d: sdmmc2-d47-3 {
pins {
pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
@@ -218,6 +240,7 @@
};
};
+ /omit-if-no-ref/
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
@@ -231,6 +254,7 @@
};
};
+ /omit-if-no-ref/
uart4_pins_b: uart4-1 {
pins1 {
pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
@@ -244,6 +268,7 @@
};
};
+ /omit-if-no-ref/
uart7_pins_a: uart7-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
@@ -259,6 +284,7 @@
};
};
+ /omit-if-no-ref/
uart7_pins_b: uart7-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */
@@ -272,6 +298,7 @@
};
};
+ /omit-if-no-ref/
uart7_pins_c: uart7-2 {
pins1 {
pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */
@@ -281,10 +308,11 @@
};
pins2 {
pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */
- bias-disable;
+ bias-pull-up;
};
};
+ /omit-if-no-ref/
uart8_pins_a: uart8-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */
@@ -298,6 +326,7 @@
};
};
+ /omit-if-no-ref/
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@@ -313,6 +342,7 @@
};
};
+ /omit-if-no-ref/
usart2_pins_b: usart2-1 {
pins1 {
pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */
@@ -328,13 +358,14 @@
};
};
+ /omit-if-no-ref/
usart2_pins_c: usart2-2 {
pins1 {
pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */
<STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */
bias-disable;
drive-push-pull;
- slew-rate = <3>;
+ slew-rate = <0>;
};
pins2 {
pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */
@@ -343,6 +374,7 @@
};
};
+ /omit-if-no-ref/
usart3_pins_a: usart3-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */
@@ -356,6 +388,7 @@
};
};
+ /omit-if-no-ref/
usart3_pins_b: usart3-1 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
@@ -371,6 +404,7 @@
};
};
+ /omit-if-no-ref/
usart3_pins_c: usart3-2 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
@@ -386,12 +420,14 @@
};
};
+ /omit-if-no-ref/
usbotg_hs_pins_a: usbotg-hs-0 {
pins {
pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */
};
};
+ /omit-if-no-ref/
usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 {
pins {
pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */
@@ -401,6 +437,7 @@
};
&pinctrl_z {
+ /omit-if-no-ref/
i2c4_pins_a: i2c4-0 {
pins {
pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi
index 869b912..7a22a1c 100644
--- a/fdts/stm32mp151.dtsi
+++ b/fdts/stm32mp151.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -324,9 +324,8 @@
sdmmc1: mmc@58005000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
- reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
+ reg = <0x58005000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC1_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC1_R>;
@@ -339,9 +338,8 @@
sdmmc2: mmc@58007000 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
arm,primecell-periphid = <0x00253180>;
- reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
+ reg = <0x58007000 0x1000>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "cmd_irq";
clocks = <&rcc SDMMC2_K>;
clock-names = "apb_pclk";
resets = <&rcc SDMMC2_R>;
@@ -463,7 +461,7 @@
cfg0_otp: cfg0_otp@0 {
reg = <0x0 0x1>;
};
- part_number_otp: part_number_otp@4 {
+ part_number_otp: part-number-otp@4 {
reg = <0x4 0x1>;
};
monotonic_otp: monotonic_otp@10 {
@@ -523,7 +521,7 @@
};
tamp: tamp@5c00a000 {
- compatible = "st,stm32-tamp", "simple-bus", "syscon", "simple-mfd";
+ compatible = "st,stm32-tamp", "syscon", "simple-mfd";
reg = <0x5c00a000 0x400>;
secure-interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc RTCAPB>;
@@ -540,7 +538,6 @@
ranges = <0 0x50002000 0xa400>;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
- pins-are-numbered;
gpioa: gpio@50002000 {
gpio-controller;
@@ -669,7 +666,6 @@
#size-cells = <1>;
compatible = "st,stm32mp157-z-pinctrl";
ranges = <0 0x54004000 0x400>;
- pins-are-numbered;
interrupt-parent = <&exti>;
st,syscfg = <&exti 0x60 0xff>;
diff --git a/fdts/stm32mp151a-prtt1a.dts b/fdts/stm32mp151a-prtt1a.dts
index be9bdae..3634620 100644
--- a/fdts/stm32mp151a-prtt1a.dts
+++ b/fdts/stm32mp151a-prtt1a.dts
@@ -39,7 +39,9 @@
&qspi {
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
@@ -56,7 +58,7 @@
};
&qspi_bk1_pins_a {
- pins1 {
+ pins {
bias-pull-up;
drive-push-pull;
slew-rate = <1>;
diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts
index a73bef8..b4d5d20 100644
--- a/fdts/stm32mp157a-dk1.dts
+++ b/fdts/stm32mp157a-dk1.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (C) 2019-2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
@@ -15,12 +15,6 @@
model = "STMicroelectronics STM32MP157A-DK1 Discovery Board";
compatible = "st,stm32mp157a-dk1", "st,stm32mp157";
- aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
- };
-
chosen {
stdout-path = "serial0:115200n8";
};
diff --git a/fdts/stm32mp157c-dk2.dts b/fdts/stm32mp157c-dk2.dts
index be8300e..f6f3782 100644
--- a/fdts/stm32mp157c-dk2.dts
+++ b/fdts/stm32mp157c-dk2.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
+ * Copyright (C) 2019-2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
*/
@@ -17,9 +17,6 @@
compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
aliases {
- serial0 = &uart4;
- serial1 = &usart3;
- serial2 = &uart7;
serial3 = &usart2;
};
diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index 63753bd..949c929 100644
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
/dts-v1/;
@@ -16,6 +16,10 @@
model = "STMicroelectronics STM32MP157C eval daughter";
compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
+ aliases {
+ serial0 = &uart4;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -24,10 +28,6 @@
device_type = "memory";
reg = <0xC0000000 0x40000000>;
};
-
- aliases {
- serial0 = &uart4;
- };
};
&bsec {
diff --git a/fdts/stm32mp157c-ev1.dts b/fdts/stm32mp157c-ev1.dts
index 02840a2..e274645 100644
--- a/fdts/stm32mp157c-ev1.dts
+++ b/fdts/stm32mp157c-ev1.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
- * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2023, STMicroelectronics - All Rights Reserved
* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
*/
/dts-v1/;
@@ -11,13 +11,13 @@
model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
aliases {
serial1 = &usart3;
};
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
};
&fmc {
@@ -39,13 +39,15 @@
&qspi {
pinctrl-names = "default";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
- flash0: mx66l51235l@0 {
+ flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
diff --git a/fdts/stm32mp15xx-dhcom-som.dtsi b/fdts/stm32mp15xx-dhcom-som.dtsi
index c9f21b0..7737a44 100644
--- a/fdts/stm32mp15xx-dhcom-som.dtsi
+++ b/fdts/stm32mp15xx-dhcom-som.dtsi
@@ -2,6 +2,7 @@
/*
* Copyright (C) 2019-2020 Marek Vasut <marex@denx.de>
* Copyright (C) 2022 DH electronics GmbH
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
*/
#include "stm32mp15-pinctrl.dtsi"
@@ -169,7 +170,9 @@
&qspi {
pinctrl-names = "default";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/fdts/stm32mp15xx-dhcor-som.dtsi b/fdts/stm32mp15xx-dhcor-som.dtsi
index c241efc..8d829a4 100644
--- a/fdts/stm32mp15xx-dhcor-som.dtsi
+++ b/fdts/stm32mp15xx-dhcor-som.dtsi
@@ -4,6 +4,7 @@
* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
* Copyright (C) 2020 Marek Vasut <marex@denx.de>
* Copyright (C) 2022 DH electronics GmbH
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
*/
#include "stm32mp15-pinctrl.dtsi"
@@ -164,7 +165,9 @@
&qspi {
pinctrl-names = "default";
- pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>;
+ pinctrl-0 = <&qspi_clk_pins_a
+ &qspi_bk1_pins_a
+ &qspi_cs1_pins_a>;
reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi
index 52d4170..f8baa9d 100644
--- a/fdts/stm32mp15xx-dkx.dtsi
+++ b/fdts/stm32mp15xx-dkx.dtsi
@@ -8,6 +8,12 @@
#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
/ {
+ aliases {
+ serial0 = &uart4;
+ serial1 = &usart3;
+ serial2 = &uart7;
+ };
+
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x20000000>;
diff --git a/fdts/stm32mp25-bl2.dtsi b/fdts/stm32mp25-bl2.dtsi
index 7a6bbbe..438a58c 100644
--- a/fdts/stm32mp25-bl2.dtsi
+++ b/fdts/stm32mp25-bl2.dtsi
@@ -2,5 +2,3 @@
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
*/
-
-/omit-if-no-ref/ &usart2_pins_a;
diff --git a/fdts/stm32mp25-pinctrl.dtsi b/fdts/stm32mp25-pinctrl.dtsi
index 8d0eaaf..05876a3 100644
--- a/fdts/stm32mp25-pinctrl.dtsi
+++ b/fdts/stm32mp25-pinctrl.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
+ /omit-if-no-ref/
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */
diff --git a/fdts/stm32mp251.dtsi b/fdts/stm32mp251.dtsi
index 821eb49..f55a3b9 100644
--- a/fdts/stm32mp251.dtsi
+++ b/fdts/stm32mp251.dtsi
@@ -67,7 +67,7 @@
<0x0 0x4ac60000 0x0 0x2000>;
};
- timer: timer {
+ timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
diff --git a/fdts/stm32mp257f-ev1.dts b/fdts/stm32mp257f-ev1.dts
index 916d1e2..b7e92e4 100644
--- a/fdts/stm32mp257f-ev1.dts
+++ b/fdts/stm32mp257f-ev1.dts
@@ -25,7 +25,7 @@
memory@80000000 {
device_type = "memory";
- reg = <0x0 0x80000000 0x1 0x00000000>;
+ reg = <0x0 0x80000000 0x1 0x0>;
};
};
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index c10102a..001fad5 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -1231,7 +1231,9 @@
/* MPAM register definitions */
#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
+#define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62)
#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
+#define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT
#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index bd41fef..cf8da5e 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -159,7 +159,7 @@
}
CREATE_FEATURE_FUNCS_VER(feat_mpam, read_feat_mpam_version, 1U,
- ENABLE_MPAM_FOR_LOWER_ELS)
+ ENABLE_FEAT_MPAM)
/* FEAT_HCX: Extended Hypervisor Configuration Register */
CREATE_FEATURE_FUNCS(feat_hcx, id_aa64mmfr1_el1, ID_AA64MMFR1_EL1_HCX_SHIFT,
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index ebd0e30..e7e9f58 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -63,6 +63,7 @@
#define CTX_IS_IN_EL3 U(0x30)
#define CTX_CPTR_EL3 U(0x38)
#define CTX_ZCR_EL3 U(0x40)
+#define CTX_MPAM3_EL3 U(0x48)
#define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */
/*******************************************************************************
diff --git a/include/lib/extensions/mpam.h b/include/lib/extensions/mpam.h
index e5438ce..170f919 100644
--- a/include/lib/extensions/mpam.h
+++ b/include/lib/extensions/mpam.h
@@ -9,16 +9,18 @@
#include <stdbool.h>
-#if ENABLE_MPAM_FOR_LOWER_ELS
-void mpam_init_el3(void);
+#include <context.h>
+
+#if ENABLE_FEAT_MPAM
+void mpam_enable(cpu_context_t *context);
void mpam_init_el2_unused(void);
#else
-static inline void mpam_init_el3(void)
+static inline void mpam_enable(cpu_context_t *context)
{
}
static inline void mpam_init_el2_unused(void)
{
}
-#endif /* ENABLE_MPAM_FOR_LOWER_ELS */
+#endif /* ENABLE_FEAT_MPAM */
#endif /* MPAM_H */
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 290a93a..758355a 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -350,6 +350,43 @@
#endif /* ENABLE_FEAT_DIT */
.endm /* set_unset_pstate_bits */
+/*-------------------------------------------------------------------------
+ * This macro checks the ENABLE_FEAT_MPAM state, performs ID register
+ * check to see if the platform supports MPAM extension and restores MPAM3
+ * register value if it is FEAT_STATE_ENABLED/FEAT_STATE_CHECKED.
+ *
+ * This is particularly more complicated because we can't check
+ * if the platform supports MPAM by looking for status of a particular bit
+ * in the MDCR_EL3 or CPTR_EL3 register like other extensions.
+ * ------------------------------------------------------------------------
+ */
+
+ .macro restore_mpam3_el3
+#if ENABLE_FEAT_MPAM
+#if ENABLE_FEAT_MPAM == 2
+
+ mrs x8, id_aa64pfr0_el1
+ lsr x8, x8, #(ID_AA64PFR0_MPAM_SHIFT)
+ and x8, x8, #(ID_AA64PFR0_MPAM_MASK)
+ mrs x7, id_aa64pfr1_el1
+ lsr x7, x7, #(ID_AA64PFR1_MPAM_FRAC_SHIFT)
+ and x7, x7, #(ID_AA64PFR1_MPAM_FRAC_MASK)
+ orr x7, x7, x8
+ cbz x7, no_mpam
+#endif
+ /* -----------------------------------------------------------
+ * Restore MPAM3_EL3 register as per context state
+ * Currently we only enable MPAM for NS world and trap to EL3
+ * for MPAM access in lower ELs of Secure and Realm world
+ * -----------------------------------------------------------
+ */
+ ldr x17, [sp, #CTX_EL3STATE_OFFSET + CTX_MPAM3_EL3]
+ msr S3_6_C10_C5_0, x17 /* mpam3_el3 */
+
+no_mpam:
+#endif
+ .endm /* restore_mpam3_el3 */
+
/* ------------------------------------------------------------------
* The following macro is used to save and restore all the general
* purpose and ARMv8.3-PAuth (if enabled) registers.
@@ -573,6 +610,9 @@
isb
msr S3_6_C1_C2_0, x20 /* zcr_el3 */
sve_not_enabled:
+
+ restore_mpam3_el3
+
#endif /* IMAGE_BL31 */
#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 3a7e50f..98cee16 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -482,6 +482,11 @@
}
#endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */
+ if (is_feat_mpam_supported()) {
+ write_ctx_reg(get_el3state_ctx(ctx), CTX_MPAM3_EL3, \
+ MPAM3_EL3_RESET_VAL);
+ }
+
/*
* Populate EL3 state so that we've the right context
* before doing ERET
@@ -578,10 +583,6 @@
sme_init_el3();
}
- if (is_feat_mpam_supported()) {
- mpam_init_el3();
- }
-
if (is_feat_trbe_supported()) {
trbe_init_el3();
}
@@ -621,6 +622,9 @@
sys_reg_trace_enable(ctx);
}
+ if (is_feat_mpam_supported()) {
+ mpam_enable(ctx);
+ }
pmuv3_enable(ctx);
#endif /* IMAGE_BL31 */
}
diff --git a/lib/extensions/mpam/mpam.c b/lib/extensions/mpam/mpam.c
index 6462c97..875ad9c 100644
--- a/lib/extensions/mpam/mpam.c
+++ b/lib/extensions/mpam/mpam.c
@@ -11,14 +11,19 @@
#include <arch_helpers.h>
#include <lib/extensions/mpam.h>
-void mpam_init_el3(void)
+void mpam_enable(cpu_context_t *context)
{
+ u_register_t mpam3_el3;
+
+ mpam3_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_MPAM3_EL3);
+
/*
* Enable MPAM, and disable trapping to EL3 when lower ELs access their
- * own MPAM registers.
+ * own MPAM registers
*/
- write_mpam3_el3(MPAM3_EL3_MPAMEN_BIT);
-
+ mpam3_el3 = (mpam3_el3 | MPAM3_EL3_MPAMEN_BIT) &
+ ~(MPAM3_EL3_TRAPLOWER_BIT);
+ write_ctx_reg(get_el3state_ctx(context), CTX_MPAM3_EL3, mpam3_el3);
}
/*
diff --git a/make_helpers/arch_features.mk b/make_helpers/arch_features.mk
index f90136b..c92b4a5 100644
--- a/make_helpers/arch_features.mk
+++ b/make_helpers/arch_features.mk
@@ -182,25 +182,25 @@
# Build option to enable/disable the Statistical Profiling Extension,
# keep it enabled by default for AArch64.
ifeq (${ARCH},aarch64)
- ENABLE_SPE_FOR_NS ?= 2
+ ENABLE_SPE_FOR_NS ?= 2
else ifeq (${ARCH},aarch32)
- ifdef ENABLE_SPE_FOR_NS
- $(error ENABLE_SPE_FOR_NS is not supported for AArch32)
- else
- ENABLE_SPE_FOR_NS := 0
- endif
+ ifdef ENABLE_SPE_FOR_NS
+ $(error ENABLE_SPE_FOR_NS is not supported for AArch32)
+ else
+ ENABLE_SPE_FOR_NS := 0
+ endif
endif
# Enable SVE for non-secure world by default.
ifeq (${ARCH},aarch64)
- ENABLE_SVE_FOR_NS ?= 2
+ ENABLE_SVE_FOR_NS ?= 2
# SVE is only supported on AArch64 so disable it on AArch32.
else ifeq (${ARCH},aarch32)
- ifdef ENABLE_SVE_FOR_NS
- $(error ENABLE_SVE_FOR_NS is not supported for AArch32)
- else
- ENABLE_SVE_FOR_NS := 0
- endif
+ ifdef ENABLE_SVE_FOR_NS
+ $(error ENABLE_SVE_FOR_NS is not supported for AArch32)
+ else
+ ENABLE_SVE_FOR_NS := 0
+ endif
endif
#----
@@ -214,7 +214,16 @@
AMU_RESTRICT_COUNTERS ?= 0
# Build option to enable MPAM for lower ELs.
-ENABLE_MPAM_FOR_LOWER_ELS ?= 0
+# Enabling it by default
+ifeq (${ARCH},aarch64)
+ ENABLE_FEAT_MPAM ?= 2
+else ifeq (${ARCH},aarch32)
+ ifdef ENABLE_FEAT_MPAM
+ $(error ENABLE_FEAT_MPAM is not supported for AArch32)
+ else
+ ENABLE_FEAT_MPAM := 0
+ endif
+endif
# Include nested virtualization control (Armv8.4-NV) registers in cpu context.
# This must be set to 1 if architecture implements Nested Virtualization
@@ -291,13 +300,13 @@
# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in
# AArch32.
ifeq (${ARCH},aarch64)
- ENABLE_TRBE_FOR_NS ?= 0
+ ENABLE_TRBE_FOR_NS ?= 0
else ifeq (${ARCH},aarch32)
- ifdef ENABLE_TRBE_FOR_NS
- $(error ENABLE_TRBE_FOR_NS is not supported for AArch32)
- else
- ENABLE_TRBE_FOR_NS := 0
- endif
+ ifdef ENABLE_TRBE_FOR_NS
+ $(error ENABLE_TRBE_FOR_NS is not supported for AArch32)
+ else
+ ENABLE_TRBE_FOR_NS := 0
+ endif
endif
#----
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index bd56f30..c71c99a 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -41,7 +41,7 @@
ENABLE_FEAT_ECV := 2
ENABLE_FEAT_FGT := 2
ENABLE_FEAT_HCX := 2
-ENABLE_MPAM_FOR_LOWER_ELS := 2
+ENABLE_FEAT_MPAM := 2
ENABLE_SYS_REG_TRACE_FOR_NS := 2
ENABLE_TRF_FOR_NS := 2
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 72f94b0..165b1610 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -53,7 +53,7 @@
ENABLE_FEAT_AMU := 2
ENABLE_FEAT_AMUv1p1 := 2
ENABLE_FEAT_HCX := 2
- ENABLE_MPAM_FOR_LOWER_ELS := 2
+ ENABLE_FEAT_MPAM := 2
ENABLE_FEAT_RNG := 2
ENABLE_FEAT_TWED := 2
ENABLE_FEAT_GCS := 2
@@ -75,8 +75,8 @@
ifeq (${ENABLE_RME},0)
ENABLE_BRBE_FOR_NS := 2
endif
+ ENABLE_TRBE_FOR_NS := 2
endif
-ENABLE_TRBE_FOR_NS := 2
ENABLE_SYS_REG_TRACE_FOR_NS := 2
ENABLE_FEAT_CSV2_2 := 2
ENABLE_FEAT_DIT := 2
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
index 2a2f559..8696f2a 100644
--- a/plat/mediatek/mt8195/include/platform_def.h
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -133,7 +133,7 @@
* Platform memory map related constants
******************************************************************************/
#define TZRAM_BASE 0x54600000
-#define TZRAM_SIZE 0x00030000
+#define TZRAM_SIZE 0x00040000
/*******************************************************************************
* BL31 specific defines.
diff --git a/plat/st/common/common_rules.mk b/plat/st/common/common_rules.mk
index d2d2fb1..f39caab 100644
--- a/plat/st/common/common_rules.mk
+++ b/plat/st/common/common_rules.mk
@@ -72,7 +72,7 @@
tf-a-%.stm32: tf-a-%.bin ${STM32_DEPS}
@echo
@echo "Generate $@"
- $(eval LOADADDR = $(shell cat $(@:.stm32=.map) | grep RAM | awk '{print $$2}'))
+ $(eval LOADADDR = $(shell cat $(@:.stm32=.map) | grep '^RAM' | awk '{print $$2}'))
$(eval ENTRY = $(shell cat $(@:.stm32=.map) | grep "__BL2_IMAGE_START" | awk '{print $$1}'))
${Q}${STM32IMAGE} -s $< -d $@ \
-l $(LOADADDR) -e ${ENTRY} \
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index 194672e..ddc5289 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -62,7 +62,7 @@
STM32_HEADER_VERSION_MINOR:= 0
# Add OP-TEE reserved shared memory area in mapping
-STM32MP15_OPTEE_RSV_SHM := 1
+STM32MP15_OPTEE_RSV_SHM := 0
$(eval $(call add_defines,STM32MP15_OPTEE_RSV_SHM))
STM32MP_CRYPTO_ROM_LIB := 1
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 0fa6c73..6530957 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -427,7 +427,7 @@
/* OTP labels */
#define CFG0_OTP "cfg0_otp"
-#define PART_NUMBER_OTP "part_number_otp"
+#define PART_NUMBER_OTP "part-number-otp"
#if STM32MP15
#define PACKAGE_OTP "package_otp"
#endif
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index d830403..066571e 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -110,6 +110,12 @@
spmd_spmc_id_get());
write_ctx_reg(gpregs, CTX_GPREG_X2, BIT(31) | target_func);
write_ctx_reg(gpregs, CTX_GPREG_X3, message);
+
+ /* Zero out x4-x7 for the direct request emitted towards the SPMC. */
+ write_ctx_reg(gpregs, CTX_GPREG_X4, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X5, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X6, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X7, 0);
}
@@ -945,6 +951,21 @@
SPMD_FWK_MSG_FFA_VERSION_REQ,
input_version);
+ /*
+ * Ensure x8-x17 NS GP register values are untouched when returning
+ * from the SPMC.
+ */
+ write_ctx_reg(gpregs, CTX_GPREG_X8, SMC_GET_GP(handle, CTX_GPREG_X8));
+ write_ctx_reg(gpregs, CTX_GPREG_X9, SMC_GET_GP(handle, CTX_GPREG_X9));
+ write_ctx_reg(gpregs, CTX_GPREG_X10, SMC_GET_GP(handle, CTX_GPREG_X10));
+ write_ctx_reg(gpregs, CTX_GPREG_X11, SMC_GET_GP(handle, CTX_GPREG_X11));
+ write_ctx_reg(gpregs, CTX_GPREG_X12, SMC_GET_GP(handle, CTX_GPREG_X12));
+ write_ctx_reg(gpregs, CTX_GPREG_X13, SMC_GET_GP(handle, CTX_GPREG_X13));
+ write_ctx_reg(gpregs, CTX_GPREG_X14, SMC_GET_GP(handle, CTX_GPREG_X14));
+ write_ctx_reg(gpregs, CTX_GPREG_X15, SMC_GET_GP(handle, CTX_GPREG_X15));
+ write_ctx_reg(gpregs, CTX_GPREG_X16, SMC_GET_GP(handle, CTX_GPREG_X16));
+ write_ctx_reg(gpregs, CTX_GPREG_X17, SMC_GET_GP(handle, CTX_GPREG_X17));
+
rc = spmd_spm_core_sync_entry(ctx);
if ((rc != 0ULL) ||
@@ -960,6 +981,14 @@
}
/*
+ * x0-x4 are updated by spmd_smc_forward below.
+ * Zero out x5-x7 in the FFA_VERSION response.
+ */
+ write_ctx_reg(gpregs, CTX_GPREG_X5, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X6, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X7, 0);
+
+ /*
* Return here after SPMC has handled FFA_VERSION.
* The returned SPMC version is held in X3.
* Forward this version in X0 to the non-secure caller.
diff --git a/services/std_svc/spmd/spmd_pm.c b/services/std_svc/spmd/spmd_pm.c
index a2704dd..fd89c81 100644
--- a/services/std_svc/spmd/spmd_pm.c
+++ b/services/std_svc/spmd/spmd_pm.c
@@ -122,8 +122,20 @@
assert(ctx->state != SPMC_STATE_OFF);
/* Build an SPMD to SPMC direct message request. */
- spmd_build_spmc_message(get_gpregs_ctx(&ctx->cpu_ctx),
- FFA_FWK_MSG_PSCI, PSCI_CPU_OFF);
+ gp_regs_t *gpregs = get_gpregs_ctx(&ctx->cpu_ctx);
+ spmd_build_spmc_message(gpregs, FFA_FWK_MSG_PSCI, PSCI_CPU_OFF);
+
+ /* Clear remaining x8 - x17 at EL3/SEL2 or EL3/SEL1 boundary. */
+ write_ctx_reg(gpregs, CTX_GPREG_X8, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X9, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X10, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X11, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X12, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X13, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X14, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X15, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X16, 0);
+ write_ctx_reg(gpregs, CTX_GPREG_X17, 0);
rc = spmd_spm_core_sync_entry(ctx);
if (rc != 0ULL) {