Merge "feat(qemu): add A55 cpu support for virt" into integration
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 9426ac7..0ab0e82 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -593,15 +593,15 @@
* As the BL31 image size appears to be increased when built with the ENABLE_PIE
* option, set BL2 base address to have enough space for BL31 in Trusted SRAM.
*/
-#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
- (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
- 0x3000)
+#define BL2_OFFSET (0x5000)
#else
/* Put BL2 towards the middle of the Trusted SRAM */
-#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
- (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
- 0x2000)
+#define BL2_OFFSET (0x2000)
#endif /* ENABLE_PIE */
+
+#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
+ (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
+ BL2_OFFSET)
#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
#else
diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
index 534a175..51dda9e 100644
--- a/plat/arm/board/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c
@@ -65,25 +65,6 @@
/* Disable coherency if this cluster is to be turned off */
fvp_interconnect_disable();
-#if HW_ASSISTED_COHERENCY
- uint32_t reg;
-
- /*
- * If we have determined this core to be the last man standing and we
- * intend to power down the cluster proactively, we provide a hint to
- * the power controller that cluster power is not required when all
- * cores are powered down.
- * Note that this is only an advisory to power controller and is supported
- * by SoCs with DynamIQ Shared Units only.
- */
- reg = read_clusterpwrdn();
-
- /* Clear and set bit 0 : Cluster power not required */
- reg &= ~DSU_CLUSTER_PWR_MASK;
- reg |= DSU_CLUSTER_PWR_OFF;
- write_clusterpwrdn(reg);
-#endif
-
/* Program the power controller to turn the cluster off */
fvp_pwrc_write_pcoffr(mpidr);
}
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index d9fe24f..826fca2 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -168,8 +168,13 @@
# define MAX_XLAT_TABLES 6
# endif
#elif !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES 12
-# define MAX_XLAT_TABLES 6
+# if ENABLE_RME && defined(IMAGE_BL2)
+# define PLAT_ARM_MMAP_ENTRIES 12
+# define MAX_XLAT_TABLES 6
+# else
+# define PLAT_ARM_MMAP_ENTRIES 11
+# define MAX_XLAT_TABLES 5
+# endif /* (IMAGE_BL2 && ENABLE_RME) */
#else
# define PLAT_ARM_MMAP_ENTRIES 12
# if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index 3222226..bb64e73 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -131,28 +131,8 @@
plat_arm_gic_cpuif_disable();
/* Cluster is to be turned off, so disable coherency */
- if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) {
+ if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF)
plat_arm_interconnect_exit_coherency();
-
-#if HW_ASSISTED_COHERENCY
- uint32_t reg;
-
- /*
- * If we have determined this core to be the last man standing and we
- * intend to power down the cluster proactively, we provide a hint to
- * the power controller that cluster power is not required when all
- * cores are powered down.
- * Note that this is only an advisory to power controller and is supported
- * by SoCs with DynamIQ Shared Units only.
- */
- reg = read_clusterpwrdn();
-
- /* Clear and set bit 0 : Cluster power not required */
- reg &= ~DSU_CLUSTER_PWR_MASK;
- reg |= DSU_CLUSTER_PWR_OFF;
- write_clusterpwrdn(reg);
-#endif
- }
}
/*******************************************************************************
diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
index b341d25..618e6c9 100644
--- a/plat/qemu/common/common.mk
+++ b/plat/qemu/common/common.mk
@@ -21,12 +21,25 @@
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/cortex_a76.S \
+ lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/qemu_max.S
PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
+
+# Cpu core architecture level:
+# v8.0: a53, a57, a72
+# v8.2: a76, n1
+# v8.4: v1
+# v9.0: a710
+#
+# let treat v9.0 as v8.5 as they share cpu features
+# https://developer.arm.com/documentation/102378/0201/Armv8-x-and-Armv9-x-extensions-and-features
+
+ARM_ARCH_MAJOR := 8
+ARM_ARCH_MINOR := 5
endif
PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \