commit 8bed83dd8ad19e1768f313f3412d40e264ca9ebb
author Patrick Delaunay <patrick.delaunay@foss.st.com> Tue Apr 13 14:44:48 2021 +0200
committer Yann Gautier <yann.gautier@st.com> Tue Jul 05 17:03:19 2022 +0200
tree 0448c03e7fb8315d049392aea4fb22007789cc76
parent 94fbb15a0b36304e47bc9a2cf4648520b34d80dd

feat(stm32mp13): change BL33 memory mapping

U-Boot is loaded at the beginning of the DDR:
STM32MP_DDR_BASE = 0xC0000000.

This patch remove the need to use the 0x100000 offset, reserved
on STM32MP15 for flashlayout.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Change-Id: I8d0a93f4db411cf59838e635a315c729cccee269

plat/st/stm32mp1/stm32mp1_def.h

diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 7e0745a..bd25321 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -182,7 +182,12 @@
  #endif
 #endif
 
+#if STM32MP13
+#define STM32MP_BL33_BASE		STM32MP_DDR_BASE
+#endif
+#if STM32MP15
 #define STM32MP_BL33_BASE		(STM32MP_DDR_BASE + U(0x100000))
+#endif
 #define STM32MP_BL33_MAX_SIZE		U(0x400000)
 
 /* Define maximum page size for NAND devices */