feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA
This patch is used to enable pinmux, peripheral and handoff support
for Agilex5 SoC FPGA.
1. Initial handoff bring up
2. Added power manager handoff implementation
3. Added sdram handoff implementation
4. Updated product name -> Agilex5
5. Updated register address based on y22ww52.2 RTL
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I4b0176bc86c57823127bf41086306015d702577d
diff --git a/plat/intel/soc/agilex5/include/agilex5_pinmux.h b/plat/intel/soc/agilex5/include/agilex5_pinmux.h
new file mode 100644
index 0000000..8a8e8c7
--- /dev/null
+++ b/plat/intel/soc/agilex5/include/agilex5_pinmux.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef AGX5_PINMUX_H
+#define AGX5_PINMUX_H
+
+/* PINMUX REGISTER ADDRESS */
+#define AGX5_PINMUX_PIN0SEL 0x10d13000
+#define AGX5_PINMUX_IO0CTRL 0x10d13130
+#define AGX5_PINMUX_EMAC0_USEFPGA 0x10d13300
+#define AGX5_PINMUX_IO0_DELAY 0x10d13400
+#define AGX5_PERIPHERAL 0x10d14044
+
+#include "socfpga_handoff.h"
+
+/* PINMUX DEFINE */
+#define PINMUX_HANDOFF_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define PINMUX_HANDOFF_CONFIG_ADDR 0xbeec
+#define PINMUX_HANDOFF_CONFIG_VAL 0x7e000
+
+/* Macros */
+#define SOCFPGA_PINMUX_SEL_NAND (0x03)
+#define SOCFPGA_PINMUX_PIN0SEL (0x00)
+#define SOCFPGA_PINMUX_PIN1SEL (0x04)
+#define SOCFPGA_PINMUX_PIN2SEL (0x08)
+#define SOCFPGA_PINMUX_PIN3SEL (0x0C)
+#define SOCFPGA_PINMUX_PIN4SEL (0x10)
+#define SOCFPGA_PINMUX_PIN5SEL (0x14)
+#define SOCFPGA_PINMUX_PIN6SEL (0x18)
+#define SOCFPGA_PINMUX_PIN7SEL (0x1C)
+#define SOCFPGA_PINMUX_PIN8SEL (0x20)
+#define SOCFPGA_PINMUX_PIN9SEL (0x24)
+#define SOCFPGA_PINMUX_PIN10SEL (0x28)
+#define SOCFPGA_PINMUX_PIN11SEL (0x2C)
+#define SOCFPGA_PINMUX_PIN12SEL (0x30)
+#define SOCFPGA_PINMUX_PIN13SEL (0x34)
+#define SOCFPGA_PINMUX_PIN14SEL (0x38)
+#define SOCFPGA_PINMUX_PIN15SEL (0x3C)
+#define SOCFPGA_PINMUX_PIN16SEL (0x40)
+#define SOCFPGA_PINMUX_PIN17SEL (0x44)
+#define SOCFPGA_PINMUX_PIN18SEL (0x48)
+#define SOCFPGA_PINMUX_PIN19SEL (0x4C)
+#define SOCFPGA_PINMUX_PIN20SEL (0x50)
+#define SOCFPGA_PINMUX_PIN21SEL (0x54)
+#define SOCFPGA_PINMUX_PIN22SEL (0x58)
+#define SOCFPGA_PINMUX_PIN23SEL (0x5C)
+#define SOCFPGA_PINMUX_PIN24SEL (0x60)
+#define SOCFPGA_PINMUX_PIN25SEL (0x64)
+#define SOCFPGA_PINMUX_PIN26SEL (0x68)
+#define SOCFPGA_PINMUX_PIN27SEL (0x6C)
+#define SOCFPGA_PINMUX_PIN28SEL (0x70)
+#define SOCFPGA_PINMUX_PIN29SEL (0x74)
+#define SOCFPGA_PINMUX_PIN30SEL (0x78)
+#define SOCFPGA_PINMUX_PIN31SEL (0x7C)
+#define SOCFPGA_PINMUX_PIN32SEL (0x80)
+#define SOCFPGA_PINMUX_PIN33SEL (0x84)
+#define SOCFPGA_PINMUX_PIN34SEL (0x88)
+#define SOCFPGA_PINMUX_PIN35SEL (0x8C)
+#define SOCFPGA_PINMUX_PIN36SEL (0x90)
+#define SOCFPGA_PINMUX_PIN37SEL (0x94)
+#define SOCFPGA_PINMUX_PIN38SEL (0x98)
+#define SOCFPGA_PINMUX_PIN39SEL (0x9C)
+#define SOCFPGA_PINMUX_PIN40SEL (0x100)
+#define SOCFPGA_PINMUX_PIN41SEL (0x104)
+#define SOCFPGA_PINMUX_PIN42SEL (0x108)
+#define SOCFPGA_PINMUX_PIN43SEL (0x10C)
+#define SOCFPGA_PINMUX_PIN44SEL (0x110)
+#define SOCFPGA_PINMUX_PIN45SEL (0x114)
+#define SOCFPGA_PINMUX_PIN46SEL (0x118)
+#define SOCFPGA_PINMUX_PIN47SEL (0x11C)
+
+#define SOCFPGA_PINMUX_IO0CTRL (0x00)
+#define SOCFPGA_PINMUX_IO1CTRL (0x04)
+#define SOCFPGA_PINMUX_IO2CTRL (0x08)
+#define SOCFPGA_PINMUX_IO3CTRL (0x0C)
+#define SOCFPGA_PINMUX_IO4CTRL (0x10)
+#define SOCFPGA_PINMUX_IO5CTRL (0x14)
+#define SOCFPGA_PINMUX_IO6CTRL (0x18)
+#define SOCFPGA_PINMUX_IO7CTRL (0x1C)
+#define SOCFPGA_PINMUX_IO8CTRL (0x20)
+#define SOCFPGA_PINMUX_IO9CTRL (0x24)
+#define SOCFPGA_PINMUX_IO10CTRL (0x28)
+#define SOCFPGA_PINMUX_IO11CTRL (0x2C)
+#define SOCFPGA_PINMUX_IO12CTRL (0x30)
+#define SOCFPGA_PINMUX_IO13CTRL (0x34)
+#define SOCFPGA_PINMUX_IO14CTRL (0x38)
+#define SOCFPGA_PINMUX_IO15CTRL (0x3C)
+#define SOCFPGA_PINMUX_IO16CTRL (0x40)
+#define SOCFPGA_PINMUX_IO17CTRL (0x44)
+#define SOCFPGA_PINMUX_IO18CTRL (0x48)
+#define SOCFPGA_PINMUX_IO19CTRL (0x4C)
+#define SOCFPGA_PINMUX_IO20CTRL (0x50)
+#define SOCFPGA_PINMUX_IO21CTRL (0x54)
+#define SOCFPGA_PINMUX_IO22CTRL (0x58)
+#define SOCFPGA_PINMUX_IO23CTRL (0x5C)
+#define SOCFPGA_PINMUX_IO24CTRL (0x60)
+#define SOCFPGA_PINMUX_IO25CTRL (0x64)
+#define SOCFPGA_PINMUX_IO26CTRL (0x68)
+#define SOCFPGA_PINMUX_IO27CTRL (0x6C)
+#define SOCFPGA_PINMUX_IO28CTRL (0xD0)
+#define SOCFPGA_PINMUX_IO29CTRL (0xD4)
+#define SOCFPGA_PINMUX_IO30CTRL (0xD8)
+#define SOCFPGA_PINMUX_IO31CTRL (0xDC)
+#define SOCFPGA_PINMUX_IO32CTRL (0xE0)
+#define SOCFPGA_PINMUX_IO33CTRL (0xE4)
+#define SOCFPGA_PINMUX_IO34CTRL (0xE8)
+#define SOCFPGA_PINMUX_IO35CTRL (0xEC)
+#define SOCFPGA_PINMUX_IO36CTRL (0xF0)
+#define SOCFPGA_PINMUX_IO37CTRL (0xF4)
+#define SOCFPGA_PINMUX_IO38CTRL (0xF8)
+#define SOCFPGA_PINMUX_IO39CTRL (0xFC)
+#define SOCFPGA_PINMUX_IO40CTRL (0x100)
+#define SOCFPGA_PINMUX_IO41CTRL (0x104)
+#define SOCFPGA_PINMUX_IO42CTRL (0x108)
+#define SOCFPGA_PINMUX_IO43CTRL (0x10C)
+#define SOCFPGA_PINMUX_IO44CTRL (0x110)
+#define SOCFPGA_PINMUX_IO45CTRL (0x114)
+#define SOCFPGA_PINMUX_IO46CTRL (0x118)
+#define SOCFPGA_PINMUX_IO47CTRL (0x11C)
+
+#define SOCFPGA_PINMUX_EMAC0_USEFPGA (0x00)
+#define SOCFPGA_PINMUX_EMAC1_USEFPGA (0x04)
+#define SOCFPGA_PINMUX_EMAC2_USEFPGA (0x08)
+#define SOCFPGA_PINMUX_I2C0_USEFPGA (0x0C)
+#define SOCFPGA_PINMUX_I2C1_USEFPGA (0x10)
+#define SOCFPGA_PINMUX_I2C_EMAC0_USEFPGA (0x14)
+#define SOCFPGA_PINMUX_I2C_EMAC1_USEFPGA (0x18)
+#define SOCFPGA_PINMUX_I2C_EMAC2_USEFPGA (0x1C)
+#define SOCFPGA_PINMUX_NAND_USEFPGA (0x20)
+#define SOCFPGA_PINMUX_SPIM0_USEFPGA (0x28)
+#define SOCFPGA_PINMUX_SPIM1_USEFPGA (0x2C)
+#define SOCFPGA_PINMUX_SPIS0_USEFPGA (0x30)
+#define SOCFPGA_PINMUX_SPIS1_USEFPGA (0x34)
+#define SOCFPGA_PINMUX_UART0_USEFPGA (0x38)
+#define SOCFPGA_PINMUX_UART1_USEFPGA (0x3C)
+#define SOCFPGA_PINMUX_MDIO0_USEFPGA (0x40)
+#define SOCFPGA_PINMUX_MDIO1_USEFPGA (0x44)
+#define SOCFPGA_PINMUX_MDIO2_USEFPGA (0x48)
+#define SOCFPGA_PINMUX_JTAG_USEFPGA (0x50)
+#define SOCFPGA_PINMUX_SDMMC_USEFPGA (0x54)
+
+#define SOCFPGA_PINMUX_IO0DELAY (0x00)
+#define SOCFPGA_PINMUX_IO1DELAY (0x04)
+#define SOCFPGA_PINMUX_IO2DELAY (0x08)
+#define SOCFPGA_PINMUX_IO3DELAY (0x0C)
+#define SOCFPGA_PINMUX_IO4DELAY (0x10)
+#define SOCFPGA_PINMUX_IO5DELAY (0x14)
+#define SOCFPGA_PINMUX_IO6DELAY (0x18)
+#define SOCFPGA_PINMUX_IO7DELAY (0x1C)
+#define SOCFPGA_PINMUX_IO8DELAY (0x20)
+#define SOCFPGA_PINMUX_IO9DELAY (0x24)
+#define SOCFPGA_PINMUX_IO10DELAY (0x28)
+#define SOCFPGA_PINMUX_IO11DELAY (0x2C)
+#define SOCFPGA_PINMUX_IO12DELAY (0x30)
+#define SOCFPGA_PINMUX_IO13DELAY (0x34)
+#define SOCFPGA_PINMUX_IO14DELAY (0x38)
+#define SOCFPGA_PINMUX_IO15DELAY (0x3C)
+#define SOCFPGA_PINMUX_IO16DELAY (0x40)
+#define SOCFPGA_PINMUX_IO17DELAY (0x44)
+#define SOCFPGA_PINMUX_IO18DELAY (0x48)
+#define SOCFPGA_PINMUX_IO19DELAY (0x4C)
+#define SOCFPGA_PINMUX_IO20DELAY (0x50)
+#define SOCFPGA_PINMUX_IO21DELAY (0x54)
+#define SOCFPGA_PINMUX_IO22DELAY (0x58)
+#define SOCFPGA_PINMUX_IO23DELAY (0x5C)
+#define SOCFPGA_PINMUX_IO24DELAY (0x60)
+#define SOCFPGA_PINMUX_IO25DELAY (0x64)
+#define SOCFPGA_PINMUX_IO26DELAY (0x68)
+#define SOCFPGA_PINMUX_IO27DELAY (0x6C)
+#define SOCFPGA_PINMUX_IO28DELAY (0x70)
+#define SOCFPGA_PINMUX_IO29DELAY (0x74)
+#define SOCFPGA_PINMUX_IO30DELAY (0x78)
+#define SOCFPGA_PINMUX_IO31DELAY (0x7C)
+#define SOCFPGA_PINMUX_IO32DELAY (0x80)
+#define SOCFPGA_PINMUX_IO33DELAY (0x84)
+#define SOCFPGA_PINMUX_IO34DELAY (0x88)
+#define SOCFPGA_PINMUX_IO35DELAY (0x8C)
+#define SOCFPGA_PINMUX_IO36DELAY (0x90)
+#define SOCFPGA_PINMUX_IO37DELAY (0x94)
+#define SOCFPGA_PINMUX_IO38DELAY (0x98)
+#define SOCFPGA_PINMUX_IO39DELAY (0x9C)
+#define SOCFPGA_PINMUX_IO40DELAY (0xA0)
+#define SOCFPGA_PINMUX_IO41DELAY (0xA4)
+#define SOCFPGA_PINMUX_IO42DELAY (0xA8)
+#define SOCFPGA_PINMUX_IO43DELAY (0xAC)
+#define SOCFPGA_PINMUX_IO44DELAY (0xB0)
+#define SOCFPGA_PINMUX_IO45DELAY (0xB4)
+#define SOCFPGA_PINMUX_IO46DELAY (0xB8)
+#define SOCFPGA_PINMUX_IO47DELAY (0xBC)
+
+#define SOCFPGA_PINMUX_I3C0_USEFPGA (0xC0)
+#define SOCFPGA_PINMUX_I3C1_USEFPGA (0xC4)
+
+#define SOCFPGA_PINMUX(_reg) (SOCFPGA_PINMUX_REG_BASE \
+ + (SOCFPGA_PINMUX_##_reg))
+
+void config_pinmux(handoff *handoff);
+void config_peripheral(handoff *handoff);
+#endif
diff --git a/plat/intel/soc/agilex5/soc/agilex5_pinmux.c b/plat/intel/soc/agilex5/soc/agilex5_pinmux.c
new file mode 100644
index 0000000..50d9e36
--- /dev/null
+++ b/plat/intel/soc/agilex5/soc/agilex5_pinmux.c
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+
+#include "agilex5_pinmux.h"
+#include "agilex5_system_manager.h"
+
+const uint32_t sysmgr_pinmux_array_sel[] = {
+ 0x00000000, 0x00000001, /* usb */
+ 0x00000004, 0x00000001,
+ 0x00000008, 0x00000001,
+ 0x0000000c, 0x00000001,
+ 0x00000010, 0x00000001,
+ 0x00000014, 0x00000001,
+ 0x00000018, 0x00000001,
+ 0x0000001c, 0x00000001,
+ 0x00000020, 0x00000001,
+ 0x00000024, 0x00000001,
+ 0x00000028, 0x00000001,
+ 0x0000002c, 0x00000001,
+ 0x00000030, 0x00000000, /* emac0 */
+ 0x00000034, 0x00000000,
+ 0x00000038, 0x00000000,
+ 0x0000003c, 0x00000000,
+ 0x00000040, 0x00000000,
+ 0x00000044, 0x00000000,
+ 0x00000048, 0x00000000,
+ 0x0000004c, 0x00000000,
+ 0x00000050, 0x00000000,
+ 0x00000054, 0x00000000,
+ 0x00000058, 0x00000000,
+ 0x0000005c, 0x00000000,
+ 0x00000060, 0x00000008, /* gpio1 */
+ 0x00000064, 0x00000008,
+ 0x00000068, 0x00000005, /* uart0 tx */
+ 0x0000006c, 0x00000005, /* uart 0 rx */
+ 0x00000070, 0x00000008, /* gpio */
+ 0x00000074, 0x00000008,
+ 0x00000078, 0x00000004, /* i2c1 */
+ 0x0000007c, 0x00000004,
+ 0x00000080, 0x00000007, /* jtag */
+ 0x00000084, 0x00000007,
+ 0x00000088, 0x00000007,
+ 0x0000008c, 0x00000007,
+ 0x00000090, 0x00000001, /* sdmmc data0 */
+ 0x00000094, 0x00000001,
+ 0x00000098, 0x00000001,
+ 0x0000009c, 0x00000001,
+ 0x00000100, 0x00000001,
+ 0x00000104, 0x00000001, /* sdmmc.data3 */
+ 0x00000108, 0x00000008, /* loan */
+ 0x0000010c, 0x00000008, /* gpio */
+ 0x00000110, 0x00000008,
+ 0x00000114, 0x00000008, /* gpio1.io21 */
+ 0x00000118, 0x00000005, /* mdio0.mdio */
+ 0x0000011c, 0x00000005 /* mdio0.mdc */
+};
+
+const uint32_t sysmgr_pinmux_array_ctrl[] = {
+ 0x00000000, 0x00502c38, /* Q1_1 */
+ 0x00000004, 0x00102c38,
+ 0x00000008, 0x00502c38,
+ 0x0000000c, 0x00502c38,
+ 0x00000010, 0x00502c38,
+ 0x00000014, 0x00502c38,
+ 0x00000018, 0x00502c38,
+ 0x0000001c, 0x00502c38,
+ 0x00000020, 0x00502c38,
+ 0x00000024, 0x00502c38,
+ 0x00000028, 0x00502c38,
+ 0x0000002c, 0x00502c38,
+ 0x00000030, 0x00102c38, /* Q2_1 */
+ 0x00000034, 0x00102c38,
+ 0x00000038, 0x00502c38,
+ 0x0000003c, 0x00502c38,
+ 0x00000040, 0x00102c38,
+ 0x00000044, 0x00102c38,
+ 0x00000048, 0x00502c38,
+ 0x0000004c, 0x00502c38,
+ 0x00000050, 0x00102c38,
+ 0x00000054, 0x00102c38,
+ 0x00000058, 0x00502c38,
+ 0x0000005c, 0x00502c38,
+ 0x00000060, 0x00502c38, /* Q3_1 */
+ 0x00000064, 0x00502c38,
+ 0x00000068, 0x00102c38,
+ 0x0000006c, 0x00502c38,
+ 0x000000d0, 0x00502c38,
+ 0x000000d4, 0x00502c38,
+ 0x000000d8, 0x00542c38,
+ 0x000000dc, 0x00542c38,
+ 0x000000e0, 0x00502c38,
+ 0x000000e4, 0x00502c38,
+ 0x000000e8, 0x00102c38,
+ 0x000000ec, 0x00502c38,
+ 0x000000f0, 0x00502c38, /* Q4_1 */
+ 0x000000f4, 0x00502c38,
+ 0x000000f8, 0x00102c38,
+ 0x000000fc, 0x00502c38,
+ 0x00000100, 0x00502c38,
+ 0x00000104, 0x00502c38,
+ 0x00000108, 0x00102c38,
+ 0x0000010c, 0x00502c38,
+ 0x00000110, 0x00502c38,
+ 0x00000114, 0x00502c38,
+ 0x00000118, 0x00542c38,
+ 0x0000011c, 0x00102c38
+};
+
+const uint32_t sysmgr_pinmux_array_fpga[] = {
+ 0x00000000, 0x00000000,
+ 0x00000004, 0x00000000,
+ 0x00000008, 0x00000000,
+ 0x0000000c, 0x00000000,
+ 0x00000010, 0x00000000,
+ 0x00000014, 0x00000000,
+ 0x00000018, 0x00000000,
+ 0x0000001c, 0x00000000,
+ 0x00000020, 0x00000000,
+ 0x00000028, 0x00000000,
+ 0x0000002c, 0x00000000,
+ 0x00000030, 0x00000000,
+ 0x00000034, 0x00000000,
+ 0x00000038, 0x00000000,
+ 0x0000003c, 0x00000000,
+ 0x00000040, 0x00000000,
+ 0x00000044, 0x00000000,
+ 0x00000048, 0x00000000,
+ 0x00000050, 0x00000000,
+ 0x00000054, 0x00000000,
+ 0x00000058, 0x0000002a
+};
+
+const uint32_t sysmgr_pinmux_array_iodelay[] = {
+ 0x00000000, 0x00000000,
+ 0x00000004, 0x00000000,
+ 0x00000008, 0x00000000,
+ 0x0000000c, 0x00000000,
+ 0x00000010, 0x00000000,
+ 0x00000014, 0x00000000,
+ 0x00000018, 0x00000000,
+ 0x0000001c, 0x00000000,
+ 0x00000020, 0x00000000,
+ 0x00000024, 0x00000000,
+ 0x00000028, 0x00000000,
+ 0x0000002c, 0x00000000,
+ 0x00000030, 0x00000000,
+ 0x00000034, 0x00000000,
+ 0x00000038, 0x00000000,
+ 0x0000003c, 0x00000000,
+ 0x00000040, 0x00000000,
+ 0x00000044, 0x00000000,
+ 0x00000048, 0x00000000,
+ 0x0000004c, 0x00000000,
+ 0x00000050, 0x00000000,
+ 0x00000054, 0x00000000,
+ 0x00000058, 0x00000000,
+ 0x0000005c, 0x00000000,
+ 0x00000060, 0x00000000,
+ 0x00000064, 0x00000000,
+ 0x00000068, 0x00000000,
+ 0x0000006c, 0x00000000,
+ 0x00000070, 0x00000000,
+ 0x00000074, 0x00000000,
+ 0x00000078, 0x00000000,
+ 0x0000007c, 0x00000000,
+ 0x00000080, 0x00000000,
+ 0x00000084, 0x00000000,
+ 0x00000088, 0x00000000,
+ 0x0000008c, 0x00000000,
+ 0x00000090, 0x00000000,
+ 0x00000094, 0x00000000,
+ 0x00000098, 0x00000000,
+ 0x0000009c, 0x00000000,
+ 0x00000100, 0x00000000,
+ 0x00000104, 0x00000000,
+ 0x00000108, 0x00000000,
+ 0x0000010c, 0x00000000,
+ 0x00000110, 0x00000000,
+ 0x00000114, 0x00000000,
+ 0x00000118, 0x00000000,
+ 0x0000011c, 0x00000000
+};
+
+void config_fpgaintf_mod(void)
+{
+ mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), 1<<8);
+}
+
+void config_pinmux(handoff *hoff_ptr)
+{
+ unsigned int i;
+
+ mmio_write_32(PINMUX_HANDOFF_CONFIG_ADDR, PINMUX_HANDOFF_CONFIG_VAL);
+ for (i = 0; i < PINMUX_HANDOFF_ARRAY_SIZE(hoff_ptr->pinmux_sel_array); i += 2) {
+ mmio_write_32(AGX5_PINMUX_PIN0SEL +
+ hoff_ptr->pinmux_sel_array[i],
+ hoff_ptr->pinmux_sel_array[i + 1]);
+ }
+
+ config_fpgaintf_mod();
+}
+
+void config_peripheral(handoff *hoff_ptr)
+{
+
+ // TODO: This need to be update due to peripheral_pwr_gate_array handoff change
+ // Pending SDM to pass over handoff data
+ // unsigned int i;
+
+ // for (i = 0; i < 4; i += 2) {
+ // mmio_write_32(AGX_EDGE_PERIPHERAL +
+ // hoff_ptr->peripheral_pwr_gate_array[i],
+ // hoff_ptr->peripheral_pwr_gate_array[i+1]);
+ // }
+
+
+ // TODO: This need to be update due to peripheral_pwr_gate_array handoff change
+ mmio_write_32(AGX5_PERIPHERAL,
+ hoff_ptr->peripheral_pwr_gate_array);
+}
diff --git a/plat/intel/soc/common/include/socfpga_handoff.h b/plat/intel/soc/common/include/socfpga_handoff.h
index ba0f7f3..b2913c7 100644
--- a/plat/intel/soc/common/include/socfpga_handoff.h
+++ b/plat/intel/soc/common/include/socfpga_handoff.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,13 +7,15 @@
#ifndef HANDOFF_H
#define HANDOFF_H
-#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
-#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
-#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
-#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
-#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */
-#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
-#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
+#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
+#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
+#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
+#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
+#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */
+#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
+#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
+#define HANDOFF_MAGIC_PERIPHERAL 0x50455249 /* PERIPHERAL */
+#define HANDOFF_MAGIC_DDR 0x5344524d /* DDR */
#include <socfpga_plat_def.h>
@@ -39,8 +41,9 @@
uint32_t pinmux_fpga_magic;
uint32_t pinmux_fpga_length;
uint32_t _pad_0x338_0x340[2];
- uint32_t pinmux_fpga_array[42]; /* offset, value */
- uint32_t _pad_0x3e8_0x3f0[2];
+ uint32_t pinmux_fpga_array[44]; /* offset, value */
+ /* TODO: Temp remove due to add in extra handoff data */
+ // uint32_t _pad_0x3e8_0x3f0[2];
/* pinmux configuration - io delay */
uint32_t pinmux_delay_magic;
@@ -49,7 +52,6 @@
uint32_t pinmux_iodelay_array[96]; /* offset, value */
/* clock configuration */
-
#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
uint32_t clock_magic;
uint32_t clock_length;
@@ -120,16 +122,68 @@
uint32_t hps_osc_clk_h;
uint32_t fpga_clk_hz;
uint32_t _pad_0x604_0x610[3];
+#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ uint32_t clock_magic;
+ uint32_t clock_length;
+ uint32_t _pad_0x588_0x590[2];
+ uint32_t main_pll_nocclk;
+ uint32_t main_pll_nocdiv;
+ uint32_t main_pll_pllglob;
+ uint32_t main_pll_fdbck;
+ uint32_t main_pll_pllc0;
+ uint32_t main_pll_pllc1;
+ uint32_t main_pll_pllc2;
+ uint32_t main_pll_pllc3;
+ uint32_t main_pll_pllm;
+ uint32_t per_pll_emacctl;
+ uint32_t per_pll_gpiodiv;
+ uint32_t per_pll_pllglob;
+ uint32_t per_pll_fdbck;
+ uint32_t per_pll_pllc0;
+ uint32_t per_pll_pllc1;
+ uint32_t per_pll_pllc2;
+ uint32_t per_pll_pllc3;
+ uint32_t per_pll_pllm;
+ uint32_t alt_emacactr;
+ uint32_t alt_emacbctr;
+ uint32_t alt_emacptpctr;
+ uint32_t alt_gpiodbctr;
+ uint32_t alt_sdmmcctr;
+ uint32_t alt_s2fuser0ctr;
+ uint32_t alt_s2fuser1ctr;
+ uint32_t alt_psirefctr;
+ /* TODO: Temp added for clk manager. */
+ uint32_t qspi_clk_khz;
+ uint32_t hps_osc_clk_hz;
+ uint32_t fpga_clk_hz;
+ /* TODO: Temp added for clk manager. */
+ uint32_t ddr_reset_type;
+ /* TODO: Temp added for clk manager. */
+ uint32_t hps_status_coldreset;
+ /* TODO: Temp remove due to add in extra handoff data */
+ //uint32_t _pad_0x604_0x610[3];
#endif
/* misc configuration */
uint32_t misc_magic;
uint32_t misc_length;
uint32_t _pad_0x618_0x620[2];
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ /* peripheral configuration - select */
+ uint32_t peripheral_pwr_gate_magic;
+ uint32_t peripheral_pwr_gate_length;
+ uint32_t _pad_0x08_0x0C[2];
+ uint32_t peripheral_pwr_gate_array; /* offset, value */
+
+ /* ddr configuration - select */
+ uint32_t ddr_magic;
+ uint32_t ddr_length;
+ uint32_t _pad_0x1C_0x20[2];
+ uint32_t ddr_array[4]; /* offset, value */
+#endif
} handoff;
int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr);
int socfpga_get_handoff(handoff *hoff_ptr);
#endif
-
-
diff --git a/plat/intel/soc/common/soc/socfpga_handoff.c b/plat/intel/soc/common/soc/socfpga_handoff.c
index a3146b4..526c6e1 100644
--- a/plat/intel/soc/common/soc/socfpga_handoff.c
+++ b/plat/intel/soc/common/soc/socfpga_handoff.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,16 +29,34 @@
for (i = 0; i < sizeof(handoff) / 4; i++)
buffer[i] = SWAP_UINT32(buffer[i]);
- if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER)
+ if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER) {
return -1;
- if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL)
+ }
+ if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL) {
return -1;
- if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR)
+ }
+ if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR) {
return -1;
- if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA)
+ }
+ if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA) {
return -1;
- if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY)
+ }
+ if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY) {
return -1;
+ }
+ if (reverse_hoff_ptr->clock_magic != HANDOFF_MAGIC_CLOCK) {
+ return -1;
+ }
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ if (reverse_hoff_ptr->peripheral_pwr_gate_magic != HANDOFF_MAGIC_PERIPHERAL) {
+ return -1;
+ }
+
+ if (reverse_hoff_ptr->ddr_magic != HANDOFF_MAGIC_DDR) {
+ return -1;
+ }
+#endif
return 0;
}