fix(nxp-mmc): wait SDSTB before changing the clock
According to the reference manual, the host driver must ensure that the
SDSTB field is high before changing the clock divisor value (SDCLKFS or
DVS).
Change-Id: I3c89df707a825ccb5e5125b52e2d321b659bbb3f
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/drivers/imx/usdhc/imx_usdhc.c b/drivers/imx/usdhc/imx_usdhc.c
index 5ff947d..f3eccb2 100644
--- a/drivers/imx/usdhc/imx_usdhc.c
+++ b/drivers/imx/usdhc/imx_usdhc.c
@@ -123,6 +123,9 @@
div -= 1;
clk = (pre_div << 8) | (div << 4);
+ while ((mmio_read_32(reg_base + PSTATE) & PSTATE_SDSTB) == 0U) {
+ }
+
mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN);
mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk);
udelay(10000);
diff --git a/drivers/imx/usdhc/imx_usdhc.h b/drivers/imx/usdhc/imx_usdhc.h
index 3ef2474..bb0ef01 100644
--- a/drivers/imx/usdhc/imx_usdhc.h
+++ b/drivers/imx/usdhc/imx_usdhc.h
@@ -44,6 +44,7 @@
#define PSTATE 0x024U
#define PSTATE_DAT0 BIT_32(24U)
+#define PSTATE_SDSTB BIT_32(3U)
#define PSTATE_DLA BIT_32(2U)
#define PSTATE_CDIHB BIT_32(1U)
#define PSTATE_CIHB BIT_32(0U)