Merge "docs: update links to tf.org-wide process documents" into integration
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index ce45076..905b016 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -783,6 +783,10 @@
Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r1p1. It is fixed in r1p2.
+- ``ERRATA_X3_2743088``: This applies errata 2743088 workaround to Cortex-X3
+ CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1. It is
+ fixed in r1p2.
+
- ``ERRATA_X3_2779509``: This applies errata 2779509 workaround to Cortex-X3
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
CPU. It is fixed in r1p2.
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 235b2cf..215156b 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -62,23 +62,22 @@
#define CTX_ELR_EL3 U(0x20)
#define CTX_PMCR_EL0 U(0x28)
#define CTX_IS_IN_EL3 U(0x30)
-#define CTX_MPAM3_EL3 U(0x38)
/* Constants required in supporting nested exception in EL3 */
-#define CTX_SAVED_ELR_EL3 U(0x40)
+#define CTX_SAVED_ELR_EL3 U(0x38)
/*
* General purpose flag, to save various EL3 states
* FFH mode : Used to identify if handling nested exception
* KFH mode : Used as counter value
*/
-#define CTX_NESTED_EA_FLAG U(0x48)
+#define CTX_NESTED_EA_FLAG U(0x40)
#if FFH_SUPPORT
- #define CTX_SAVED_ESR_EL3 U(0x50)
- #define CTX_SAVED_SPSR_EL3 U(0x58)
- #define CTX_SAVED_GPREG_LR U(0x60)
- #define CTX_EL3STATE_END U(0x70) /* Align to the next 16 byte boundary */
+ #define CTX_SAVED_ESR_EL3 U(0x48)
+ #define CTX_SAVED_SPSR_EL3 U(0x50)
+ #define CTX_SAVED_GPREG_LR U(0x58)
+ #define CTX_EL3STATE_END U(0x60) /* Align to the next 16 byte boundary */
#else
#define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */
-#endif
+#endif /* FFH_SUPPORT */
/*******************************************************************************
* Constants that allow assembler code to access members of and the
@@ -343,7 +342,8 @@
******************************************************************************/
#define CTX_CPTR_EL3 U(0x0)
#define CTX_ZCR_EL3 U(0x8)
-#define CTX_PERWORLD_EL3STATE_END U(0x10)
+#define CTX_MPAM3_EL3 U(0x10)
+#define CTX_PERWORLD_EL3STATE_END U(0x18)
#ifndef __ASSEMBLER__
@@ -462,6 +462,7 @@
typedef struct per_world_context {
uint64_t ctx_cptr_el3;
uint64_t ctx_zcr_el3;
+ uint64_t ctx_mpam3_el3;
} per_world_context_t;
extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM];
diff --git a/include/lib/extensions/mpam.h b/include/lib/extensions/mpam.h
index 170f919..3dd5652 100644
--- a/include/lib/extensions/mpam.h
+++ b/include/lib/extensions/mpam.h
@@ -12,10 +12,10 @@
#include <context.h>
#if ENABLE_FEAT_MPAM
-void mpam_enable(cpu_context_t *context);
+void mpam_enable_per_world(per_world_context_t *per_world_ctx);
void mpam_init_el2_unused(void);
#else
-static inline void mpam_enable(cpu_context_t *context)
+static inline void mpam_enable_per_world(per_world_context_t *per_world_ctx)
{
}
static inline void mpam_init_el2_unused(void)
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index 95f3d10..7e9a7fc 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -57,6 +57,13 @@
check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1)
+workaround_runtime_start cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
+ /* dsb before isb of power down sequence */
+ dsb sy
+workaround_runtime_end cortex_x3, ERRATUM(2743088), NO_ISB
+
+check_erratum_ls cortex_x3, ERRATUM(2743088), CPU_REV(1, 1)
+
workaround_reset_start cortex_x3, ERRATUM(2779509), ERRATA_X3_2779509
/* Set CPUACTLR3_EL1 bit 47 */
sysreg_bit_set CORTEX_X3_CPUACTLR3_EL1, CORTEX_X3_CPUACTLR3_EL1_BIT_47
@@ -82,12 +89,13 @@
* ----------------------------------------------------
*/
func cortex_x3_core_pwr_dwn
-apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
+ apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ apply_erratum cortex_x3, ERRATUM(2743088), ERRATA_X3_2743088
isb
ret
endfunc cortex_x3_core_pwr_dwn
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 302f697..0ad5e78 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -786,6 +786,10 @@
# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2742421
+# Flag to apply erratum 2743088 workaround on powerdown. This erratum applies
+# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_X3_2743088
+
# Flag to apply erratum 2779509 workaround on reset. This erratum applies
# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2779509
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 18bdca8..389c086 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -378,9 +378,11 @@
* Restore MPAM3_EL3 register as per context state
* Currently we only enable MPAM for NS world and trap to EL3
* for MPAM access in lower ELs of Secure and Realm world
+ * x9 holds address of the per_world context
* -----------------------------------------------------------
*/
- ldr x17, [sp, #CTX_EL3STATE_OFFSET + CTX_MPAM3_EL3]
+
+ ldr x17, [x9, #CTX_MPAM3_EL3]
msr S3_6_C10_C5_0, x17 /* mpam3_el3 */
no_mpam:
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index a0212c6..05628b5 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -483,11 +483,6 @@
}
#endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */
- if (is_feat_mpam_supported()) {
- write_ctx_reg(get_el3state_ctx(ctx), CTX_MPAM3_EL3, \
- MPAM3_EL3_RESET_VAL);
- }
-
/*
* Populate EL3 state so that we've the right context
* before doing ERET
@@ -618,7 +613,17 @@
* CPTR_EL2,CPACR, or HCPTR do not trap to EL3.
*/
uint64_t cptr_el3 = CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TFP_BIT);
+
per_world_ctx->ctx_cptr_el3 = cptr_el3;
+
+ /*
+ * Initialize MPAM3_EL3 to its default reset value
+ *
+ * MPAM3_EL3_RESET_VAL sets the MPAM3_EL3.TRAPLOWER bit that forces
+ * all lower ELn MPAM3_EL3 register access to, trap to EL3
+ */
+
+ per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL;
}
#endif /* IMAGE_BL31 */
@@ -647,6 +652,10 @@
if (is_feat_sys_reg_trace_supported()) {
sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
}
+
+ if (is_feat_mpam_supported()) {
+ mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
+ }
}
#endif /* IMAGE_BL31 */
@@ -715,9 +724,6 @@
sme_enable(ctx);
}
- if (is_feat_mpam_supported()) {
- mpam_enable(ctx);
- }
pmuv3_enable(ctx);
#endif /* IMAGE_BL31 */
}
diff --git a/lib/extensions/mpam/mpam.c b/lib/extensions/mpam/mpam.c
index 875ad9c..5285b96 100644
--- a/lib/extensions/mpam/mpam.c
+++ b/lib/extensions/mpam/mpam.c
@@ -11,19 +11,19 @@
#include <arch_helpers.h>
#include <lib/extensions/mpam.h>
-void mpam_enable(cpu_context_t *context)
+void mpam_enable_per_world(per_world_context_t *per_world_ctx)
{
u_register_t mpam3_el3;
- mpam3_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_MPAM3_EL3);
-
/*
* Enable MPAM, and disable trapping to EL3 when lower ELs access their
* own MPAM registers
*/
+ mpam3_el3 = per_world_ctx->ctx_mpam3_el3;
mpam3_el3 = (mpam3_el3 | MPAM3_EL3_MPAMEN_BIT) &
~(MPAM3_EL3_TRAPLOWER_BIT);
- write_ctx_reg(get_el3state_ctx(context), CTX_MPAM3_EL3, mpam3_el3);
+
+ per_world_ctx->ctx_mpam3_el3 = mpam3_el3;
}
/*
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 8f1f1fe..537cb5c 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -449,8 +449,9 @@
[1] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
[2] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
[3] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
- [4] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
- [5 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [4] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
+ [5] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
+ [6 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_X3_H_INC */