tree 6b4ce897827c97cfa229c617c336adbeccfccee6
parent ff820ba2b893cdebd9539c09e2f13e1826f04796
author Jacky Bai <ping.bai@nxp.com> 1615884174 +0800
committer Jacky Bai <ping.bai@nxp.com> 1677565648 +0800

fix(imx8m): add ddr4 dvfs sw workaround for ERR050712

APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring

When performing a software driven MR access, the following
sequence must be done automatically before performing other
APB register accesses:

1. Set MRCTRL0.mr_wr=1
2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2)
3. Check for MRSTAT.mr_wr_busy=0 again (for the second time),
   if not, go to step (2).

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: Ie26e08bcc83d3ed4844ed04a853162308dcdccd0