tree 594497fd25e62ceb3652da99aefe9138c6399afc
parent 13d8a1594d915d31fbc3b12d649ed9cf77ce76f9
author Ravi Patel <ravi.patel@xilinx.com> 1552653168 +0530
committer Jolly Shah <jolly.shah@xilinx.com> 1579047989 -0800

zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node

Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value to be fixed and only value of DIV2 will be
adjusted according to required clock rate.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b