rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown
cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con,
spi, i2c, uart, saradc, tsadc when suspend, we have M0 code
need to run when suspend in normal SRAM, so we need to take
care of that.
Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
diff --git a/plat/rockchip/rk3399/include/plat.ld.S b/plat/rockchip/rk3399/include/plat.ld.S
index 86ca049..c42d9a9 100644
--- a/plat/rockchip/rk3399/include/plat.ld.S
+++ b/plat/rockchip/rk3399/include/plat.ld.S
@@ -30,24 +30,33 @@
.incbin_sram : ALIGN(4096) {
__sram_incbin_start = .;
*(.sram.incbin)
+ __sram_incbin_real_end = .;
. = ALIGN(4096);
__sram_incbin_end = .;
} >SRAM
+ ASSERT((__sram_incbin_real_end - __sram_incbin_start) <=
+ SRAM_BIN_LIMIT, ".incbin_sram has exceeded its limit")
.text_sram : ALIGN(4096) {
__bl31_sram_text_start = .;
*(.sram.text)
*(.sram.rodata)
+ __bl31_sram_text_real_end = .;
. = ALIGN(4096);
__bl31_sram_text_end = .;
} >SRAM
+ ASSERT((__bl31_sram_text_real_end - __bl31_sram_text_start) <=
+ SRAM_TEXT_LIMIT, ".text_sram has exceeded its limit")
.data_sram : ALIGN(4096) {
__bl31_sram_data_start = .;
*(.sram.data)
+ __bl31_sram_data_real_end = .;
. = ALIGN(4096);
__bl31_sram_data_end = .;
} >SRAM
+ ASSERT((__bl31_sram_data_real_end - __bl31_sram_data_start) <=
+ SRAM_DATA_LIMIT, ".data_sram has exceeded its limit")
.stack_sram : ALIGN(4096) {
__bl31_sram_stack_start = .;
diff --git a/plat/rockchip/rk3399/include/shared/addressmap_shared.h b/plat/rockchip/rk3399/include/shared/addressmap_shared.h
index d72633e..fe23e56 100644
--- a/plat/rockchip/rk3399/include/shared/addressmap_shared.h
+++ b/plat/rockchip/rk3399/include/shared/addressmap_shared.h
@@ -9,6 +9,9 @@
#define SIZE_K(n) ((n) * 1024)
#define SIZE_M(n) ((n) * 1024 * 1024)
+#define SRAM_TEXT_LIMIT (4 * 1024)
+#define SRAM_DATA_LIMIT (4 * 1024)
+#define SRAM_BIN_LIMIT (4 * 1024)
/*
* The parts of the shared defined registers address with AP and M0,