tree 20f0d1e6066bc1a136e41aea7fa7d44feb622cea
parent ae58772f510e2a05a55707471f4fe366ef32b4b7
author Varun Wadekar <vwadekar@nvidia.com> 1590362782 -0700
committer Manish Pandey <manish.pandey2@arm.com> 1591732469 +0000

cpus: denver: disable cycle counter when event counting is prohibited

The Denver CPUs implement support for PMUv3 for ARMv8.1 and expect the
PMCR_EL0 to be saved in non-secure context.

This patch disables cycle counter when event counting is prohibited
immediately on entering the secure world to avoid leaking useful
information about the PMU counters. The context saving code later
saves the value of PMCR_EL0 to the non-secure world context.

Verified with 'PMU Leakage' test suite.

 ******************************* Summary *******************************
 > Test suite 'PMU Leakage'
                                                                 Passed
 =================================
 Tests Skipped : 2
 Tests Passed  : 2
 Tests Failed  : 0
 Tests Crashed : 0
 Total tests   : 4
 =================================

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: I3675e2b99b44ed23d86e29a5af1b496e80324875