Merge changes Ia0d13c3c,I8cf821a4,I1e6a598b,I9c6dd8db,Iaf6db75e, ... into integration
* changes:
fix(plat/xilinx/versal): resolve misra R10.6
fix(plat/xilinx/versal): resolve misra R14.4
fix(plat/xilinx/versal): resolve misra R17.7
fix(plat/xilinx/versal): resolve misra R10.3
fix(plat/xilinx/versal): resolve misra R7.2
fix(plat/xilinx/versal): resolve misra R15.7
fix(plat/xilinx/versal): resolve misra R15.6
fix(plat/xilinx/versal): resolve misra R10.1 in pm services
fix(plat/xilinx/versal): resolve misra R20.7 in pm services
fix(plat/xilinx/versal): resolve misra R10.3 in pm services
fix(plat/xilinx/versal): resolve misra R10.6 in pm services
fix(plat/xilinx/versal): resolve misra R16.3 in pm services
fix(plat/xilinx/versal): resolve misra R15.6 in pm services
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 8b8714c..f59859e 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -46,11 +46,11 @@
*/
static inline void bl31_set_default_config(void)
{
- bl32_image_ep_info.pc = BL32_BASE;
- bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
- bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
- bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
+ bl32_image_ep_info.pc = (uintptr_t)BL32_BASE;
+ bl32_image_ep_info.spsr = (uint32_t)arm_get_spsr_for_bl32_entry();
+ bl33_image_ep_info.pc = (uintptr_t)plat_get_ns_image_entrypoint();
+ bl33_image_ep_info.spsr = (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS);
}
/*
@@ -67,23 +67,26 @@
if (VERSAL_CONSOLE_IS(pl011)) {
static console_t versal_runtime_console;
/* Initialize the console to provide early debug support */
- int rc = console_pl011_register(VERSAL_UART_BASE,
- VERSAL_UART_CLOCK,
- VERSAL_UART_BAUDRATE,
+ int rc = console_pl011_register((unsigned long)VERSAL_UART_BASE,
+ (unsigned int)VERSAL_UART_CLOCK,
+ (unsigned int)VERSAL_UART_BAUDRATE,
&versal_runtime_console);
if (rc == 0) {
panic();
}
- console_set_scope(&versal_runtime_console, CONSOLE_FLAG_BOOT |
- CONSOLE_FLAG_RUNTIME);
+ console_set_scope(&versal_runtime_console, (unsigned int)(CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME));
} else if (VERSAL_CONSOLE_IS(dcc)) {
/* Initialize the dcc console for debug */
int rc = console_dcc_register();
if (rc == 0) {
panic();
}
+ } else {
+ NOTICE("BL31: Did not register for any console.\n");
}
+
/* Initialize the platform config for future decision making */
versal_config_setup();
/* There are no parameters from BL2 if BL31 is a reset vector */
@@ -111,6 +114,8 @@
bl31_set_default_config();
} else if (ret != FSBL_HANDOFF_SUCCESS) {
panic();
+ } else {
+ ERROR("BL31: Error during fsbl-atf handover %d.\n", ret);
}
NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc);
@@ -122,7 +127,7 @@
int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
{
/* Validate 'handler'*/
- if (!handler) {
+ if (handler == NULL) {
return -EINVAL;
}
@@ -145,7 +150,7 @@
}
handler = type_el3_interrupt_handler;
- if (handler) {
+ if (handler != NULL) {
return handler(intr_id, flags, handle, cookie);
}
@@ -161,12 +166,12 @@
void bl31_plat_runtime_setup(void)
{
uint64_t flags = 0;
- uint64_t rc;
+ int32_t rc;
set_interrupt_rm_flag(flags, NON_SECURE);
rc = register_interrupt_type_handler(INTR_TYPE_EL3,
rdo_el3_interrupt_handler, flags);
- if (rc) {
+ if (rc != 0) {
panic();
}
}
diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index 8b513ef..83e5083 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,9 +18,9 @@
#define PLATFORM_STACK_SIZE 0x440
#define PLATFORM_CORE_COUNT U(2)
-#define PLAT_MAX_PWR_LVL 1
-#define PLAT_MAX_RET_STATE 1
-#define PLAT_MAX_OFF_STATE 2
+#define PLAT_MAX_PWR_LVL U(1)
+#define PLAT_MAX_RET_STATE U(1)
+#define PLAT_MAX_OFF_STATE U(2)
/*******************************************************************************
* BL31 specific defines.
@@ -31,8 +31,8 @@
* little space for growth.
*/
#ifndef VERSAL_ATF_MEM_BASE
-# define BL31_BASE 0xfffe0000
-# define BL31_LIMIT 0xffffffff
+# define BL31_BASE U(0xfffe0000)
+# define BL31_LIMIT U(0xffffffff)
#else
# define BL31_BASE (VERSAL_ATF_MEM_BASE)
# define BL31_LIMIT (VERSAL_ATF_MEM_BASE + VERSAL_ATF_MEM_SIZE - 1)
@@ -45,8 +45,8 @@
* BL32 specific defines.
******************************************************************************/
#ifndef VERSAL_BL32_MEM_BASE
-# define BL32_BASE 0x60000000
-# define BL32_LIMIT 0x7fffffff
+# define BL32_BASE U(0x60000000)
+# define BL32_LIMIT U(0x7fffffff)
#else
# define BL32_BASE (VERSAL_BL32_MEM_BASE)
# define BL32_LIMIT (VERSAL_BL32_MEM_BASE + VERSAL_BL32_MEM_SIZE - 1)
@@ -56,7 +56,7 @@
* BL33 specific defines.
******************************************************************************/
#ifndef PRELOADED_BL33_BASE
-# define PLAT_ARM_NS_IMAGE_BASE 0x8000000
+# define PLAT_ARM_NS_IMAGE_BASE U(0x8000000)
#else
# define PLAT_ARM_NS_IMAGE_BASE PRELOADED_BL33_BASE
#endif
@@ -81,8 +81,8 @@
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-#define PLAT_VERSAL_GICD_BASE 0xF9000000
-#define PLAT_VERSAL_GICR_BASE 0xF9080000
+#define PLAT_VERSAL_GICD_BASE U(0xF9000000)
+#define PLAT_VERSAL_GICR_BASE U(0xF9080000)
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
@@ -91,7 +91,7 @@
*/
#define PLAT_VERSAL_G1S_IRQS VERSAL_IRQ_SEC_PHY_TIMER
#define PLAT_VERSAL_G0_IRQS VERSAL_IRQ_SEC_PHY_TIMER
-#define PLAT_VERSAL_IPI_IRQ 62
+#define PLAT_VERSAL_IPI_IRQ U(62)
#define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index 001fb04..9372954 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -52,7 +52,7 @@
/*******************************************************************************
* IRQ constants
******************************************************************************/
-#define VERSAL_IRQ_SEC_PHY_TIMER 29
+#define VERSAL_IRQ_SEC_PHY_TIMER U(29)
/*******************************************************************************
* CCI-400 related constants
@@ -112,33 +112,33 @@
#define FPD_MAINCCI_SIZE 0x00100000
/* APU registers and bitfields */
-#define FPD_APU_BASE 0xFD5C0000
-#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20)
-#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40)
-#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44)
-#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90)
+#define FPD_APU_BASE 0xFD5C0000U
+#define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U)
+#define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U)
+#define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U)
+#define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U)
-#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8
-#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1
-#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2
+#define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U
+#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U
+#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U
/* PMC registers and bitfields */
-#define PMC_GLOBAL_BASE 0xF1110000
-#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40)
+#define PMC_GLOBAL_BASE 0xF1110000U
+#define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U)
/* IPI registers and bitfields */
-#define IPI0_REG_BASE 0xFF330000
-#define IPI0_TRIG_BIT (1 << 2)
-#define PMC_IPI_TRIG_BIT (1 << 1)
-#define IPI1_REG_BASE 0xFF340000
-#define IPI1_TRIG_BIT (1 << 3)
-#define IPI2_REG_BASE 0xFF350000
-#define IPI2_TRIG_BIT (1 << 4)
-#define IPI3_REG_BASE 0xFF360000
-#define IPI3_TRIG_BIT (1 << 5)
-#define IPI4_REG_BASE 0xFF370000
-#define IPI4_TRIG_BIT (1 << 5)
-#define IPI5_REG_BASE 0xFF380000
-#define IPI5_TRIG_BIT (1 << 6)
+#define IPI0_REG_BASE U(0xFF330000)
+#define IPI0_TRIG_BIT (1U << 2U)
+#define PMC_IPI_TRIG_BIT (1U << 1U)
+#define IPI1_REG_BASE U(0xFF340000)
+#define IPI1_TRIG_BIT (1U << 3U)
+#define IPI2_REG_BASE U(0xFF350000)
+#define IPI2_TRIG_BIT (1U << 4U)
+#define IPI3_REG_BASE U(0xFF360000)
+#define IPI3_TRIG_BIT (1U << 5U)
+#define IPI4_REG_BASE U(0xFF370000)
+#define IPI4_TRIG_BIT (1U << 5U)
+#define IPI5_REG_BASE U(0xFF380000)
+#define IPI5_TRIG_BIT (1U << 6U)
#endif /* VERSAL_DEF_H */
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index fa0284c..eb05e58 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,19 +21,20 @@
static int versal_pwr_domain_on(u_register_t mpidr)
{
- unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr);
+ int cpu_id = plat_core_pos_by_mpidr(mpidr);
const struct pm_proc *proc;
VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr);
- if (cpu_id == -1)
+ if (cpu_id == -1) {
return PSCI_E_INTERN_FAIL;
+ }
- proc = pm_get_proc(cpu_id);
+ proc = pm_get_proc((unsigned int)cpu_id);
/* Send request to PMC to wake up selected ACPU core */
- pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFF) | 0x1,
- versal_sec_entry >> 32, 0, SECURE_FLAG);
+ (void)pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U,
+ versal_sec_entry >> 32, 0, SECURE_FLAG);
/* Clear power down request */
pm_client_wakeup(proc);
@@ -53,9 +54,10 @@
unsigned int cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
- for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
+ for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
+ }
plat_versal_gic_cpuif_disable();
@@ -67,8 +69,8 @@
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
/* Send request to PMC to suspend this core */
- pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry,
- SECURE_FLAG);
+ (void)pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry,
+ SECURE_FLAG);
/* APU is to be turned off */
if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
@@ -89,9 +91,10 @@
unsigned int cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
- for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
+ for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
+ }
/* Clear the APU power control register for this cpu */
pm_client_wakeup(proc);
@@ -123,11 +126,12 @@
static void __dead2 versal_system_off(void)
{
/* Send the power down request to the PMC */
- pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
- pm_get_shutdown_scope(), SECURE_FLAG);
+ (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
+ pm_get_shutdown_scope(), SECURE_FLAG);
- while (1)
+ while (1) {
wfi();
+ }
}
/**
@@ -137,11 +141,12 @@
static void __dead2 versal_system_reset(void)
{
/* Send the system reset request to the PMC */
- pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
- pm_get_shutdown_scope(), SECURE_FLAG);
+ (void)pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
+ pm_get_shutdown_scope(), SECURE_FLAG);
- while (1)
+ while (1) {
wfi();
+ }
}
/**
@@ -154,9 +159,10 @@
unsigned int cpu_id = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpu_id);
- for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++)
+ for (size_t i = 0U; i <= PLAT_MAX_PWR_LVL; i++) {
VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n",
__func__, i, target_state->pwr_domain_state[i]);
+ }
/* Prevent interrupts from spuriously waking up this cpu */
plat_versal_gic_cpuif_disable();
@@ -169,8 +175,8 @@
* invoking CPU_on function, during which resume address will
* be set.
*/
- pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0,
- SECURE_FLAG);
+ (void)pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0,
+ SECURE_FLAG);
}
/**
@@ -187,19 +193,21 @@
{
VERBOSE("%s: power_state: 0x%x\n", __func__, power_state);
- int pstate = psci_get_pstate_type(power_state);
+ unsigned int pstate = psci_get_pstate_type(power_state);
assert(req_state);
/* Sanity check the requested state */
- if (pstate == PSTATE_TYPE_STANDBY)
+ if (pstate == PSTATE_TYPE_STANDBY) {
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE;
- else
+ } else {
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE;
+ }
/* We expect the 'state id' to be zero */
- if (psci_get_pstate_id(power_state))
+ if (psci_get_pstate_id(power_state) != 0U) {
return PSCI_E_INVALID_PARAMS;
+ }
return PSCI_E_SUCCESS;
}
diff --git a/plat/xilinx/versal/plat_versal.c b/plat/xilinx/versal/plat_versal.c
index 107eae6..54c35b6 100644
--- a/plat/xilinx/versal/plat_versal.c
+++ b/plat/xilinx/versal/plat_versal.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,7 @@
int plat_core_pos_by_mpidr(u_register_t mpidr)
{
- if (mpidr & MPIDR_CLUSTER_MASK) {
+ if ((mpidr & MPIDR_CLUSTER_MASK) != 0U) {
return -1;
}
@@ -17,5 +17,5 @@
return -1;
}
- return versal_calc_core_pos(mpidr);
+ return (int)versal_calc_core_pos(mpidr);
}
diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c
index 912835a..534d910 100644
--- a/plat/xilinx/versal/pm_service/pm_api_sys.c
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2021, Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,10 +21,10 @@
/*********************************************************************
* Target module IDs macros
********************************************************************/
-#define LIBPM_MODULE_ID 0x2
-#define LOADER_MODULE_ID 0x7
+#define LIBPM_MODULE_ID 0x2U
+#define LOADER_MODULE_ID 0x7U
-#define MODE 0x80000000
+#define MODE 0x80000000U
/* default shutdown/reboot scope is system(2) */
static unsigned int pm_shutdown_scope = XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM;
@@ -42,32 +42,32 @@
* Assigning of argument values into array elements.
*/
#define PM_PACK_PAYLOAD1(pl, mid, flag, arg0) { \
- pl[0] = (uint32_t)((uint32_t)((arg0) & 0xFF) | (mid << 8) | ((flag) << 24)); \
+ pl[0] = (uint32_t)(((uint32_t)(arg0) & 0xFFU) | ((mid) << 8U) | ((flag) << 24U)); \
}
#define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) { \
pl[1] = (uint32_t)(arg1); \
- PM_PACK_PAYLOAD1(pl, mid, flag, arg0); \
+ PM_PACK_PAYLOAD1(pl, (mid), (flag), (arg0)); \
}
#define PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2) { \
pl[2] = (uint32_t)(arg2); \
- PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1); \
+ PM_PACK_PAYLOAD2(pl, (mid), (flag), (arg0), (arg1)); \
}
#define PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3) { \
pl[3] = (uint32_t)(arg3); \
- PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2); \
+ PM_PACK_PAYLOAD3(pl, (mid), (flag), (arg0), (arg1), (arg2)); \
}
#define PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4) { \
pl[4] = (uint32_t)(arg4); \
- PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3); \
+ PM_PACK_PAYLOAD4(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3)); \
}
#define PM_PACK_PAYLOAD6(pl, mid, flag, arg0, arg1, arg2, arg3, arg4, arg5) { \
pl[5] = (uint32_t)(arg5); \
- PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4); \
+ PM_PACK_PAYLOAD5(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3), (arg4)); \
}
/* PM API functions */
@@ -130,7 +130,7 @@
unsigned int cpuid = plat_my_core_pos();
const struct pm_proc *proc = pm_get_proc(cpuid);
- if (!proc) {
+ if (proc == NULL) {
WARN("Failed to get proc %d\n", cpuid);
return PM_RET_ERROR_INTERNAL;
}
@@ -197,10 +197,11 @@
/* Send request to the PMU */
PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, flag, PM_REQ_SUSPEND, target,
latency, state);
- if (ack == IPI_BLOCKING)
+ if (ack == IPI_BLOCKING) {
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
- else
+ } else {
return pm_ipi_send(primary_proc, payload);
+ }
}
/**
@@ -372,8 +373,9 @@
void pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag)
{
/* Return if interrupt is not from PMU */
- if (!pm_ipi_irq_status(primary_proc))
+ if (pm_ipi_irq_status(primary_proc) == 0) {
return;
+ }
pm_ipi_buff_read_callb(data, count);
pm_ipi_irq_clear(primary_proc);
@@ -771,10 +773,11 @@
PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_FORCE_POWERDOWN,
target, ack);
- if (ack == IPI_BLOCKING)
+ if (ack == IPI_BLOCKING) {
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
- else
+ } else {
return pm_ipi_send(primary_proc, payload);
+ }
}
/**
@@ -830,7 +833,7 @@
ret = pm_feature_check(PM_QUERY_DATA, &version, flag);
if (PM_RET_SUCCESS == ret) {
- fw_api_version = version & 0xFFFF ;
+ fw_api_version = version & 0xFFFFU;
if ((2U == fw_api_version) &&
((XPM_QID_CLOCK_GET_NAME == qid) ||
(XPM_QID_PINCTRL_GET_FUNCTION_NAME == qid))) {
@@ -864,32 +867,39 @@
uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
- int ret;
+ enum pm_ret_status ret;
switch (ioctl_id) {
case IOCTL_SET_PLL_FRAC_MODE:
- return pm_pll_set_mode(arg1, arg2, flag);
+ ret = pm_pll_set_mode(arg1, arg2, flag);
+ break;
case IOCTL_GET_PLL_FRAC_MODE:
- return pm_pll_get_mode(arg1, value, flag);
+ ret = pm_pll_get_mode(arg1, value, flag);
+ break;
case IOCTL_SET_PLL_FRAC_DATA:
- return pm_pll_set_param(arg1, PM_PLL_PARAM_DATA, arg2, flag);
+ ret = pm_pll_set_param(arg1, PM_PLL_PARAM_DATA, arg2, flag);
+ break;
case IOCTL_GET_PLL_FRAC_DATA:
- return pm_pll_get_param(arg1, PM_PLL_PARAM_DATA, value, flag);
+ ret = pm_pll_get_param(arg1, PM_PLL_PARAM_DATA, value, flag);
+ break;
case IOCTL_SET_SGI:
/* Get the sgi number */
- ret = pm_register_sgi(arg1);
- if (ret) {
+ if (pm_register_sgi(arg1) != 0) {
return PM_RET_ERROR_ARGS;
}
gicd_write_irouter(gicv3_driver_data->gicd_base,
- PLAT_VERSAL_IPI_IRQ, MODE);
- return PM_RET_SUCCESS;
+ (unsigned int)PLAT_VERSAL_IPI_IRQ, MODE);
+ ret = PM_RET_SUCCESS;
+ break;
default:
/* Send request to the PMC */
PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, flag, PM_IOCTL,
device_id, ioctl_id, arg1, arg2);
- return pm_ipi_send_sync(primary_proc, payload, value, 1);
+ ret = pm_ipi_send_sync(primary_proc, payload, value, 1);
+ break;
}
+
+ return ret;
}
/**
@@ -944,14 +954,15 @@
uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT], fw_api_version;
- uint32_t status;
+ enum pm_ret_status status = PM_RET_ERROR_NOFEATURE;
switch (api_id) {
case PM_GET_CALLBACK_DATA:
case PM_GET_TRUSTZONE_VERSION:
case PM_LOAD_PDI:
*version = (PM_API_BASE_VERSION << 16);
- return PM_RET_SUCCESS;
+ status = PM_RET_SUCCESS;
+ break;
case PM_GET_API_VERSION:
case PM_GET_DEVICE_STATUS:
case PM_GET_OP_CHARACTERISTIC:
@@ -992,25 +1003,36 @@
case PM_SET_MAX_LATENCY:
case PM_REGISTER_NOTIFIER:
*version = (PM_API_BASE_VERSION << 16);
+ status = PM_RET_SUCCESS;
break;
case PM_QUERY_DATA:
*version = (PM_API_QUERY_DATA_VERSION << 16);
+ status = PM_RET_SUCCESS;
break;
default:
*version = 0U;
- return PM_RET_ERROR_NOFEATURE;
+ status = PM_RET_ERROR_NOFEATURE;
+ break;
}
+ if (status != PM_RET_SUCCESS) {
+ goto done;
+ }
+
PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag,
PM_FEATURE_CHECK, api_id);
status = pm_ipi_send_sync(primary_proc, payload, &fw_api_version, 1);
- if (status != PM_RET_SUCCESS)
- return status;
+ if (status != PM_RET_SUCCESS) {
+ goto done;
+ }
*version |= fw_api_version;
- return PM_RET_SUCCESS;
+ status = PM_RET_SUCCESS;
+
+done:
+ return status;
}
/**
diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index f6c3148..77ec20e 100644
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2021, Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,8 +23,8 @@
#include "pm_client.h"
#define UNDEFINED_CPUID (~0)
-#define IRQ_MAX 142
-#define NUM_GICD_ISENABLER ((IRQ_MAX >> 5) + 1)
+#define IRQ_MAX 142U
+#define NUM_GICD_ISENABLER ((IRQ_MAX >> 5U) + 1U)
DEFINE_BAKERY_LOCK(pm_client_secure_lock);
@@ -122,36 +122,38 @@
uint8_t pm_wakeup_nodes_set[XPM_NODEIDX_DEV_MAX];
uintptr_t isenabler1 = PLAT_VERSAL_GICD_BASE + GICD_ISENABLER + 4;
- zeromem(&pm_wakeup_nodes_set, sizeof(pm_wakeup_nodes_set));
+ zeromem(&pm_wakeup_nodes_set, (u_register_t)sizeof(pm_wakeup_nodes_set));
- for (reg_num = 0; reg_num < NUM_GICD_ISENABLER; reg_num++) {
+ for (reg_num = 0U; reg_num < NUM_GICD_ISENABLER; reg_num++) {
uint32_t base_irq = reg_num << ISENABLER_SHIFT;
uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2));
- if (!reg)
+ if (reg == 0U) {
continue;
+ }
- while (reg) {
+ while (reg != 0U) {
enum pm_device_node_idx node_idx;
- uint32_t idx, ret, irq, lowest_set = reg & (-reg);
-
+ uint32_t idx, irq, lowest_set = reg & (-reg);
+ enum pm_ret_status ret;
idx = __builtin_ctz(lowest_set);
irq = base_irq + idx;
- if (irq > IRQ_MAX)
+ if (irq > IRQ_MAX) {
break;
+ }
node_idx = irq_to_pm_node_idx(irq);
reg &= ~lowest_set;
if ((node_idx != XPM_NODEIDX_DEV_MIN) &&
- (!pm_wakeup_nodes_set[node_idx])) {
+ (pm_wakeup_nodes_set[node_idx] == 0U)) {
/* Get device ID from node index */
device_id = PERIPH_DEVID(node_idx);
ret = pm_set_wakeup_source(node_id,
device_id, 1,
SECURE_FLAG);
- pm_wakeup_nodes_set[node_idx] = !ret;
+ pm_wakeup_nodes_set[node_idx] = (uint8_t)(!ret);
}
}
}
@@ -168,12 +170,13 @@
{
bakery_lock_get(&pm_client_secure_lock);
- if (state == PM_STATE_SUSPEND_TO_RAM)
- pm_client_set_wakeup_sources(proc->node_id);
+ if (state == PM_STATE_SUSPEND_TO_RAM) {
+ pm_client_set_wakeup_sources((uint32_t)proc->node_id);
+ }
/* Set powerdown request */
mmio_write_32(FPD_APU_PWRCTL, mmio_read_32(FPD_APU_PWRCTL) |
- proc->pwrdn_mask);
+ (uint32_t)proc->pwrdn_mask);
bakery_lock_release(&pm_client_secure_lock);
}
@@ -193,7 +196,7 @@
/* Clear powerdown request */
mmio_write_32(FPD_APU_PWRCTL, mmio_read_32(FPD_APU_PWRCTL) &
- ~primary_proc->pwrdn_mask);
+ ~((uint32_t)primary_proc->pwrdn_mask));
bakery_lock_release(&pm_client_secure_lock);
}
@@ -206,9 +209,10 @@
*/
static unsigned int pm_get_cpuid(uint32_t nid)
{
- for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) {
- if (pm_procs_all[i].node_id == nid)
+ for (size_t i = 0U; i < ARRAY_SIZE(pm_procs_all); i++) {
+ if (pm_procs_all[i].node_id == nid) {
return i;
+ }
}
return UNDEFINED_CPUID;
}
@@ -223,8 +227,9 @@
{
unsigned int cpuid = pm_get_cpuid(proc->node_id);
- if (cpuid == UNDEFINED_CPUID)
+ if (cpuid == UNDEFINED_CPUID) {
return;
+ }
bakery_lock_get(&pm_client_secure_lock);
@@ -244,8 +249,9 @@
*/
const struct pm_proc *pm_get_proc(unsigned int cpuid)
{
- if (cpuid < ARRAY_SIZE(pm_procs_all))
+ if (cpuid < ARRAY_SIZE(pm_procs_all)) {
return &pm_procs_all[cpuid];
+ }
return NULL;
}
diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h
index ccb2617..08b46e2 100644
--- a/plat/xilinx/versal/pm_service/pm_defs.h
+++ b/plat/xilinx/versal/pm_service/pm_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2021, Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,8 +33,8 @@
XPM_NODESUBCL_DEV_PERIPH, \
XPM_NODETYPE_DEV_PERIPH, (IDX))
-#define PM_GET_CALLBACK_DATA 0xa01
-#define PM_GET_TRUSTZONE_VERSION 0xa03
+#define PM_GET_CALLBACK_DATA 0xa01U
+#define PM_GET_TRUSTZONE_VERSION 0xa03U
/* PM API Versions */
#define PM_API_BASE_VERSION 1U
@@ -88,11 +88,11 @@
#define PM_LOAD_PDI 0x701U
/* IOCTL IDs for clock driver */
-#define IOCTL_SET_PLL_FRAC_MODE 8
-#define IOCTL_GET_PLL_FRAC_MODE 9
-#define IOCTL_SET_PLL_FRAC_DATA 10
-#define IOCTL_GET_PLL_FRAC_DATA 11
-#define IOCTL_SET_SGI 25
+#define IOCTL_SET_PLL_FRAC_MODE 8U
+#define IOCTL_GET_PLL_FRAC_MODE 9U
+#define IOCTL_SET_PLL_FRAC_DATA 10U
+#define IOCTL_GET_PLL_FRAC_DATA 11U
+#define IOCTL_SET_SGI 25U
/* Parameter ID for PLL IOCTLs */
/* Fractional data portion for PLL */
diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c
index 87ba732..b082acb 100644
--- a/plat/xilinx/versal/pm_service/pm_svc_main.c
+++ b/plat/xilinx/versal/pm_service/pm_svc_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2021, Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,24 +20,24 @@
#include <drivers/arm/gicv3.h>
#define XSCUGIC_SGIR_EL1_INITID_SHIFT 24U
-#define INVALID_SGI 0xFF
+#define INVALID_SGI 0xFFU
DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r_el1, S3_0_C12_C11_6)
/* pm_up = true - UP, pm_up = false - DOWN */
static bool pm_up;
-static unsigned int sgi = INVALID_SGI;
+static unsigned int sgi = (unsigned int)INVALID_SGI;
static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle,
void *cookie)
{
- int cpu;
+ unsigned int cpu;
unsigned int reg;
(void)plat_ic_acknowledge_interrupt();
- cpu = plat_my_core_pos() + 1;
+ cpu = plat_my_core_pos() + 1U;
- if (sgi != INVALID_SGI) {
- reg = (cpu | (sgi << XSCUGIC_SGIR_EL1_INITID_SHIFT));
+ if ((unsigned int)sgi != (unsigned int)INVALID_SGI) {
+ reg = (cpu | ((unsigned int)sgi << (unsigned int)XSCUGIC_SGIR_EL1_INITID_SHIFT));
write_icc_asgi1r_el1(reg);
}
@@ -60,7 +60,7 @@
*/
int pm_register_sgi(unsigned int sgi_num)
{
- if (sgi != INVALID_SGI) {
+ if ((unsigned int)sgi != (unsigned int)INVALID_SGI) {
return -EBUSY;
}
@@ -68,7 +68,7 @@
return -EINVAL;
}
- sgi = sgi_num;
+ sgi = (unsigned int)sgi_num;
return 0;
}
@@ -107,7 +107,7 @@
pm_ipi_irq_enable(primary_proc);
ret = request_intr_type_el3(PLAT_VERSAL_IPI_IRQ, ipi_fiq_handler);
- if (ret) {
+ if (ret != 0) {
WARN("BL31: registering IPI interrupt failed\n");
}
return ret;
@@ -138,8 +138,9 @@
uint32_t security_flag = SECURE_FLAG;
/* Handle case where PM wasn't initialized properly */
- if (!pm_up)
+ if (pm_up == false) {
SMC_RET1(handle, SMC_UNK);
+ }
pm_arg[0] = (uint32_t)x1;
pm_arg[1] = (uint32_t)(x1 >> 32);
@@ -150,7 +151,7 @@
* Mark BIT24 payload (i.e 1st bit of pm_arg[3] ) as non-secure (1)
* if smc called is non secure
*/
- if (is_caller_non_secure(flags)) {
+ if (is_caller_non_secure(flags) != 0) {
security_flag = NON_SECURE_FLAG;
}
@@ -207,8 +208,8 @@
uint32_t api_version;
ret = pm_get_api_version(&api_version, security_flag);
- SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
- ((uint64_t)api_version << 32));
+ SMC_RET1(handle, (u_register_t)PM_RET_SUCCESS |
+ ((u_register_t)api_version << 32));
}
case PM_GET_DEVICE_STATUS:
@@ -216,8 +217,8 @@
uint32_t buff[3];
ret = pm_get_device_status(pm_arg[0], buff, security_flag);
- SMC_RET2(handle, (uint64_t)ret | ((uint64_t)buff[0] << 32),
- (uint64_t)buff[1] | ((uint64_t)buff[2] << 32));
+ SMC_RET2(handle, (u_register_t)ret | ((u_register_t)buff[0] << 32),
+ (u_register_t)buff[1] | ((u_register_t)buff[2] << 32));
}
case PM_RESET_ASSERT:
@@ -230,8 +231,8 @@
ret = pm_reset_get_status(pm_arg[0], &reset_status,
security_flag);
- SMC_RET1(handle, (uint64_t)ret |
- ((uint64_t)reset_status << 32));
+ SMC_RET1(handle, (u_register_t)ret |
+ ((u_register_t)reset_status << 32));
}
case PM_INIT_FINALIZE:
@@ -244,8 +245,8 @@
pm_get_callbackdata(result, ARRAY_SIZE(result), security_flag);
SMC_RET2(handle,
- (uint64_t)result[0] | ((uint64_t)result[1] << 32),
- (uint64_t)result[2] | ((uint64_t)result[3] << 32));
+ (u_register_t)result[0] | ((u_register_t)result[1] << 32),
+ (u_register_t)result[2] | ((u_register_t)result[3] << 32));
}
case PM_PINCTRL_REQUEST:
@@ -261,7 +262,7 @@
uint32_t value = 0;
ret = pm_pinctrl_get_function(pm_arg[0], &value, security_flag);
- SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ SMC_RET1(handle, (u_register_t)ret | ((u_register_t)value) << 32);
}
case PM_PINCTRL_SET_FUNCTION:
@@ -275,7 +276,7 @@
ret = pm_pinctrl_get_pin_param(pm_arg[0], pm_arg[1], &value,
security_flag);
- SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ SMC_RET1(handle, (u_register_t)ret | ((u_register_t)value) << 32);
}
case PM_PINCTRL_CONFIG_PARAM_SET:
@@ -289,7 +290,7 @@
ret = pm_api_ioctl(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], &value, security_flag);
- SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ SMC_RET1(handle, (u_register_t)ret | ((u_register_t)value) << 32);
}
case PM_QUERY_DATA:
@@ -299,8 +300,8 @@
ret = pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], data, security_flag);
- SMC_RET2(handle, (uint64_t)ret | ((uint64_t)data[0] << 32),
- (uint64_t)data[1] | ((uint64_t)data[2] << 32));
+ SMC_RET2(handle, (u_register_t)ret | ((u_register_t)data[0] << 32),
+ (u_register_t)data[1] | ((u_register_t)data[2] << 32));
}
case PM_CLOCK_ENABLE:
@@ -316,7 +317,7 @@
uint32_t value;
ret = pm_clock_get_state(pm_arg[0], &value, security_flag);
- SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ SMC_RET1(handle, (u_register_t)ret | ((u_register_t)value) << 32);
}
case PM_CLOCK_SETDIVIDER:
@@ -328,7 +329,7 @@
uint32_t value;
ret = pm_clock_get_divider(pm_arg[0], &value, security_flag);
- SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ SMC_RET1(handle, (u_register_t)ret | ((u_register_t)value) << 32);
}
case PM_CLOCK_SETPARENT:
@@ -340,7 +341,7 @@
uint32_t value;
ret = pm_clock_get_parent(pm_arg[0], &value, security_flag);
- SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
+ SMC_RET1(handle, (u_register_t)ret | ((u_register_t)value) << 32);
}
case PM_CLOCK_GETRATE:
@@ -348,8 +349,8 @@
uint32_t rate[2] = { 0 };
ret = pm_clock_get_rate(pm_arg[0], rate, security_flag);
- SMC_RET2(handle, (uint64_t)ret | ((uint64_t)rate[0] << 32),
- rate[1]);
+ SMC_RET2(handle, (u_register_t)ret | ((u_register_t)rate[0] << 32),
+ (u_register_t)rate[1] | ((u_register_t)0U << 32));
}
case PM_PLL_SET_PARAMETER:
@@ -363,7 +364,7 @@
ret = pm_pll_get_param(pm_arg[0], pm_arg[1], &value,
security_flag);
- SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32));
+ SMC_RET1(handle, (u_register_t)ret | ((u_register_t)value << 32));
}
case PM_PLL_SET_MODE:
@@ -375,7 +376,7 @@
uint32_t mode;
ret = pm_pll_get_mode(pm_arg[0], &mode, security_flag);
- SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32));
+ SMC_RET1(handle, (u_register_t)ret | ((u_register_t)mode << 32));
}
case PM_GET_TRUSTZONE_VERSION:
@@ -387,8 +388,8 @@
uint32_t result[2];
ret = pm_get_chipid(result, security_flag);
- SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32),
- result[1]);
+ SMC_RET2(handle, (u_register_t)ret | ((u_register_t)result[0] << 32),
+ (u_register_t)result[1] | ((u_register_t)0U << 32));
}
case PM_FEATURE_CHECK:
@@ -396,14 +397,14 @@
uint32_t version;
ret = pm_feature_check(pm_arg[0], &version, security_flag);
- SMC_RET1(handle, (uint64_t)ret | ((uint64_t)version << 32));
+ SMC_RET1(handle, (u_register_t)ret | ((u_register_t)version << 32));
}
case PM_LOAD_PDI:
{
ret = pm_load_pdi(pm_arg[0], pm_arg[1], pm_arg[2],
security_flag);
- SMC_RET1(handle, (uint64_t)ret);
+ SMC_RET1(handle, (u_register_t)ret);
}
case PM_GET_OP_CHARACTERISTIC:
@@ -412,20 +413,20 @@
ret = pm_get_op_characteristic(pm_arg[0], pm_arg[1], &result,
security_flag);
- SMC_RET1(handle, (uint64_t)ret | ((uint64_t)result << 32));
+ SMC_RET1(handle, (u_register_t)ret | ((u_register_t)result << 32));
}
case PM_SET_MAX_LATENCY:
{
ret = pm_set_max_latency(pm_arg[0], pm_arg[1], security_flag);
- SMC_RET1(handle, (uint64_t)ret);
+ SMC_RET1(handle, (u_register_t)ret);
}
case PM_REGISTER_NOTIFIER:
{
ret = pm_register_notifier(pm_arg[0], pm_arg[1], pm_arg[2],
pm_arg[3], security_flag);
- SMC_RET1(handle, (uint64_t)ret);
+ SMC_RET1(handle, (u_register_t)ret);
}
default:
diff --git a/plat/xilinx/versal/sip_svc_setup.c b/plat/xilinx/versal/sip_svc_setup.c
index bc7d8b7..6f2ff94 100644
--- a/plat/xilinx/versal/sip_svc_setup.c
+++ b/plat/xilinx/versal/sip_svc_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,13 +14,13 @@
#include "pm_svc_main.h"
/* SMC function IDs for SiP Service queries */
-#define VERSAL_SIP_SVC_CALL_COUNT 0x8200ff00
-#define VERSAL_SIP_SVC_UID 0x8200ff01
-#define VERSAL_SIP_SVC_VERSION 0x8200ff03
+#define VERSAL_SIP_SVC_CALL_COUNT U(0x8200ff00)
+#define VERSAL_SIP_SVC_UID U(0x8200ff01)
+#define VERSAL_SIP_SVC_VERSION U(0x8200ff03)
/* SiP Service Calls version numbers */
-#define SIP_SVC_VERSION_MAJOR 0
-#define SIP_SVC_VERSION_MINOR 1
+#define SIP_SVC_VERSION_MAJOR U(0)
+#define SIP_SVC_VERSION_MINOR U(1)
/* These macros are used to identify PM calls from the SMC function ID */
#define PM_FID_MASK 0xf000u
@@ -31,8 +31,8 @@
/* SiP Service UUID */
DEFINE_SVC_UUID2(versal_sip_uuid,
- 0x2ab9e4ec, 0x93b9, 0x11e7, 0xa0, 0x19,
- 0xdf, 0xe0, 0xdb, 0xad, 0x0a, 0xe0);
+ 0x2ab9e4ecU, 0x93b9U, 0x11e7U, 0xa0U, 0x19U,
+ 0xdfU, 0xe0U, 0xdbU, 0xadU, 0x0aU, 0xe0U);
/**
* sip_svc_setup() - Setup SiP Service
@@ -42,7 +42,7 @@
static int32_t sip_svc_setup(void)
{
/* PM implementation as SiP Service */
- pm_setup();
+ (void)pm_setup();
return 0;
}
diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c
index 27541ff..f99af82 100644
--- a/plat/xilinx/versal/versal_ipi.c
+++ b/plat/xilinx/versal/versal_ipi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2019-2021, Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,49 +24,49 @@
[IPI_ID_APU] = {
.ipi_bit_mask = IPI0_TRIG_BIT,
.ipi_reg_base = IPI0_REG_BASE,
- .secure_only = 0,
+ .secure_only = 0U,
},
/* PMC IPI */
[IPI_ID_PMC] = {
.ipi_bit_mask = PMC_IPI_TRIG_BIT,
.ipi_reg_base = IPI0_REG_BASE,
- .secure_only = 0,
+ .secure_only = 0U,
},
/* RPU0 IPI */
[IPI_ID_RPU0] = {
.ipi_bit_mask = IPI1_TRIG_BIT,
.ipi_reg_base = IPI1_REG_BASE,
- .secure_only = 0,
+ .secure_only = 0U,
},
/* RPU1 IPI */
[IPI_ID_RPU1] = {
.ipi_bit_mask = IPI2_TRIG_BIT,
.ipi_reg_base = IPI2_REG_BASE,
- .secure_only = 0,
+ .secure_only = 0U,
},
/* IPI3 IPI */
[IPI_ID_3] = {
.ipi_bit_mask = IPI3_TRIG_BIT,
.ipi_reg_base = IPI3_REG_BASE,
- .secure_only = 0,
+ .secure_only = 0U,
},
/* IPI4 IPI */
[IPI_ID_4] = {
.ipi_bit_mask = IPI4_TRIG_BIT,
.ipi_reg_base = IPI4_REG_BASE,
- .secure_only = 0,
+ .secure_only = 0U,
},
/* IPI5 IPI */
[IPI_ID_5] = {
.ipi_bit_mask = IPI5_TRIG_BIT,
.ipi_reg_base = IPI5_REG_BASE,
- .secure_only = 0,
+ .secure_only = 0U,
},
};