feat(gicv5): add support for building with gicv5
The Generic Interrupt Controller v5 (GICv5) is the next generation of
Arm interrupt controllers. It is a clean slate design and has native
support for the latest Armv9 features. As such it is entirely backwards
incompatible with GICv3/v4.
This patch adds the necessary boilerplate to select a build with GICv5.
The GIC has always had two parts. BL31 deals directly with the CPU
interface while platform code is responsible for managing the IRI. In v5
this split is formalised and the CPU interface, FEAT_GCIE, may be
implemented on its own. So reflect this split in our code with
ENABLE_FEAT_GCIE which only affects BL31 and the GICv5 IRI lies in the
generic GIC driver.
No actual functionality yet.
Change-Id: I97a0c3ba708877c213e50e7ef148e3412aa2af90
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
diff --git a/common/feat_detect.c b/common/feat_detect.c
index 2d80b42..fa817d9 100644
--- a/common/feat_detect.c
+++ b/common/feat_detect.c
@@ -279,6 +279,11 @@
return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT,
ID_AA64MMFR3_EL1_D128_MASK);
}
+static unsigned int read_feat_gcie_id_field(void)
+{
+ return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_GCIE_SHIFT,
+ ID_AA64PFR2_EL1_GCIE_MASK);
+}
static unsigned int read_feat_fpmr_id_field(void)
{
@@ -425,6 +430,8 @@
/* v9.3 features */
check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(),
"D128", 1, 1);
+ check_feature(ENABLE_FEAT_GCIE, read_feat_gcie_id_field(),
+ "GCIE", 1, 1);
/* v9.4 features */
check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), "GCS", 1, 1);