tree daf947db21682ae911e9b73636ec51ae96e92e0a
parent cd39b14b494c829c73a90a527678b81d89c182c8
author Bipin Ravi <bipin.ravi@arm.com> 1617234355 -0500
committer Bipin Ravi <bipin.ravi@arm.com> 1630701896 -0500

errata: workaround for Cortex-A710 erratum 2017096

Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3