feat(intel): restructure sys mgr for Agilex
This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2f52d3eaf47716f7dfc636bbf1a23d68a04f39cb
diff --git a/plat/intel/soc/agilex/include/agilex_memory_controller.h b/plat/intel/soc/agilex/include/agilex_memory_controller.h
index 3746d92..9db4292 100644
--- a/plat/intel/soc/agilex/include/agilex_memory_controller.h
+++ b/plat/intel/soc/agilex/include/agilex_memory_controller.h
@@ -158,6 +158,19 @@
#define AGX_SDRAM_0_LB_ADDR 0x0
#define AGX_DDR_SIZE 0x40000000
+/* Macros */
+#define SOCFPGA_MEMCTRL_ECCCTRL1 0x008
+#define SOCFPGA_MEMCTRL_ERRINTEN 0x010
+#define SOCFPGA_MEMCTRL_ERRINTENS 0x014
+#define SOCFPGA_MEMCTRL_ERRINTENR 0x018
+#define SOCFPGA_MEMCTRL_INTMODE 0x01C
+#define SOCFPGA_MEMCTRL_INTSTAT 0x020
+#define SOCFPGA_MEMCTRL_DIAGINTTEST 0x024
+#define SOCFPGA_MEMCTRL_DERRADDRA 0x02C
+
+#define SOCFPGA_MEMCTRL(_reg) (SOCFPGA_MEMCTRL_REG_BASE \
+ + (SOCFPGA_MEMCTRL_##_reg))
+
int init_hard_memory_controller(void);
#endif
diff --git a/plat/intel/soc/agilex/include/agilex_system_manager.h b/plat/intel/soc/agilex/include/agilex_system_manager.h
new file mode 100644
index 0000000..cb9222d
--- /dev/null
+++ b/plat/intel/soc/agilex/include/agilex_system_manager.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef AGX_SOCFPGA_SYSTEMMANAGER_H
+#define AGX_SOCFPGA_SYSTEMMANAGER_H
+
+#include "socfpga_plat_def.h"
+
+/* System Manager Register Map */
+#define SOCFPGA_SYSMGR_SILICONID_1 0x00
+#define SOCFPGA_SYSMGR_SILICONID_2 0x04
+#define SOCFPGA_SYSMGR_WDDBG 0x08
+#define SOCFPGA_SYSMGR_MPU_STATUS 0x10
+#define SOCFPGA_SYSMGR_SDMMC_L3_MASTER 0x2C
+#define SOCFPGA_SYSMGR_NAND_L3_MASTER 0x34
+#define SOCFPGA_SYSMGR_USB0_L3_MASTER 0x38
+#define SOCFPGA_SYSMGR_USB1_L3_MASTER 0x3C
+#define SOCFPGA_SYSMGR_TSN_GLOBAL 0x40
+#define SOCFPGA_SYSMGR_EMAC_0 0x44 /* TSN_0 */
+#define SOCFPGA_SYSMGR_EMAC_1 0x48 /* TSN_1 */
+#define SOCFPGA_SYSMGR_EMAC_2 0x4C /* TSN_2 */
+#define SOCFPGA_SYSMGR_TSN_0_ACE 0x50
+#define SOCFPGA_SYSMGR_TSN_1_ACE 0x54
+#define SOCFPGA_SYSMGR_TSN_2_ACE 0x58
+#define SOCFPGA_SYSMGR_FPGAINTF_EN_1 0x68
+#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6C
+#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
+#define SOCFPGA_SYSMGR_DMAC0_L3_MASTER 0x74
+#define SOCFPGA_SYSMGR_ETR_L3_MASTER 0x78
+#define SOCFPGA_SYSMGR_DMAC1_L3_MASTER 0x7C
+#define SOCFPGA_SYSMGR_SEC_CTRL_SLT 0x80
+#define SOCFPGA_SYSMGR_OSC_TRIM 0x84
+#define SOCFPGA_SYSMGR_DMAC0_CTRL_STATUS_REG 0x88
+#define SOCFPGA_SYSMGR_DMAC1_CTRL_STATUS_REG 0x8C
+#define SOCFPGA_SYSMGR_ECC_INTMASK_VALUE 0x90
+#define SOCFPGA_SYSMGR_ECC_INTMASK_SET 0x94
+#define SOCFPGA_SYSMGR_ECC_INTMASK_CLR 0x98
+#define SOCFPGA_SYSMGR_ECC_INTMASK_SERR 0x9C
+#define SOCFPGA_SYSMGR_ECC_INTMASK_DERR 0xA0
+/* NOC configuration value for Agilex5 */
+#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xC0
+#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xC4
+#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xC8
+#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xCC
+#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xD0
+#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xD4
+#define SOCFPGA_SYSMGR_FPGA2SOC_CTRL 0xD8
+#define SOCFPGA_SYSMGR_FPGA_CFG 0xDC
+#define SOCFPGA_SYSMGR_GPO 0xE4
+#define SOCFPGA_SYSMGR_GPI 0xE8
+#define SOCFPGA_SYSMGR_MPU 0xF0
+#define SOCFPGA_SYSMGR_SDM_HPS_SPARE 0xF4
+#define SOCFPGA_SYSMGR_HPS_SDM_SPARE 0xF8
+#define SOCFPGA_SYSMGR_DFI_INTF 0xFC
+#define SOCFPGA_SYSMGR_NAND_DD_CTRL 0x100
+#define SOCFPGA_SYSMGR_NAND_PHY_CTRL_REG 0x104
+#define SOCFPGA_SYSMGR_NAND_PHY_TSEL_REG 0x108
+#define SOCFPGA_SYSMGR_NAND_DQ_TIMING_REG 0x10C
+#define SOCFPGA_SYSMGR_PHY_DQS_TIMING_REG 0x110
+#define SOCFPGA_SYSMGR_NAND_PHY_GATE_LPBK_CTRL_REG 0x114
+#define SOCFPGA_SYSMGR_NAND_PHY_DLL_MASTER_CTRL_REG 0x118
+#define SOCFPGA_SYSMGR_NAND_PHY_DLL_SLAVE_CTRL_REG 0x11C
+#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG0 0x120
+#define SOCFPGA_SYSMGR_NAND_DD_DEFAULT_SETTING_REG1 0x124
+#define SOCFPGA_SYSMGR_NAND_DD_STATUS_REG 0x128
+#define SOCFPGA_SYSMGR_NAND_DD_ID_LOW_REG 0x12C
+#define SOCFPGA_SYSMGR_NAND_DD_ID_HIGH_REG 0x130
+#define SOCFPGA_SYSMGR_NAND_WRITE_PROT_EN_REG 0x134
+#define SOCFPGA_SYSMGR_SDMMC_CMD_QUEUE_SETTING_REG 0x138
+#define SOCFPGA_SYSMGR_I3C_SLV_PID_LOW 0x13C
+#define SOCFPGA_SYSMGR_I3C_SLV_PID_HIGH 0x140
+#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_0 0x144
+#define SOCFPGA_SYSMGR_I3C_SLV_CTRL_1 0x148
+#define SOCFPGA_SYSMGR_F2S_BRIDGE_CTRL 0x14C
+#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA0 0x150
+#define SOCFPGA_SYSMGR_DMA_TBU_STASH_CTRL_REG_0_DMA1 0x154
+#define SOCFPGA_SYSMGR_SDM_TBU_STASH_CTRL_REG_1_SDM 0x158
+#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB2 0x15C
+#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_USB3 0x160
+#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_SDMMC 0x164
+#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_NAND 0x168
+#define SOCFPGA_SYSMGR_IO_TBU_STASH_CTRL_REG_2_ETR 0x16C
+#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN0 0x170
+#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN1 0x174
+#define SOCFPGA_SYSMGR_TSN_TBU_STASH_CTRL_REG_3_TSN2 0x178
+#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA0 0x17C
+#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_CTRL_REG_0_DMA1 0x180
+#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_CTRL_REG_1_SDM 0x184
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB2 0x188
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_USB3 0x18C
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_SDMMC 0x190
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_NAND 0x194
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_CTRL_REG_2_ETR 0x198
+#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN0 0x19C
+#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN1 0x1A0
+#define SOCFPGA_SYSMGR_TSN_TBU_STREAM_CTRL_REG_3_TSN2 0x1A4
+#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA0 0x1A8
+#define SOCFPGA_SYSMGR_DMA_TBU_STREAM_ID_AX_REG_0_DMA1 0x1AC
+#define SOCFPGA_SYSMGR_SDM_TBU_STREAM_ID_AX_REG_1_SDM 0x1B0
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB2 0x1B4
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_USB3 0x1B8
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_SDMMC 0x1BC
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_NAND 0x1C0
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_ETR 0x1C4
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN0 0x1C8
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN1 0x1CC
+#define SOCFPGA_SYSMGR_IO_TBU_STREAM_ID_AX_REG_2_TSN2 0x1D0
+#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG0 0x1F0
+#define SOCFPGA_SYSMGR_USB3_MISC_CTRL_REG1 0x1F4
+
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_3 0x20C
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_4 0x210
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_5 0x214
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_6 0x218
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_7 0x21C
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224
+#define SOCFPGA_SYSMGR_MPFE_CONFIG 0x228
+#define SOCFPGA_SYSMGR_MPFE_status 0x22C
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_0 0x230
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_1 0x234
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_2 0x238
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_3 0x23C
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_4 0x240
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_5 0x244
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_6 0x248
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_7 0x24C
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_8 0x250
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_WARM_9 0x254
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_0 0x258
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_1 0x25C
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_2 0x260
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_3 0x264
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_4 0x268
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_5 0x26C
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_6 0x270
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_7 0x274
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_8 0x278
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_POR_9 0x27C
+
+#define DMA0_STREAM_CTRL_REG 0x10D1217C
+#define DMA1_STREAM_CTRL_REG 0x10D12180
+#define SDM_STREAM_CTRL_REG 0x10D12184
+#define USB2_STREAM_CTRL_REG 0x10D12188
+#define USB3_STREAM_CTRL_REG 0x10D1218C
+#define SDMMC_STREAM_CTRL_REG 0x10D12190
+#define NAND_STREAM_CTRL_REG 0x10D12194
+#define ETR_STREAM_CTRL_REG 0x10D12198
+#define TSN0_STREAM_CTRL_REG 0x10D1219C
+#define TSN1_STREAM_CTRL_REG 0x10D121A0
+#define TSN2_STREAM_CTRL_REG 0x10D121A4
+
+/* Stream ID configuration value for Agilex5 */
+#define TSN0 0x00010001
+#define TSN1 0x00020002
+#define TSN2 0x00030003
+#define NAND 0x00040004
+#define SDMMC 0x00050005
+#define USB0 0x00060006
+#define USB1 0x00070007
+#define DMA0 0x00080008
+#define DMA1 0x00090009
+#define SDM 0x000A000A
+#define CORE_SIGHT_DEBUG 0x000B000B
+
+/* Field Masking */
+#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
+#define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4)
+#define IDLE_DATA_LWSOC2FPGA BIT(4)
+#define IDLE_DATA_SOC2FPGA BIT(0)
+#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
+#define SYSMGR_ECC_OCRAM_MASK BIT(1)
+#define SYSMGR_ECC_DDR0_MASK BIT(16)
+#define SYSMGR_ECC_DDR1_MASK BIT(17)
+#define WSTREAMIDEN_REG_CTRL BIT(0)
+#define RSTREAMIDEN_REG_CTRL BIT(1)
+#define WMMUSECSID_REG_VAL BIT(4)
+#define RMMUSECSID_REG_VAL BIT(5)
+
+/* Macros */
+#define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \
+ + (SOCFPGA_SYSMGR_##_reg))
+
+#define ENABLE_STREAMID WSTREAMIDEN_REG_CTRL | \
+ RSTREAMIDEN_REG_CTRL
+#define ENABLE_STREAMID_SECURE_TX WSTREAMIDEN_REG_CTRL | \
+ RSTREAMIDEN_REG_CTRL | \
+ WMMUSECSID_REG_VAL | RMMUSECSID_REG_VAL
+
+#endif /* AGX5_SOCFPGA_SYSTEMMANAGER_H */
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index 4d7198c..85dfeab 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,22 +8,30 @@
#ifndef PLAT_SOCFPGA_DEF_H
#define PLAT_SOCFPGA_DEF_H
+#include "agilex_system_manager.h"
#include <platform_def.h>
/* Platform Setting */
-#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
-#define BOOT_SOURCE BOOT_SOURCE_SDMMC
+#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
+#define BOOT_SOURCE BOOT_SOURCE_SDMMC
+#define PLAT_PRIMARY_CPU 0
+#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
+#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
/* FPGA config helpers */
#define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000
#define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x2000000
+/* QSPI Setting */
+#define CAD_QSPIDATA_OFST 0xff900000
+#define CAD_QSPI_OFFSET 0xff8d2000
+
/* Register Mapping */
#define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000
#define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000)
#define SOCFPGA_MMC_REG_BASE 0xff808000
-
+#define SOCFPGA_MEMCTRL_REG_BASE 0xf8011100
#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
@@ -32,6 +40,53 @@
#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200
#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+#define DRAM_BASE (0x0)
+#define DRAM_SIZE (0x80000000)
+
+#define OCRAM_BASE (0xFFE00000)
+#define OCRAM_SIZE (0x00040000)
+
+#define MEM64_BASE (0x0100000000)
+#define MEM64_SIZE (0x1F00000000)
+
+#define DEVICE1_BASE (0x80000000)
+#define DEVICE1_SIZE (0x60000000)
+
+#define DEVICE2_BASE (0xF7000000)
+#define DEVICE2_SIZE (0x08E00000)
+
+#define DEVICE3_BASE (0xFFFC0000)
+#define DEVICE3_SIZE (0x00008000)
+
+#define DEVICE4_BASE (0x2000000000)
+#define DEVICE4_SIZE (0x0100000000)
+
+#define BL2_BASE (0xffe00000)
+#define BL2_LIMIT (0xffe1b000)
+
+#define BL31_BASE (0x1000)
+#define BL31_LIMIT (0x81000)
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+#define PLAT_UART0_BASE (0xFFC02000)
+#define PLAT_UART1_BASE (0xFFC02100)
+
+/*******************************************************************************
+ * GIC related constants
+ ******************************************************************************/
+#define PLAT_GIC_BASE (0xFFFC0000)
+#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
+#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
+#define PLAT_GICR_BASE 0
+
+#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
+#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
+
/* Platform specific system counter */
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ get_cpu_clk()
diff --git a/plat/intel/soc/agilex/soc/agilex_clock_manager.c b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
index 10ef11b..d32c3f1 100644
--- a/plat/intel/soc/agilex/soc/agilex_clock_manager.c
+++ b/plat/intel/soc/agilex/soc/agilex_clock_manager.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,8 +11,8 @@
#include <lib/mmio.h>
#include "agilex_clock_manager.h"
+#include "agilex_system_manager.h"
#include "socfpga_handoff.h"
-#include "socfpga_system_manager.h"
uint32_t wait_pll_lock(void)
diff --git a/plat/intel/soc/agilex/soc/agilex_pinmux.c b/plat/intel/soc/agilex/soc/agilex_pinmux.c
index 96e1ade..d2a06fb 100644
--- a/plat/intel/soc/agilex/soc/agilex_pinmux.c
+++ b/plat/intel/soc/agilex/soc/agilex_pinmux.c
@@ -7,7 +7,7 @@
#include <lib/mmio.h>
#include "agilex_pinmux.h"
-#include "socfpga_system_manager.h"
+#include "agilex_system_manager.h"
const uint32_t sysmgr_pinmux_array_sel[] = {
0x00000000, 0x00000001, /* usb */
diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S
index 213fd3c..6bf2d82 100644
--- a/plat/intel/soc/common/aarch64/plat_helpers.S
+++ b/plat/intel/soc/common/aarch64/plat_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
index 99d48d2..bebb289 100644
--- a/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
+++ b/plat/intel/soc/common/drivers/ccu/ncore_ccu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,8 @@
#include <lib/mmio.h>
#include "ncore_ccu.h"
+#include "socfpga_plat_def.h"
+#include "socfpga_system_manager.h"
uint32_t poll_active_bit(uint32_t dir);
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index 4e50156..78deebc 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -12,12 +12,15 @@
#include <common/interrupt_props.h>
#include <common/tbbr/tbbr_img_def.h>
#include <plat/common/common_def.h>
+#include "socfpga_plat_def.h"
/* Platform Type */
#define PLAT_SOCFPGA_STRATIX10 1
#define PLAT_SOCFPGA_AGILEX 2
#define PLAT_SOCFPGA_N5X 3
-#define PLAT_SOCFPGA_EMULATOR 0
+#define PLAT_SOCFPGA_AGILEX5 4
+#define SIMICS_RUN 1
+#define MAX_IO_MTD_DEVICES U(1)
/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
#define PLAT_CPU_RELEASE_ADDR 0xffd12210
@@ -32,8 +35,20 @@
#define L2_RESET_DONE_STATUS 0x1228E5E7
/* Define next boot image name and offset */
+/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+
+#ifndef PRELOADED_BL33_BASE
+#define PLAT_NS_IMAGE_OFFSET 0x80200000
+#else
+#define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
+#endif
+#define PLAT_HANDOFF_OFFSET 0x0003F000
+
+#else
#define PLAT_NS_IMAGE_OFFSET 0x10000000
#define PLAT_HANDOFF_OFFSET 0xFFE3F000
+#endif
/*******************************************************************************
* Platform binary types for linking
@@ -49,7 +64,6 @@
/*******************************************************************************
* Generic platform constants
******************************************************************************/
-#define PLAT_PRIMARY_CPU 0
#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0
/* Size of cacheable stacks */
@@ -64,49 +78,27 @@
#define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
-#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
- PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
+ PLATFORM_CLUSTER0_CORE_COUNT)
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
/* Interrupt related constant */
#define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14
-#define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15
-
-#define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER
-#define TSP_SEC_MEM_BASE BL32_BASE
-#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
-/*******************************************************************************
- * Platform memory map related constants
- ******************************************************************************/
-#define DRAM_BASE (0x0)
-#define DRAM_SIZE (0x80000000)
-
-#define OCRAM_BASE (0xFFE00000)
-#define OCRAM_SIZE (0x00040000)
-
-#define MEM64_BASE (0x0100000000)
-#define MEM64_SIZE (0x1F00000000)
-
-#define DEVICE1_BASE (0x80000000)
-#define DEVICE1_SIZE (0x60000000)
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14
+#define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15
-#define DEVICE2_BASE (0xF7000000)
-#define DEVICE2_SIZE (0x08E00000)
+#define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER
+#define TSP_SEC_MEM_BASE BL32_BASE
+#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
-#define DEVICE3_BASE (0xFFFC0000)
-#define DEVICE3_SIZE (0x00008000)
-
-#define DEVICE4_BASE (0x2000000000)
-#define DEVICE4_SIZE (0x0100000000)
/*******************************************************************************
* BL31 specific defines.
@@ -117,33 +109,28 @@
* little space for growth.
*/
-
-#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
-
-#define BL1_RO_BASE (0xffe00000)
-#define BL1_RO_LIMIT (0xffe0f000)
-#define BL1_RW_BASE (0xffe10000)
-#define BL1_RW_LIMIT (0xffe1ffff)
-#define BL1_RW_SIZE (0x14000)
+#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
-#define BL2_BASE (0xffe00000)
-#define BL2_LIMIT (0xffe1b000)
+#define BL1_RO_BASE (0xffe00000)
+#define BL1_RO_LIMIT (0xffe0f000)
+#define BL1_RW_BASE (0xffe10000)
+#define BL1_RW_LIMIT (0xffe1ffff)
+#define BL1_RW_SIZE (0x14000)
-#define BL31_BASE (0x1000)
-#define BL31_LIMIT (0x81000)
+#define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET
-#define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET
+#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16)
+#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8)
-#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16)
-#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8)
+#define CMP_ENTRY 0xFFE3EFF8
-#define PLAT_SEC_WARM_ENTRY 0
+#define PLAT_SEC_WARM_ENTRY 0
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
-#define MAX_XLAT_TABLES 8
-#define MAX_MMAP_REGIONS 16
+#define MAX_XLAT_TABLES 8
+#define MAX_MMAP_REGIONS 16
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
@@ -155,46 +142,34 @@
* a valid mailbox address.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
-#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-
-#define PLAT_GIC_BASE (0xFFFC0000)
-#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
-#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
-#define PLAT_GICR_BASE 0
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
/*******************************************************************************
* UART related constants
******************************************************************************/
-#define PLAT_UART0_BASE (0xFFC02000)
-#define PLAT_UART1_BASE (0xFFC02100)
+#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
+#define PLAT_INTEL_UART_BASE PLAT_UART0_BASE
-#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
-#define PLAT_INTEL_UART_BASE PLAT_UART0_BASE
-
-#if PLAT_SOCFPGA_EMULATOR
-#define PLAT_BAUDRATE (4800)
-#define PLAT_UART_CLOCK (76800)
-#else
-#define PLAT_BAUDRATE (115200)
-#define PLAT_UART_CLOCK (100000000)
-#endif
+#define PLAT_BAUDRATE (115200)
+#define PLAT_UART_CLOCK (100000000)
/*******************************************************************************
* PHY related constants
******************************************************************************/
-#define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII
-#define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII
-#define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII
+#define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII
+#define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII
+#define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII
/*******************************************************************************
- * System counter frequency related constants
+ * GIC related constants
******************************************************************************/
-#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
-#define PLAT_HZ_CONVERT_TO_MHZ (1000000)
+#define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE
+#define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE
-#define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE
-#define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE
+/*******************************************************************************
+ * System counter frequency related constants
+ ******************************************************************************/
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
@@ -223,9 +198,9 @@
#define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp)
-#define MAX_IO_HANDLES 4
-#define MAX_IO_DEVICES 4
-#define MAX_IO_BLOCK_DEVICES 2
+#define MAX_IO_HANDLES 4
+#define MAX_IO_DEVICES 4
+#define MAX_IO_BLOCK_DEVICES 2
#ifndef __ASSEMBLER__
struct socfpga_bl31_params {
@@ -239,4 +214,3 @@
#endif
#endif /* PLATFORM_DEF_H */
-
diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h
index 69ee6d3..8d9ba70 100644
--- a/plat/intel/soc/common/include/socfpga_system_manager.h
+++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -13,26 +13,6 @@
#define SOCFPGA_SYSMGR_SDMMC 0x28
-#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c
-
-#define SOCFPGA_SYSMGR_EMAC_0 0x44
-#define SOCFPGA_SYSMGR_EMAC_1 0x48
-#define SOCFPGA_SYSMGR_EMAC_2 0x4c
-#define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70
-
-#define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0
-#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4
-#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8
-#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc
-#define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0
-#define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4
-
-#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200
-#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204
-#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208
-#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220
-#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224
-
/* Field Masking */
#define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0)
diff --git a/plat/intel/soc/common/sip/socfpga_sip_ecc.c b/plat/intel/soc/common/sip/socfpga_sip_ecc.c
index c4e06a6..c444d48 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_ecc.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_ecc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
- * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2023, ARM Limited and Contributors. All rights reserved.
*/
#include <assert.h>
@@ -11,10 +11,12 @@
#include "socfpga_fcs.h"
#include "socfpga_mailbox.h"
+#include "socfpga_plat_def.h"
#include "socfpga_reset_manager.h"
#include "socfpga_sip_svc.h"
#include "socfpga_system_manager.h"
+
uint32_t intel_ecc_dbe_notification(uint64_t dbe_value)
{
dbe_value &= WARM_RESET_WFI_FLAG;
diff --git a/plat/intel/soc/common/soc/socfpga_emac.c b/plat/intel/soc/common/soc/socfpga_emac.c
index cacfd53..02ff89e 100644
--- a/plat/intel/soc/common/soc/socfpga_emac.c
+++ b/plat/intel/soc/common/soc/socfpga_emac.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,7 @@
#include <platform_def.h>
#include "socfpga_emac.h"
+#include "socfpga_plat_def.h"
#include "socfpga_reset_manager.h"
#include "socfpga_system_manager.h"
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 7010d81..5c99872 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,8 +7,10 @@
#include <lib/mmio.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
+#include <platform_def.h>
#include "socfpga_mailbox.h"
+#include "socfpga_plat_def.h"
#include "socfpga_sip_svc.h"
#include "socfpga_system_manager.h"
diff --git a/plat/intel/soc/common/soc/socfpga_reset_manager.c b/plat/intel/soc/common/soc/socfpga_reset_manager.c
index 77d9a73..a546638 100644
--- a/plat/intel/soc/common/soc/socfpga_reset_manager.c
+++ b/plat/intel/soc/common/soc/socfpga_reset_manager.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,9 +8,11 @@
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
+#include <platform_def.h>
#include "socfpga_f2sdram_manager.h"
#include "socfpga_mailbox.h"
+#include "socfpga_plat_def.h"
#include "socfpga_reset_manager.h"
#include "socfpga_system_manager.h"
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
index bdece93..3b96dfc 100644
--- a/plat/intel/soc/common/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -1,12 +1,16 @@
/*
- * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/debug.h>
+#ifndef SOCFPGA_GIC_V3
#include <drivers/arm/gicv2.h>
+#else
+#include <drivers/arm/gicv3.h>
+#endif
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
@@ -14,8 +18,8 @@
#include "socfpga_mailbox.h"
#include "socfpga_plat_def.h"
#include "socfpga_reset_manager.h"
-#include "socfpga_system_manager.h"
#include "socfpga_sip_svc.h"
+#include "socfpga_system_manager.h"
/*******************************************************************************
@@ -146,11 +150,11 @@
memcpy(addr_buf, &intel_rsu_update_address,
sizeof(intel_rsu_update_address));
-
- if (intel_rsu_update_address)
+ if (intel_rsu_update_address) {
mailbox_rsu_update(addr_buf);
- else
+ } else {
mailbox_reset_cold();
+ }
while (1)
wfi();
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index 79f743f..90cb90a 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,9 +12,10 @@
#include "socfpga_fcs.h"
#include "socfpga_mailbox.h"
+#include "socfpga_plat_def.h"
#include "socfpga_reset_manager.h"
#include "socfpga_sip_svc.h"
-
+#include "socfpga_system_manager.h"
/* Total buffer the driver can hold */
#define FPGA_CONFIG_BUFFER_SIZE 4
diff --git a/plat/intel/soc/common/socfpga_storage.c b/plat/intel/soc/common/socfpga_storage.c
index a2f2c18..79e15d7 100644
--- a/plat/intel/soc/common/socfpga_storage.c
+++ b/plat/intel/soc/common/socfpga_storage.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/