tree 5db07956e53f059f5fa68758aaa6ea1e9fb1636e
parent 6d65bd91a7b04d66dbd6c6d4b98a408d1a7b3ff1
author Sudeep Holla <sudeep.holla@arm.com> 1470323690 +0100
committer Sudeep Holla <sudeep.holla@arm.com> 1470910175 +0100

gicv3: disable Group1 NonSecure interrupts during core powerdown

As per the GICv3 specification, to power down a processor using GICv3
and allow automatic power-on if an interrupt must be sent to a processor,
software must set Enable to zero for all interrupt groups(by writing to
GICC_CTLR or ICC_IGRPEN{0,1}_EL1/3 as appropriate.

Also, NonSecure EL1 software may not be aware of the CPU power state
details and fail to choose right states that require quiescing the CPU
interface. So it's preferred that the PSCI implementation handles it as
it is fully aware of the CPU power states.

This patch adds disabling of Group1 NonSecure interrupts during processor
power down along with Group0 and Group1 Secure interrupts so that all the
interrupt groups are handled at once as per specification.

Change-Id: Ib564d773c9c4c41f2ca9471451c030e3de75e641