tree 38677fea87564a8ce75091decd20980b56578078
parent 7787efe4d03ba13ac71103cf2875af96d8125513
author Jit Loon Lim <jit.loon.lim@intel.com> 1684297571 +0800
committer Jit Loon Lim <jit.loon.lim@intel.com> 1688519311 +0800

feat(intel): reset manager support for Agilex5 SoC FPGA

This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
	1. Added HPS bridges support
		a. SOC2FPGA
		b. LWSOC2FPGA
		c. F2SDRAM
		d. F2SOC
	2. Added EMULATOR support
	3. Added WDT support
	4. Updated product name -> Agilex5
	5. Added SMP support

Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Icab15b25f787fdccce1de75d102604db23beaf11