refactor(ethos-n): move build flags to ethosn_npu.mk
The build flags to enable the Arm(R) Ethos(TM)-N NPU driver are in arm
platform specific make files i.e. plat/arm/common/arm_common.mk. These
flags are renamed and moved to ethosn_npu.mk. Other source and make
files are changed to reflect the changes in these flags.
Signed-off-by: Rajasekaran Kalidoss <rajasekaran.kalidoss@arm.com>
Change-Id: I6fd20225343c574cb5ac1f0f32ff2fc28ef37ea6
diff --git a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
index e512192..9a65e7c 100644
--- a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
+++ b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
@@ -223,17 +223,17 @@
},
#endif /* EL3_PAYLOAD_BASE */
-# if ARM_ETHOSN_NPU_TZMP1
+# if ETHOSN_NPU_TZMP1
{
- .image_id = ARM_ETHOSN_NPU_FW_IMAGE_ID,
+ .image_id = ETHOSN_NPU_FW_IMAGE_ID,
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t, 0),
- .image_info.image_base = ARM_ETHOSN_NPU_FW_IMAGE_BASE,
- .image_info.image_max_size = ARM_ETHOSN_NPU_FW_IMAGE_LIMIT -
- ARM_ETHOSN_NPU_FW_IMAGE_BASE,
+ .image_info.image_base = ETHOSN_NPU_FW_IMAGE_BASE,
+ .image_info.image_max_size = ETHOSN_NPU_FW_IMAGE_LIMIT -
+ ETHOSN_NPU_FW_IMAGE_BASE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
-# endif
+#endif /* ETHOSN_NPU_TZMP1 */
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 647a9d9..4914553 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -114,48 +114,6 @@
endif
endif
-# Arm(R) Ethos(TM)-N NPU SiP service
-ARM_ETHOSN_NPU_DRIVER := 0
-$(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER))
-$(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER))
-
-# Arm(R) Ethos(TM)-N NPU TZMP1
-ARM_ETHOSN_NPU_TZMP1 := 0
-$(eval $(call assert_boolean,ARM_ETHOSN_NPU_TZMP1))
-$(eval $(call add_define,ARM_ETHOSN_NPU_TZMP1))
-ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
- ifeq (${ARM_ETHOSN_NPU_DRIVER},0)
- $(error ARM_ETHOSN_NPU_TZMP1 is only available if ARM_ETHOSN_NPU_DRIVER=1)
- endif
- ifeq (${PLAT},juno)
- $(eval $(call add_define,JUNO_ETHOSN_TZMP1))
- else
- $(error ARM_ETHOSN_NPU_TZMP1 only supported on Juno platform, not ${PLAT})
- endif
-
- ifeq (${TRUSTED_BOARD_BOOT},0)
- # We rely on TRUSTED_BOARD_BOOT to prevent the firmware code from being
- # tampered with, which is required to protect the confidentiality of protected
- # inference data.
- $(error ARM_ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled)
- endif
-
- # We need the FW certificate and key certificate
- $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_key.crt,--npu-fw-key-cert))
- $(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/npu_fw_content.crt,--npu-fw-cert))
- # Needed for our OIDs to be available in tbbr_cot_bl2.c
- $(eval $(call add_define, PLAT_DEF_OID))
- PLAT_INCLUDES += -I${PLAT_DIR}certificate/include
- PLAT_INCLUDES += -Iinclude/drivers/arm/
-
- # We need the firmware to be built into the FIP
- $(eval $(call TOOL_ADD_IMG,ARM_ETHOSN_NPU_FW,--npu-fw))
-
- # Needed so that UUIDs from the FIP are available in BL2
- $(eval $(call add_define,PLAT_DEF_FIP_UUID))
- PLAT_INCLUDES += -I${PLAT_DIR}fip
-endif # ARM_ETHOSN_NPU_TZMP1
-
# Use an implementation of SHA-256 with a smaller memory footprint but reduced
# speed.
$(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
@@ -348,18 +306,18 @@
plat/arm/common/arm_topology.c \
plat/common/plat_psci_common.c
-ifneq ($(filter 1,${ENABLE_PMF} ${ARM_ETHOSN_NPU_DRIVER}),)
+ifneq ($(filter 1,${ENABLE_PMF} ${ETHOSN_NPU_DRIVER}),)
ARM_SVC_HANDLER_SRCS :=
ifeq (${ENABLE_PMF},1)
ARM_SVC_HANDLER_SRCS += lib/pmf/pmf_smc.c
endif
-ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
+ifeq (${ETHOSN_NPU_DRIVER},1)
ARM_SVC_HANDLER_SRCS += plat/arm/common/fconf/fconf_ethosn_getter.c \
drivers/delay_timer/delay_timer.c \
drivers/arm/ethosn/ethosn_smc.c
-ifeq (${ARM_ETHOSN_NPU_TZMP1},1)
+ifeq (${ETHOSN_NPU_TZMP1},1)
ARM_SVC_HANDLER_SRCS += drivers/arm/ethosn/ethosn_big_fw.c
endif
endif
diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c
index af8a02f..6af23a7 100644
--- a/plat/arm/common/arm_sip_svc.c
+++ b/plat/arm/common/arm_sip_svc.c
@@ -34,13 +34,13 @@
#endif /* USE_DEBUGFS */
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
if (ethosn_smc_setup() != 0) {
return 1;
}
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif /* ETHOSN_NPU_DRIVER */
return 0;
}
@@ -81,14 +81,14 @@
#endif /* USE_DEBUGFS */
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
if (is_ethosn_fid(smc_fid)) {
return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
handle, flags);
}
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif /* ETHOSN_NPU_DRIVER */
switch (smc_fid) {
case ARM_SIP_SVC_EXE_STATE_SWITCH: {
@@ -114,10 +114,10 @@
/* PMF calls */
call_count += PMF_NUM_SMC_CALLS;
-#if ARM_ETHOSN_NPU_DRIVER
+#if ETHOSN_NPU_DRIVER
/* ETHOSN calls */
call_count += ETHOSN_NUM_SMC_CALLS;
-#endif /* ARM_ETHOSN_NPU_DRIVER */
+#endif /* ETHOSN_NPU_DRIVER */
/* State switch call */
call_count += 1;
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c
index 743cc90..27acc3a 100644
--- a/plat/arm/common/fconf/arm_fconf_io.c
+++ b/plat/arm/common/fconf/arm_fconf_io.c
@@ -68,9 +68,9 @@
[TOS_FW_CONFIG_ID] = {UUID_TOS_FW_CONFIG},
[NT_FW_CONFIG_ID] = {UUID_NT_FW_CONFIG},
[RMM_IMAGE_ID] = {UUID_REALM_MONITOR_MGMT_FIRMWARE},
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_IMAGE_ID] = {UUID_ETHOSN_FW},
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT},
@@ -91,10 +91,10 @@
[SIP_SP_CONTENT_CERT_ID] = {UUID_SIP_SECURE_PARTITION_CONTENT_CERT},
[PLAT_SP_CONTENT_CERT_ID] = {UUID_PLAT_SECURE_PARTITION_CONTENT_CERT},
#endif
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE},
- [ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_KEY_CERT_ID] = {UUID_ETHOSN_FW_KEY_CERTIFICATE},
+ [ETHOSN_NPU_FW_CONTENT_CERT_ID] = {UUID_ETHOSN_FW_CONTENT_CERTIFICATE},
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@@ -198,13 +198,13 @@
(uintptr_t)&arm_uuid_spec[NT_FW_CONFIG_ID],
open_fip
},
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_IMAGE_ID] = {
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_IMAGE_ID] = {
&fip_dev_handle,
- (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_IMAGE_ID],
+ (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_IMAGE_ID],
open_fip
},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
@@ -285,18 +285,18 @@
open_fip
},
#endif
-#if ARM_ETHOSN_NPU_TZMP1
- [ARM_ETHOSN_NPU_FW_KEY_CERT_ID] = {
+#if ETHOSN_NPU_TZMP1
+ [ETHOSN_NPU_FW_KEY_CERT_ID] = {
&fip_dev_handle,
- (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_KEY_CERT_ID],
+ (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_KEY_CERT_ID],
open_fip
},
- [ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID] = {
+ [ETHOSN_NPU_FW_CONTENT_CERT_ID] = {
&fip_dev_handle,
- (uintptr_t)&arm_uuid_spec[ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID],
+ (uintptr_t)&arm_uuid_spec[ETHOSN_NPU_FW_CONTENT_CERT_ID],
open_fip
},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@@ -305,11 +305,11 @@
#define FCONF_ARM_IO_UUID_NUM_BASE U(10)
-#if ARM_ETHOSN_NPU_TZMP1
+#if ETHOSN_NPU_TZMP1
#define FCONF_ARM_IO_UUID_NUM_NPU U(1)
#else
#define FCONF_ARM_IO_UUID_NUM_NPU U(0)
-#endif
+#endif /* ETHOSN_NPU_TZMP1 */
#if TRUSTED_BOARD_BOOT
#define FCONF_ARM_IO_UUID_NUM_TBB U(12)
@@ -323,11 +323,11 @@
#define FCONF_ARM_IO_UUID_NUM_SPD U(0)
#endif /* TRUSTED_BOARD_BOOT && defined(SPD_spmd) */
-#if TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1
+#if TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1
#define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(2)
#else
#define FCONF_ARM_IO_UUID_NUM_NPU_TBB U(0)
-#endif /* TRUSTED_BOARD_BOOT && ARM_ETHOSN_NPU_TZMP1 */
+#endif /* TRUSTED_BOARD_BOOT && ETHOSN_NPU_TZMP1 */
#define FCONF_ARM_IO_UUID_NUMBER FCONF_ARM_IO_UUID_NUM_BASE + \
FCONF_ARM_IO_UUID_NUM_NPU + \
@@ -355,9 +355,9 @@
{SOC_FW_CONFIG_ID, "soc_fw_cfg_uuid"},
{TOS_FW_CONFIG_ID, "tos_fw_cfg_uuid"},
{NT_FW_CONFIG_ID, "nt_fw_cfg_uuid"},
-#if ARM_ETHOSN_NPU_TZMP1
- {ARM_ETHOSN_NPU_FW_IMAGE_ID, "arm_ethosn_npu_fw_uuid"},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ {ETHOSN_NPU_FW_IMAGE_ID, "ethosn_npu_fw_uuid"},
+#endif /* ETHOSN_NPU_TZMP1 */
#if TRUSTED_BOARD_BOOT
{CCA_CONTENT_CERT_ID, "cca_cert_uuid"},
{CORE_SWD_KEY_CERT_ID, "core_swd_cert_uuid"},
@@ -375,10 +375,10 @@
{SIP_SP_CONTENT_CERT_ID, "sip_sp_content_cert_uuid"},
{PLAT_SP_CONTENT_CERT_ID, "plat_sp_content_cert_uuid"},
#endif
-#if ARM_ETHOSN_NPU_TZMP1
- {ARM_ETHOSN_NPU_FW_KEY_CERT_ID, "arm_ethosn_npu_fw_key_cert_uuid"},
- {ARM_ETHOSN_NPU_FW_CONTENT_CERT_ID, "arm_ethosn_npu_fw_content_cert_uuid"},
-#endif /* ARM_ETHOSN_NPU_TZMP1 */
+#if ETHOSN_NPU_TZMP1
+ {ETHOSN_NPU_FW_KEY_CERT_ID, "ethosn_npu_fw_key_cert_uuid"},
+ {ETHOSN_NPU_FW_CONTENT_CERT_ID, "ethosn_npu_fw_content_cert_uuid"},
+#endif /* ETHOSN_NPU_TZMP1 */
#endif /* TRUSTED_BOARD_BOOT */
};