| commit | 84275bfdf32c566c6b99bdaf543be7ae356c13c6 | [log] [tgz] |
|---|---|---|
| author | Tejas Patel <tejas.patel@xilinx.com> | Tue Sep 01 04:43:53 2020 -0700 |
| committer | Manish Pandey <manish.pandey2@arm.com> | Mon Dec 07 11:10:13 2020 +0000 |
| tree | 92e406d36aaae1084dc19636198d2edcd192c664 | |
| parent | 5c154e15be4bc53fa7d6ede347658e96427f3b9c [diff] |
plat: xilinx: versal: Add support to get clock rate value Add support to get clock's rate value. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I3ed881053ef323b2ca73e13edd0affda860d381d