| commit | 830e74e1278c57d24bc749ca7ff8d56d5b64cb99 | [log] [tgz] |
|---|---|---|
| author | Joanna Farley <joanna.farley@arm.com> | Wed Nov 09 12:49:28 2022 +0100 |
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | Wed Nov 09 12:49:28 2022 +0100 |
| tree | 32015403ece3ce8e15033ec4547b0c343425107b | |
| parent | 73040572e80a1aab58d9155a5e30a6f326fb5a47 [diff] | |
| parent | 266e07b504d12954b351a607e4f62abc0218d273 [diff] |
Merge "fix(versal-net): add default values for silicon" into integration
diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c index 97080e9..c9942d6 100644 --- a/plat/xilinx/versal_net/bl31_versal_net_setup.c +++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c
@@ -88,6 +88,9 @@ uart_clock = 25000000; break; case VERSAL_NET_SILICON: + cpu_clock = 100000000; + uart_clock = 100000000; + break; default: panic(); }