commit 82e63c8901c82e2aa878f73031dfc76c6b60ba01
author Hiroyuki Nakano <hiroyuki.nakano.cj@renesas.com> Thu May 16 09:21:37 2019 +0900
committer Marek Vasut <marek.vasut+renesas@gmail.com> Fri Jul 12 06:38:10 2019 +0200
tree fa76773f6a68b96ae8c1cbe1c29e27c9f1bf8c9c
parent 2d592b71cccfad9c504550ce368c94808a6c708e

rcar_gen3: drivers: ddr-a: Update E3 DDR setting

[IPL/DDR]
- Update E3 DDR setting rev.0.12.

Signed-off-by: Hiroyuki Nakano <hiroyuki.nakano.cj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Change-Id: Ic9fb7ed1cd7588fab169a99c4070a8dfc40038dc

drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h

diff --git a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
index 2e9a5bf..1a96a69 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,7 @@
 
 #include <stdint.h>
 
-#define RCAR_E3_DDR_VERSION    "rev.0.11"
+#define RCAR_E3_DDR_VERSION    "rev.0.12"
 
 #ifdef ddr_qos_init_setting
    #define REFRESH_RATE  3900               /*  Average periodic refresh interval[ns]. Support 3900,7800 */