| commit | 82254eec4af748a77241f08978e795a4fb23f2e5 | [log] [tgz] |
|---|---|---|
| author | Sieu Mun Tang <sieu.mun.tang@intel.com> | Tue Oct 22 00:52:09 2024 +0800 |
| committer | Sieu Mun Tang <sieu.mun.tang@intel.com> | Tue Oct 22 09:46:18 2024 +0800 |
| tree | fcfe1cf677c9445568f7cd9f03c7033e1fc4daf3 | |
| parent | 9dd2c1826b60aada7b1d28dc8fa678d207e9428e [diff] [blame] |
fix(intel): fix CCU for cache maintenance Fix CCU settings for cache maintenance. Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93 Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
diff --git a/plat/intel/soc/agilex5/include/agilex5_cache.h b/plat/intel/soc/agilex5/include/agilex5_cache.h index 095d99e..f7801b9 100644 --- a/plat/intel/soc/agilex5/include/agilex5_cache.h +++ b/plat/intel/soc/agilex5/include/agilex5_cache.h
@@ -8,5 +8,6 @@ #define AGX5_CACHE_H void invalidate_dcache_all(void); +void invalidate_cache_low_el(void); #endif /* AGX5_CACHE_H */