fix(intel): fix CCU for cache maintenance
Fix CCU settings for cache maintenance.
Change-Id: I9af35a6ab7aa9ee20e05ba82d0a042948ac29a93
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
diff --git a/plat/intel/soc/agilex5/include/agilex5_cache.h b/plat/intel/soc/agilex5/include/agilex5_cache.h
index 095d99e..f7801b9 100644
--- a/plat/intel/soc/agilex5/include/agilex5_cache.h
+++ b/plat/intel/soc/agilex5/include/agilex5_cache.h
@@ -8,5 +8,6 @@
#define AGX5_CACHE_H
void invalidate_dcache_all(void);
+void invalidate_cache_low_el(void);
#endif /* AGX5_CACHE_H */
diff --git a/plat/intel/soc/agilex5/soc/agilex5_cache.S b/plat/intel/soc/agilex5/soc/agilex5_cache.S
index a174386..52ed5d3 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_cache.S
+++ b/plat/intel/soc/agilex5/soc/agilex5_cache.S
@@ -9,6 +9,21 @@
#include <plat_macros.S>
.globl invalidate_dcache_all
+ .globl invalidate_cache_low_el
+ /* --------------------------------------------------------
+ * Invalidate for NS EL2 and EL1
+ * --------------------------------------------------------
+ */
+func invalidate_cache_low_el
+ mrs x0,SCR_EL3
+ orr x1,x0,#SCR_NS_BIT
+ msr SCR_EL3, x1
+ isb
+ tlbi ALLE2
+ dsb sy
+ tlbi ALLE1
+ dsb sy
+endfunc invalidate_cache_low_el
.pushsection .text.asm_dcache_level, "ax"
func asm_dcache_level
diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S
index 6ce4148..9a17587 100644
--- a/plat/intel/soc/common/aarch64/plat_helpers.S
+++ b/plat/intel/soc/common/aarch64/plat_helpers.S
@@ -21,7 +21,6 @@
.globl plat_crash_console_flush
.globl platform_mem_init
.globl plat_secondary_cpus_bl31_entry
- .globl invalidate_cache_low_el
.globl plat_get_my_entrypoint
@@ -216,18 +215,3 @@
_exception_vectors=runtime_exceptions \
_pie_fixup_size=BL31_LIMIT - BL31_BASE
endfunc plat_secondary_cpus_bl31_entry
-
-/* --------------------------------------------------------
- * Invalidate for NS EL2 and EL1
- * --------------------------------------------------------
- */
-func invalidate_cache_low_el
- mrs x0,SCR_EL3
- orr x1,x0,#SCR_NS_BIT
- msr SCR_EL3, x1
- isb
- tlbi ALLE2
- dsb sy
- tlbi ALLE1
- dsb sy
-endfunc invalidate_cache_low_el
diff --git a/plat/intel/soc/common/include/socfpga_private.h b/plat/intel/soc/common/include/socfpga_private.h
index b54b402..a0d4180 100644
--- a/plat/intel/soc/common/include/socfpga_private.h
+++ b/plat/intel/soc/common/include/socfpga_private.h
@@ -65,6 +65,4 @@
void plat_secondary_cpus_bl31_entry(void);
-void invalidate_cache_low_el(void);
-
#endif /* SOCFPGA_PRIVATE_H */
diff --git a/plat/intel/soc/common/socfpga_psci.c b/plat/intel/soc/common/socfpga_psci.c
index 8baa8dd..8dc39e2 100644
--- a/plat/intel/soc/common/socfpga_psci.c
+++ b/plat/intel/soc/common/socfpga_psci.c
@@ -17,6 +17,9 @@
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <plat/common/platform.h>
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+#include "agilex5_cache.h"
+#endif
#include "ccu/ncore_ccu.h"
#include "socfpga_mailbox.h"
#include "socfpga_plat_def.h"