diff --git a/.gitignore b/.gitignore
index 2abfffb..64b389b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -34,3 +34,7 @@
 GRTAGS
 GSYMS
 GTAGS
+
+# Ctags
+tags
+
diff --git a/Makefile b/Makefile
index bd52c0b..5167d2e 100644
--- a/Makefile
+++ b/Makefile
@@ -255,7 +255,7 @@
 # General warnings
 WARNINGS		:=	-Wall -Wmissing-include-dirs -Wunused	\
 				-Wdisabled-optimization	-Wvla -Wshadow	\
-				-Wno-unused-parameter
+				-Wno-unused-parameter -Wredundant-decls
 
 # Additional warnings
 # Level 1
@@ -274,7 +274,6 @@
 WARNING3 += -Wconversion
 WARNING3 += -Wpacked
 WARNING3 += -Wpointer-arith
-WARNING3 += -Wredundant-decls
 WARNING3 += -Wswitch-default
 
 ifeq (${W},1)
@@ -604,6 +603,14 @@
     endif
 endif
 
+ifeq ($(MEASURED_BOOT),1)
+    ifneq (${TRUSTED_BOARD_BOOT},1)
+        $(error MEASURED_BOOT requires TRUSTED_BOARD_BOOT=1")
+    else
+        $(info MEASURED_BOOT is an experimental feature)
+    endif
+endif
+
 ################################################################################
 # Process platform overrideable behaviour
 ################################################################################
@@ -695,6 +702,9 @@
 PRINT_MEMORY_MAP_PATH		?=	tools/memory
 PRINT_MEMORY_MAP		?=	${PRINT_MEMORY_MAP_PATH}/print_memory_map.py
 
+# Variables for use with documentation build using Sphinx tool
+DOCS_PATH		?=	docs
+
 ################################################################################
 # Include BL specific makefiles
 ################################################################################
@@ -751,6 +761,7 @@
 $(eval $(call assert_boolean,GICV2_G0_FOR_EL3))
 $(eval $(call assert_boolean,HANDLE_EA_EL3_FIRST))
 $(eval $(call assert_boolean,HW_ASSISTED_COHERENCY))
+$(eval $(call assert_boolean,MEASURED_BOOT))
 $(eval $(call assert_boolean,NS_TIMER_SWITCH))
 $(eval $(call assert_boolean,OVERRIDE_LIBC))
 $(eval $(call assert_boolean,PL011_GENERIC_UART))
@@ -817,6 +828,7 @@
 $(eval $(call add_define,HANDLE_EA_EL3_FIRST))
 $(eval $(call add_define,HW_ASSISTED_COHERENCY))
 $(eval $(call add_define,LOG_LEVEL))
+$(eval $(call add_define,MEASURED_BOOT))
 $(eval $(call add_define,NS_TIMER_SWITCH))
 $(eval $(call add_define,PL011_GENERIC_UART))
 $(eval $(call add_define,PLAT_${PLAT}))
@@ -869,7 +881,7 @@
 # Build targets
 ################################################################################
 
-.PHONY:	all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip fwu_fip certtool dtbs memmap
+.PHONY:	all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool sptool fip fwu_fip certtool dtbs memmap doc
 .SUFFIXES:
 
 all: msg_start
@@ -1009,7 +1021,7 @@
 
 .PHONY: ${CRTTOOL}
 ${CRTTOOL}:
-	${Q}${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} --no-print-directory -C ${CRTTOOLPATH}
+	${Q}${MAKE} PLAT=${PLAT} USE_TBBR_DEFS=${USE_TBBR_DEFS} COT=${COT} --no-print-directory -C ${CRTTOOLPATH}
 	@${ECHO_BLANK_LINE}
 	@echo "Built $@ successfully"
 	@${ECHO_BLANK_LINE}
@@ -1067,6 +1079,10 @@
 memmap: all
 	${Q}${PYTHON} $(PRINT_MEMORY_MAP) $(BUILD_PLAT)
 
+doc:
+	@echo "  BUILD DOCUMENTATION"
+	${Q}${MAKE} --no-print-directory -C ${DOCS_PATH} html
+
 cscope:
 	@echo "  CSCOPE"
 	${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files
@@ -1107,6 +1123,7 @@
 	@echo "  sptool         Build the Secure Partition Package creation tool"
 	@echo "  dtbs           Build the Device Tree Blobs (if required for the platform)"
 	@echo "  memmap         Print the memory map of the built binaries"
+	@echo "  doc            Build html based documentation using Sphinx tool"
 	@echo ""
 	@echo "Note: most build targets require PLAT to be set to a specific platform."
 	@echo ""
diff --git a/bl1/tbbr/tbbr_img_desc.c b/bl1/tbbr/tbbr_img_desc.c
index e8df73d..4836712 100644
--- a/bl1/tbbr/tbbr_img_desc.c
+++ b/bl1/tbbr/tbbr_img_desc.c
@@ -1,12 +1,11 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <platform_def.h>
 
-#include <bl1/bl1.h>
 #include <bl1/tbbr/tbbr_img_desc.h>
 #include <common/bl_common.h>
 
diff --git a/bl2/bl2_image_load_v2.c b/bl2/bl2_image_load_v2.c
index dd53e1d..1fbdbab 100644
--- a/bl2/bl2_image_load_v2.c
+++ b/bl2/bl2_image_load_v2.c
@@ -68,7 +68,8 @@
 			err = load_auth_image(bl2_node_info->image_id,
 				bl2_node_info->image_info);
 			if (err) {
-				ERROR("BL2: Failed to load image (%i)\n", err);
+				ERROR("BL2: Failed to load image id %d (%i)\n",
+				      bl2_node_info->image_id, err);
 				plat_error_handler(err);
 			}
 		} else {
diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S
index 665a05e..2d672dd 100644
--- a/bl31/aarch64/bl31_entrypoint.S
+++ b/bl31/aarch64/bl31_entrypoint.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -110,13 +110,17 @@
 	 * caches and participate in coherency.
 	 * --------------------------------------------------------------------
 	 */
-	adr	x0, __DATA_START__
-	adr	x1, __DATA_END__
+	adrp	x0, __DATA_START__
+	add	x0, x0, :lo12:__DATA_START__
+	adrp	x1, __DATA_END__
+	add	x1, x1, :lo12:__DATA_END__
 	sub	x1, x1, x0
 	bl	clean_dcache_range
 
-	adr	x0, __BSS_START__
-	adr	x1, __BSS_END__
+	adrp	x0, __BSS_START__
+	add	x0, x0, :lo12:__BSS_START__
+	adrp	x1, __BSS_END__
+	add	x1, x1, :lo12:__BSS_END__
 	sub	x1, x1, x0
 	bl	clean_dcache_range
 
diff --git a/bl31/aarch64/runtime_exceptions.S b/bl31/aarch64/runtime_exceptions.S
index 7f739a9..5b37388 100644
--- a/bl31/aarch64/runtime_exceptions.S
+++ b/bl31/aarch64/runtime_exceptions.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -414,7 +414,8 @@
 	orr	x16, x16, x15, lsl #FUNCID_OEN_WIDTH
 
 	/* Load descriptor index from array of indices */
-	adr	x14, rt_svc_descs_indices
+	adrp	x14, rt_svc_descs_indices
+	add	x14, x14, :lo12:rt_svc_descs_indices
 	ldrb	w15, [x14, x16]
 
 	/* Any index greater than 127 is invalid. Check bit 7. */
diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index c7185a8..4a1c5f3 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -208,6 +208,7 @@
      * Define a linker symbol to mark end of the RW memory area for this
      * image.
      */
+    . = ALIGN(PAGE_SIZE);
     __RW_END__ = .;
     __BL31_END__ = .;
 
diff --git a/bl31/bl31_context_mgmt.c b/bl31/bl31_context_mgmt.c
index d41979f..9175ee3 100644
--- a/bl31/bl31_context_mgmt.c
+++ b/bl31/bl31_context_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,7 +11,6 @@
 #include <context.h>
 #include <lib/el3_runtime/context_mgmt.h>
 #include <lib/el3_runtime/cpu_data.h>
-#include <plat/common/platform.h>
 
 /*******************************************************************************
  * This function returns a pointer to the most recent 'cpu_context' structure
diff --git a/bl31/interrupt_mgmt.c b/bl31/interrupt_mgmt.c
index e6efad3..b8cc3de 100644
--- a/bl31/interrupt_mgmt.c
+++ b/bl31/interrupt_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,6 +17,11 @@
  * registered interrupt handlers for each interrupt type.
  * The field descriptions are:
  *
+ * 'scr_el3[2]'  : Mapping of the routing model in the 'flags' field to the
+ *                 value of the SCR_EL3.IRQ or FIQ bit for each security state.
+ *                 There are two instances of this field corresponding to the
+ *                 two security states.
+ *
  * 'flags' : Bit[0], Routing model for this interrupt type when execution is
  *                   not in EL3 in the secure state. '1' implies that this
  *                   interrupt will be routed to EL3. '0' implies that this
@@ -28,16 +33,11 @@
  *                   interrupt will be routed to the current exception level.
  *
  *           All other bits are reserved and SBZ.
- *
- * 'scr_el3[2]'  : Mapping of the routing model in the 'flags' field to the
- *                 value of the SCR_EL3.IRQ or FIQ bit for each security state.
- *                 There are two instances of this field corresponding to the
- *                 two security states.
  ******************************************************************************/
 typedef struct intr_type_desc {
 	interrupt_type_handler_t handler;
+	u_register_t scr_el3[2];
 	uint32_t flags;
-	uint32_t scr_el3[2];
 } intr_type_desc_t;
 
 static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES];
@@ -78,9 +78,9 @@
  * routing model (expressed through the IRQ and FIQ bits) for a security state
  * which was stored through a call to 'set_routing_model()' earlier.
  ******************************************************************************/
-uint32_t get_scr_el3_from_routing_model(uint32_t security_state)
+u_register_t get_scr_el3_from_routing_model(uint32_t security_state)
 {
-	uint32_t scr_el3;
+	u_register_t scr_el3;
 
 	assert(sec_state_is_valid(security_state));
 	scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state];
@@ -103,7 +103,7 @@
 
 	flag = get_interrupt_rm_flag(interrupt_type_flags, security_state);
 	bit_pos = plat_interrupt_type_to_line(type, security_state);
-	intr_type_descs[type].scr_el3[security_state] = flag << bit_pos;
+	intr_type_descs[type].scr_el3[security_state] = (u_register_t)flag << bit_pos;
 
 	/*
 	 * Update scr_el3 only if there is a context available. If not, it
diff --git a/common/fdt_wrappers.c b/common/fdt_wrappers.c
index e67fdb0..ca5b455 100644
--- a/common/fdt_wrappers.c
+++ b/common/fdt_wrappers.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -103,6 +103,41 @@
 }
 
 /*
+ * Read bytes from a given property of the given node. Any number of
+ * bytes of the property can be read. The fdt pointer is updated.
+ * Returns 0 on success, and -1 on error.
+ */
+int fdtw_read_bytes(const void *dtb, int node, const char *prop,
+		    unsigned int length, void *value)
+{
+	const void *ptr;
+	int value_len;
+
+	assert(dtb != NULL);
+	assert(prop != NULL);
+	assert(value != NULL);
+	assert(node >= 0);
+
+	/* Access property and obtain its length (in bytes) */
+	ptr = fdt_getprop_namelen(dtb, node, prop, (int)strlen(prop),
+					&value_len);
+	if (ptr == NULL) {
+		WARN("Couldn't find property %s in dtb\n", prop);
+		return -1;
+	}
+
+	/* Verify that property length is not less than number of bytes */
+	if ((unsigned int)value_len < length) {
+		WARN("Property length mismatch\n");
+		return -1;
+	}
+
+	(void)memcpy(value, ptr, length);
+
+	return 0;
+}
+
+/*
  * Read string from a given property of the given node. Up to 'size - 1'
  * characters are read, and a NUL terminator is added. Returns 0 on success,
  * and -1 upon error.
@@ -167,3 +202,45 @@
 
 	return 0;
 }
+
+/*
+ * Write bytes in place to a given property of the given node.
+ * Any number of bytes of the property can be written.
+ * Returns 0 on success, and < 0 on error.
+ */
+int fdtw_write_inplace_bytes(void *dtb, int node, const char *prop,
+			     unsigned int length, const void *data)
+{
+	const void *ptr;
+	int namelen, value_len, err;
+
+	assert(dtb != NULL);
+	assert(prop != NULL);
+	assert(data != NULL);
+	assert(node >= 0);
+
+	namelen = (int)strlen(prop);
+
+	/* Access property and obtain its length in bytes */
+	ptr = fdt_getprop_namelen(dtb, node, prop, namelen, &value_len);
+	if (ptr == NULL) {
+		WARN("Couldn't find property %s in dtb\n", prop);
+		return -1;
+	}
+
+	/* Verify that property length is not less than number of bytes */
+	if ((unsigned int)value_len < length) {
+		WARN("Property length mismatch\n");
+		return -1;
+	}
+
+	/* Set property value in place */
+	err = fdt_setprop_inplace_namelen_partial(dtb, node, prop,
+						  namelen, 0,
+						  data, (int)length);
+	if (err != 0) {
+		WARN("Set property %s failed with error %d\n", prop, err);
+	}
+
+	return err;
+}
diff --git a/docs/change-log-upcoming.rst b/docs/change-log-upcoming.rst
index 3d7d509..14280cb 100644
--- a/docs/change-log-upcoming.rst
+++ b/docs/change-log-upcoming.rst
@@ -23,7 +23,7 @@
    - Example: "Add support for Branch Target Identification (BTI)"
 
 - Build System
-   - Example: "Add support for default stack-protector flag"
+   - Add support for documentation build as a target in Makefile
 
 - CPU Support
    - Example: "cortex-a55: Workaround for erratum 1221012"
diff --git a/docs/components/exception-handling.rst b/docs/components/exception-handling.rst
index 3f38685..e330a62 100644
--- a/docs/components/exception-handling.rst
+++ b/docs/components/exception-handling.rst
@@ -467,7 +467,7 @@
 Non-secure world to request Secure services. They're broadly classified as
 *Fast* or *Yielding* (see `SMCCC`__).
 
-.. __: `http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html`
+.. __: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
 
 -  *Fast* SMCs are atomic from the caller's point of view. I.e., they return
    to the caller only when the Secure world has finished serving the request.
@@ -621,6 +621,6 @@
 
 --------------
 
-*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.*
 
 .. _SDEI specification: http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index fc45455..e9747af 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -128,6 +128,9 @@
    ``plat_secondary_cold_boot_setup()`` platform porting interfaces do not need
    to be implemented in this case.
 
+-  ``COT``: When Trusted Boot is enabled, selects the desired chain of trust.
+   Defaults to ``tbbr``.
+
 -  ``CRASH_REPORTING``: A non-zero value enables a console dump of processor
    register state when an unexpected exception occurs during execution of
    BL31. This option defaults to the value of ``DEBUG`` - i.e. by default
@@ -307,8 +310,8 @@
    EL1 for handling. The default value of this option is ``0``, which means the
    Group 0 interrupts are assumed to be handled by Secure EL1.
 
-   .. __: `platform-interrupt-controller-API.rst`
-   .. __: `interrupt-framework-design.rst`
+   .. __: platform-interrupt-controller-API.rst
+   .. __: interrupt-framework-design.rst
 
 -  ``HANDLE_EA_EL3_FIRST``: When set to ``1``, External Aborts and SError
    Interrupts will be always trapped in EL3 i.e. in BL31 at runtime. When set to
@@ -387,6 +390,11 @@
    All log output up to and including the selected log level is compiled into
    the build. The default value is 40 in debug builds and 20 in release builds.
 
+-  ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
+   feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set.
+   This option defaults to 0 and is an experimental feature in the stage of
+   development.
+
 -  ``NON_TRUSTED_WORLD_KEY``: This option is used when ``GENERATE_COT=1``. It
    specifies the file that contains the Non-Trusted World private key in PEM
    format. If ``SAVE_KEYS=1``, this file name will be used to save the key.
@@ -649,4 +657,4 @@
 
 --------------
 
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
diff --git a/docs/getting_started/docs-build.rst b/docs/getting_started/docs-build.rst
index c5625e9..91b1b3a 100644
--- a/docs/getting_started/docs-build.rst
+++ b/docs/getting_started/docs-build.rst
@@ -56,21 +56,28 @@
 Building rendered documentation
 -------------------------------
 
-From the ``docs`` directory of the project, run the following commands. It is
-important to note that you will not get the correct result if the commands are
-run from the project root directory, as that would invoke the top-level Makefile
-for |TF-A| itself.
+Documents can be built into HTML-formatted pages from project root directory by
+running the following command.
 
 .. code:: shell
 
-   make clean
-   make html
+   make doc
 
 Output from the build process will be placed in:
 
 ::
 
-   <tf-a root>/docs/build/html/
+   docs/build/html/
+
+We also support building documentation in other formats. From the ``docs``
+directory of the project, run the following command to see the supported
+formats. It is important to note that you will not get the correct result if
+the command is run from the project root directory, as that would invoke the
+top-level Makefile for |TF-A| itself.
+
+.. code:: shell
+
+   make help
 
 --------------
 
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index bb14717..e8357b3 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -2763,6 +2763,19 @@
    to ``no``. If any of the options ``EL3_PAYLOAD_BASE`` or ``PRELOADED_BL33_BASE``
    are used, this flag will be set to ``no`` automatically.
 
+Platform include paths
+----------------------
+
+Platforms are allowed to add more include paths to be passed to the compiler.
+The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in
+particular for the file ``platform_def.h``.
+
+Example:
+
+.. code:: c
+
+  PLAT_INCLUDES  += -Iinclude/plat/myplat/include
+
 C Library
 ---------
 
@@ -2844,7 +2857,7 @@
 
 --------------
 
-*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
 
 .. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
 .. _Arm Generic Interrupt Controller version 2.0 (GICv2): http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html
diff --git a/docs/plat/qemu.rst b/docs/plat/qemu.rst
index 4ebe64b..88196bc 100644
--- a/docs/plat/qemu.rst
+++ b/docs/plat/qemu.rst
@@ -10,7 +10,11 @@
 BL2 edits the Flattened Device Tree, FDT, generated by QEMU at run-time to
 add a node describing PSCI and also enable methods for the CPUs.
 
-An ARM64 defconfig v4.5 Linux kernel is known to boot, FDT doesn't need to be
+If ``ARM_LINUX_KERNEL_AS_BL33`` is set to 1 then this FDT will be passed to BL33
+via register x0, as expected by a Linux kernel. This allows a Linux kernel image
+to be booted directly as BL33 rather than using a bootloader.
+
+An ARM64 defconfig v5.5 Linux kernel is known to boot, FDT doesn't need to be
 provided as it's generated by QEMU.
 
 Current limitations:
@@ -20,7 +24,7 @@
 -  No instructions for how to load a BL32 (Secure Payload)
 
 ``QEMU_EFI.fd`` can be dowloaded from
-http://snapshots.linaro.org/components/kernel/leg-virt-tianocore-edk2-upstream/latest/QEMU-KERNEL-AARCH64/RELEASE_GCC49/QEMU_EFI.fd
+http://snapshots.linaro.org/components/kernel/leg-virt-tianocore-edk2-upstream/latest/QEMU-KERNEL-AARCH64/RELEASE_GCC5/QEMU_EFI.fd
 
 Boot binaries, except BL1, are primarily loaded via semi-hosting so all
 binaries has to reside in the same directory as QEMU is started from. This
@@ -29,7 +33,7 @@
 -  ``bl2.bin`` -> BL2
 -  ``bl31.bin`` -> BL31
 -  ``bl33.bin`` -> BL33 (``QEMU_EFI.fd``)
--  ``Image`` -> linux/Image
+-  ``Image`` -> linux/arch/arm64/boot/Image
 
 To build:
 
@@ -37,12 +41,12 @@
 
     make CROSS_COMPILE=aarch64-none-elf- PLAT=qemu
 
-To start (QEMU v2.6.0):
+To start (QEMU v4.1.0):
 
 .. code:: shell
 
     qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57  \
         -kernel Image                           \
-        -append console=ttyAMA0,38400 keep_bootcon root=/dev/vda2   \
+        -append "console=ttyAMA0,38400 keep_bootcon root=/dev/vda2"   \
         -initrd rootfs-arm64.cpio.gz -smp 2 -m 1024 -bios bl1.bin   \
         -d unimp -semihosting-config enable,target=native
diff --git a/docs/process/coding-guidelines.rst b/docs/process/coding-guidelines.rst
index cb8b892..f7d53a9 100644
--- a/docs/process/coding-guidelines.rst
+++ b/docs/process/coding-guidelines.rst
@@ -1,232 +1,126 @@
-Coding Style & Guidelines
-=========================
+Coding Guidelines
+=================
 
-The following sections contain TF coding guidelines. They are continually
-evolving and should not be considered "set in stone". Feel free to question them
-and provide feedback.
+This document provides some additional guidelines to consider when writing
+|TF-A| code. These are not intended to be strictly-enforced rules like the
+contents of the :ref:`Coding Style`.
 
-Some of the guidelines may also apply to other codebases.
+Automatic Editor Configuration
+------------------------------
 
-.. note::
-   The existing TF codebase does not necessarily comply with all the
-   below guidelines but the intent is for it to do so eventually.
-
-Checkpatch overrides
---------------------
-
-Some checkpatch warnings in the TF codebase are deliberately ignored. These
-include:
-
-- ``**WARNING: line over 80 characters**``: Although the codebase should
-  generally conform to the 80 character limit this is overly restrictive in some
-  cases.
-
-- ``**WARNING: Use of volatile is usually wrong``: see
-  `Why the “volatile” type class should not be used`_ . Although this document
-  contains some very useful information, there are several legitimate uses of
-  the volatile keyword within the TF codebase.
-
-Headers and inclusion
----------------------
-
-Header guards
-^^^^^^^^^^^^^
-
-For a header file called "some_driver.h" the style used by the Trusted Firmware
-is:
-
-.. code:: c
-
-  #ifndef SOME_DRIVER_H
-  #define SOME_DRIVER_H
-
-  <header content>
-
-  #endif /* SOME_DRIVER_H */
+Many of the rules given below (such as indentation size, use of tabs, and
+newlines) can be set automatically using the `EditorConfig`_ configuration file
+in the root of the repository: ``.editorconfig``. With a supported editor, the
+rules set out in this file can be automatically applied when you are editing
+files in the |TF-A| repository.
 
-Include statement ordering
-^^^^^^^^^^^^^^^^^^^^^^^^^^
+Several editors include built-in support for EditorConfig files, and many others
+support its functionality through plugins.
 
-All header files that are included by a source file must use the following,
-grouped ordering. This is to improve readability (by making it easier to quickly
-read through the list of headers) and maintainability.
+Use of the EditorConfig file is suggested but is not required.
 
-#. *System* includes: Header files from the standard *C* library, such as
-   ``stddef.h`` and ``string.h``.
 
-#. *Project* includes: Header files under the ``include/`` directory within TF
-   are *project* includes.
-
-#. *Platform* includes: Header files relating to a single, specific platform,
-   and which are located under the ``plat/<platform_name>`` directory within TF,
-   are *platform* includes.
-
-Within each group, ``#include`` statements must be in alphabetical order,
-taking both the file and directory names into account.
-
-Groups must be separated by a single blank line for clarity.
-
-The example below illustrates the ordering rules using some contrived header
-file names; this type of name reuse should be otherwise avoided.
-
-.. code:: c
-
-  #include <string.h>
-
-  #include <a_dir/example/a_header.h>
-  #include <a_dir/example/b_header.h>
-  #include <a_dir/test/a_header.h>
-  #include <b_dir/example/a_header.h>
-
-  #include "./a_header.h"
-
-Include statement variants
-^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Two variants of the ``#include`` directive are acceptable in the TF codebase.
-Correct use of the two styles improves readability by suggesting the location
-of the included header and reducing ambiguity in cases where generic and
-platform-specific headers share a name.
-
-For header files that are in the same directory as the source file that is
-including them, use the ``"..."`` variant.
-
-For header files that are **not** in the same directory as the source file that
-is including them, use the ``<...>`` variant.
-
-Example (bl1_fwu.c):
-
-.. code:: c
-
-  #include <assert.h>
-  #include <errno.h>
-  #include <string.h>
-
-  #include "bl1_private.h"
-
-Platform include paths
-^^^^^^^^^^^^^^^^^^^^^^
-
-Platforms are allowed to add more include paths to be passed to the compiler.
-The ``PLAT_INCLUDES`` variable is used for this purpose. This is needed in
-particular for the file ``platform_def.h``.
-
-Example:
-
-.. code:: c
-
-  PLAT_INCLUDES  += -Iinclude/plat/myplat/include
+Automatic Compliance Checking
+-----------------------------
 
-Types and typedefs
-------------------
+To assist with coding style compliance, the project Makefile contains two
+targets which both utilise the `checkpatch.pl` script that ships with the Linux
+source tree. The project also defines certain *checkpatch* options in the
+``.checkpatch.conf`` file in the top-level directory.
 
-Use of built-in *C* and *libc* data types
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. note::
+   Checkpatch errors will gate upstream merging of pull requests.
+   Checkpatch warnings will not gate merging but should be reviewed and fixed if
+   possible.
 
-The TF codebase should be kept as portable as possible, especially since both
-64-bit and 32-bit platforms are supported. To help with this, the following data
-type usage guidelines should be followed:
+To check the entire source tree, you must first download copies of
+``checkpatch.pl``, ``spelling.txt`` and ``const_structs.checkpatch`` available
+in the `Linux master tree`_ *scripts* directory, then set the ``CHECKPATCH``
+environment variable to point to ``checkpatch.pl`` (with the other 2 files in
+the same directory) and build the `checkcodebase` target:
 
-- Where possible, use the built-in *C* data types for variable storage (for
-  example, ``char``, ``int``, ``long long``, etc) instead of the standard *C99*
-  types. Most code is typically only concerned with the minimum size of the
-  data stored, which the built-in *C* types guarantee.
-
-- Avoid using the exact-size standard *C99* types in general (for example,
-  ``uint16_t``, ``uint32_t``, ``uint64_t``, etc) since they can prevent the
-  compiler from making optimizations. There are legitimate uses for them,
-  for example to represent data of a known structure. When using them in struct
-  definitions, consider how padding in the struct will work across architectures.
-  For example, extra padding may be introduced in AArch32 systems if a struct
-  member crosses a 32-bit boundary.
+.. code:: shell
 
-- Use ``int`` as the default integer type - it's likely to be the fastest on all
-  systems. Also this can be assumed to be 32-bit as a consequence of the
-  `Procedure Call Standard for the Arm Architecture`_ and the `Procedure Call
-  Standard for the Arm 64-bit Architecture`_ .
+    make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkcodebase
 
-- Avoid use of ``short`` as this may end up being slower than ``int`` in some
-  systems. If a variable must be exactly 16-bit, use ``int16_t`` or
-  ``uint16_t``.
+To just check the style on the files that differ between your local branch and
+the remote master, use:
 
-- Avoid use of ``long``. This is guaranteed to be at least 32-bit but, given
-  that `int` is 32-bit on Arm platforms, there is no use for it. For integers of
-  at least 64-bit, use ``long long``.
+.. code:: shell
 
-- Use ``char`` for storing text. Use ``uint8_t`` for storing other 8-bit data.
+    make CHECKPATCH=<path-to-linux>/linux/scripts/checkpatch.pl checkpatch
 
-- Use ``unsigned`` for integers that can never be negative (counts,
-  indices, sizes, etc). TF intends to comply with MISRA "essential type" coding
-  rules (10.X), where signed and unsigned types are considered different
-  essential types. Choosing the correct type will aid this. MISRA static
-  analysers will pick up any implicit signed/unsigned conversions that may lead
-  to unexpected behaviour.
+If you wish to check your patch against something other than the remote master,
+set the ``BASE_COMMIT`` variable to your desired branch. By default,
+``BASE_COMMIT`` is set to ``origin/master``.
 
-- For pointer types:
+Ignored Checkpatch Warnings
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-  - If an argument in a function declaration is pointing to a known type then
-    simply use a pointer to that type (for example: ``struct my_struct *``).
+Some checkpatch warnings in the TF codebase are deliberately ignored. These
+include:
 
-  - If a variable (including an argument in a function declaration) is pointing
-    to a general, memory-mapped address, an array of pointers or another
-    structure that is likely to require pointer arithmetic then use
-    ``uintptr_t``. This will reduce the amount of casting required in the code.
-    Avoid using ``unsigned long`` or ``unsigned long long`` for this purpose; it
-    may work but is less portable.
+- ``**WARNING: line over 80 characters**``: Although the codebase should
+  generally conform to the 80 character limit this is overly restrictive in some
+  cases.
 
-  - For other pointer arguments in a function declaration, use ``void *``. This
-    includes pointers to types that are abstracted away from the known API and
-    pointers to arbitrary data. This allows the calling function to pass a
-    pointer argument to the function without any explicit casting (the cast to
-    ``void *`` is implicit). The function implementation can then do the
-    appropriate casting to a specific type.
+- ``**WARNING: Use of volatile is usually wrong``: see
+  `Why the “volatile” type class should not be used`_ . Although this document
+  contains some very useful information, there are several legimate uses of the
+  volatile keyword within the TF codebase.
 
-  - Use ``ptrdiff_t`` to compare the difference between 2 pointers.
+Performance considerations
+--------------------------
 
-- Use ``size_t`` when storing the ``sizeof()`` something.
+Avoid printf and use logging macros
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-- Use ``ssize_t`` when returning the ``sizeof()`` something from a function that
-  can also return an error code; the signed type allows for a negative return
-  code in case of error. This practice should be used sparingly.
+``debug.h`` provides logging macros (for example, ``WARN`` and ``ERROR``)
+which wrap ``tf_log`` and which allow the logging call to be compiled-out
+depending on the ``make`` command. Use these macros to avoid print statements
+being compiled unconditionally into the binary.
 
-- Use ``u_register_t`` when it's important to store the contents of a register
-  in its native size (32-bit in AArch32 and 64-bit in AArch64). This is not a
-  standard *C99* type but is widely available in libc implementations,
-  including the FreeBSD version included with the TF codebase. Where possible,
-  cast the variable to a more appropriate type before interpreting the data. For
-  example, the following struct in ``ep_info.h`` could use this type to minimize
-  the storage required for the set of registers:
+Each logging macro has a numerical log level:
 
 .. code:: c
 
-    typedef struct aapcs64_params {
-            u_register_t arg0;
-            u_register_t arg1;
-            u_register_t arg2;
-            u_register_t arg3;
-            u_register_t arg4;
-            u_register_t arg5;
-            u_register_t arg6;
-            u_register_t arg7;
-    } aapcs64_params_t;
+  #define LOG_LEVEL_NONE    0
+  #define LOG_LEVEL_ERROR   10
+  #define LOG_LEVEL_NOTICE  20
+  #define LOG_LEVEL_WARNING 30
+  #define LOG_LEVEL_INFO    40
+  #define LOG_LEVEL_VERBOSE 50
 
-If some code wants to operate on ``arg0`` and knows that it represents a 32-bit
-unsigned integer on all systems, cast it to ``unsigned int``.
+By default, all logging statements with a log level ``<= LOG_LEVEL_INFO`` will
+be compiled into debug builds and all statements with a log level
+``<= LOG_LEVEL_NOTICE`` will be compiled into release builds. This can be
+overridden from the command line or by the platform makefile (although it may be
+necessary to clean the build directory first). For example, to enable
+``VERBOSE`` logging on FVP:
 
-These guidelines should be updated if additional types are needed.
+``make PLAT=fvp LOG_LEVEL=50 all``
 
-Avoid anonymous typedefs of structs/enums in headers
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Use const data where possible
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-For example, the following definition:
+For example, the following code:
 
 .. code:: c
 
-  typedef struct {
+  struct my_struct {
           int arg1;
           int arg2;
-  } my_struct_t;
+  };
 
+  void init(struct my_struct *ptr);
+
+  void main(void)
+  {
+          struct my_struct x;
+          x.arg1 = 1;
+          x.arg2 = 2;
+          init(&x);
+  }
 
 is better written as:
 
@@ -237,31 +131,18 @@
           int arg2;
   };
 
-This allows function declarations in other header files that depend on the
-struct/enum to forward declare the struct/enum instead of including the
-entire header:
-
-.. code:: c
-
-  #include <my_struct.h>
-  void my_func(my_struct_t *arg);
-
-instead of:
-
-.. code:: c
-
-  struct my_struct;
-  void my_func(struct my_struct *arg);
-
-Some TF definitions use both a struct/enum name **and** a typedef name. This
-is discouraged for new definitions as it makes it difficult for TF to comply
-with MISRA rule 8.3, which states that "All declarations of an object or
-function shall use the same names and type qualifiers".
+  void init(const struct my_struct *ptr);
 
-The Linux coding standards also discourage new typedefs and checkpatch emits
-a warning for this.
+  void main(void)
+  {
+          const struct my_struct x = { 1, 2 };
+          init(&x);
+  }
 
-Existing typedefs will be retained for compatibility.
+This allows the linker to put the data in a read-only data section instead of a
+writeable data section, which may result in a smaller and faster binary. Note
+that this may require dependent functions (``init()`` in the above example) to
+have ``const`` arguments, assuming they don't need to modify the data.
 
 Libc functions that are banned or to be used with caution
 ---------------------------------------------------------
@@ -410,14 +291,14 @@
    then emit an ``ERROR`` message and call the platform-specific function
    ``plat_error_handler()``.
 
-Cases 1 and 2 are subtly different. A platform may implement ``plat_panic_handler``
-and ``plat_error_handler`` in the same way (for example, by waiting for a secure
-watchdog to time-out or by invoking an interface on the platform's power
-controller to reset the platform). However, ``plat_error_handler`` may take
-additional action for some errors (for example, it may set a flag so the
-platform resets into a different mode). Also, ``plat_panic_handler()`` may
-implement additional debug functionality (for example, invoking a hardware
-breakpoint).
+Cases 1 and 2 are subtly different. A platform may implement
+``plat_panic_handler`` and ``plat_error_handler`` in the same way (for example,
+by waiting for a secure watchdog to time-out or by invoking an interface on the
+platform's power controller to reset the platform). However,
+``plat_error_handler`` may take additional action for some errors (for example,
+it may set a flag so the platform resets into a different mode). Also,
+``plat_panic_handler()`` may implement additional debug functionality (for
+example, invoking a hardware breakpoint).
 
 Examples of unexpected unrecoverable errors:
 
@@ -456,131 +337,115 @@
 - Secure world is waiting for a hardware response that is critical for continued
   operation.
 
-Security considerations
------------------------
-
-Part of the security of a platform is handling errors correctly, as described in
-the previous section. There are several other security considerations covered in
-this section.
-
-Do not leak secrets to the normal world
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The secure world **must not** leak secrets to the normal world, for example in
-response to an SMC.
-
-Handling Denial of Service attacks
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Use of built-in *C* and *libc* data types
+-----------------------------------------
 
-The secure world **should never** crash or become unusable due to receiving too
-many normal world requests (a *Denial of Service* or *DoS* attack). It should
-have a mechanism for throttling or ignoring normal world requests.
+The |TF-A| codebase should be kept as portable as possible, especially since
+both 64-bit and 32-bit platforms are supported. To help with this, the following
+data type usage guidelines should be followed:
 
-Performance considerations
---------------------------
+- Where possible, use the built-in *C* data types for variable storage (for
+  example, ``char``, ``int``, ``long long``, etc) instead of the standard *C99*
+  types. Most code is typically only concerned with the minimum size of the
+  data stored, which the built-in *C* types guarantee.
 
-Avoid printf and use logging macros
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+- Avoid using the exact-size standard *C99* types in general (for example,
+  ``uint16_t``, ``uint32_t``, ``uint64_t``, etc) since they can prevent the
+  compiler from making optimizations. There are legitimate uses for them,
+  for example to represent data of a known structure. When using them in struct
+  definitions, consider how padding in the struct will work across architectures.
+  For example, extra padding may be introduced in |AArch32| systems if a struct
+  member crosses a 32-bit boundary.
 
-``debug.h`` provides logging macros (for example, ``WARN`` and ``ERROR``)
-which wrap ``tf_log`` and which allow the logging call to be compiled-out
-depending on the ``make`` command. Use these macros to avoid print statements
-being compiled unconditionally into the binary.
+- Use ``int`` as the default integer type - it's likely to be the fastest on all
+  systems. Also this can be assumed to be 32-bit as a consequence of the
+  `Procedure Call Standard for the Arm Architecture`_ and the `Procedure Call
+  Standard for the Arm 64-bit Architecture`_ .
 
-Each logging macro has a numerical log level:
+- Avoid use of ``short`` as this may end up being slower than ``int`` in some
+  systems. If a variable must be exactly 16-bit, use ``int16_t`` or
+  ``uint16_t``.
 
-.. code:: c
+- Avoid use of ``long``. This is guaranteed to be at least 32-bit but, given
+  that `int` is 32-bit on Arm platforms, there is no use for it. For integers of
+  at least 64-bit, use ``long long``.
 
-  #define LOG_LEVEL_NONE    0
-  #define LOG_LEVEL_ERROR   10
-  #define LOG_LEVEL_NOTICE  20
-  #define LOG_LEVEL_WARNING 30
-  #define LOG_LEVEL_INFO    40
-  #define LOG_LEVEL_VERBOSE 50
+- Use ``char`` for storing text. Use ``uint8_t`` for storing other 8-bit data.
 
+- Use ``unsigned`` for integers that can never be negative (counts,
+  indices, sizes, etc). TF intends to comply with MISRA "essential type" coding
+  rules (10.X), where signed and unsigned types are considered different
+  essential types. Choosing the correct type will aid this. MISRA static
+  analysers will pick up any implicit signed/unsigned conversions that may lead
+  to unexpected behaviour.
 
-By default, all logging statements with a log level ``<= LOG_LEVEL_INFO`` will
-be compiled into debug builds and all statements with a log level
-``<= LOG_LEVEL_NOTICE`` will be compiled into release builds. This can be
-overridden from the command line or by the platform makefile (although it may be
-necessary to clean the build directory first). For example, to enable
-``VERBOSE`` logging on FVP:
+- For pointer types:
 
-``make PLAT=fvp LOG_LEVEL=50 all``
+  - If an argument in a function declaration is pointing to a known type then
+    simply use a pointer to that type (for example: ``struct my_struct *``).
 
-Use const data where possible
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+  - If a variable (including an argument in a function declaration) is pointing
+    to a general, memory-mapped address, an array of pointers or another
+    structure that is likely to require pointer arithmetic then use
+    ``uintptr_t``. This will reduce the amount of casting required in the code.
+    Avoid using ``unsigned long`` or ``unsigned long long`` for this purpose; it
+    may work but is less portable.
 
-For example, the following code:
+  - For other pointer arguments in a function declaration, use ``void *``. This
+    includes pointers to types that are abstracted away from the known API and
+    pointers to arbitrary data. This allows the calling function to pass a
+    pointer argument to the function without any explicit casting (the cast to
+    ``void *`` is implicit). The function implementation can then do the
+    appropriate casting to a specific type.
 
-.. code:: c
+  - Avoid pointer arithmetic generally (as this violates MISRA C 2012 rule
+    18.4) and especially on void pointers (as this is only supported via
+    language extensions and is considered non-standard). In TF-A, setting the
+    ``W`` build flag to ``W=3`` enables the *-Wpointer-arith* compiler flag and
+    this will emit warnings where pointer arithmetic is used.
 
-  struct my_struct {
-          int arg1;
-          int arg2;
-  };
+  - Use ``ptrdiff_t`` to compare the difference between 2 pointers.
 
-  void init(struct my_struct *ptr);
+- Use ``size_t`` when storing the ``sizeof()`` something.
 
-  void main(void)
-  {
-          struct my_struct x;
-          x.arg1 = 1;
-          x.arg2 = 2;
-          init(&x);
-  }
+- Use ``ssize_t`` when returning the ``sizeof()`` something from a function that
+  can also return an error code; the signed type allows for a negative return
+  code in case of error. This practice should be used sparingly.
 
-is better written as:
+- Use ``u_register_t`` when it's important to store the contents of a register
+  in its native size (32-bit in |AArch32| and 64-bit in |AArch64|). This is not a
+  standard *C99* type but is widely available in libc implementations,
+  including the FreeBSD version included with the TF codebase. Where possible,
+  cast the variable to a more appropriate type before interpreting the data. For
+  example, the following struct in ``ep_info.h`` could use this type to minimize
+  the storage required for the set of registers:
 
 .. code:: c
 
-  struct my_struct {
-          int arg1;
-          int arg2;
-  };
-
-  void init(const struct my_struct *ptr);
-
-  void main(void)
-  {
-          const struct my_struct x = { 1, 2 };
-          init(&x);
-  }
-
-This allows the linker to put the data in a read-only data section instead of a
-writeable data section, which may result in a smaller and faster binary. Note
-that this may require dependent functions (``init()`` in the above example) to
-have ``const`` arguments, assuming they don't need to modify the data.
-
-Library and driver code
------------------------
-
-TF library code (under ``lib/`` and ``include/lib``) is any code that provides a
-reusable interface to other code, potentially even to code outside of TF.
-
-In some systems drivers must conform to a specific driver framework to provide
-services to the rest of the system. TF has no driver framework and the
-distinction between a driver and library is somewhat subjective.
+    typedef struct aapcs64_params {
+            u_register_t arg0;
+            u_register_t arg1;
+            u_register_t arg2;
+            u_register_t arg3;
+            u_register_t arg4;
+            u_register_t arg5;
+            u_register_t arg6;
+            u_register_t arg7;
+    } aapcs64_params_t;
 
-A driver (under ``drivers/`` and ``include/drivers/``) is defined as code that
-interfaces with hardware via a memory mapped interface.
+If some code wants to operate on ``arg0`` and knows that it represents a 32-bit
+unsigned integer on all systems, cast it to ``unsigned int``.
 
-Some drivers (for example, the Arm CCI driver in ``include/drivers/arm/cci.h``)
-provide a general purpose API to that specific hardware. Other drivers (for
-example, the Arm PL011 console driver in ``drivers/arm/pl011/pl011_console.S``)
-provide a specific hardware implementation of a more abstract library API. In
-the latter case there may potentially be multiple drivers for the same hardware
-device.
+These guidelines should be updated if additional types are needed.
 
-Neither libraries nor drivers should depend on platform-specific code. If they
-require platform-specific data (for example, a base address) to operate then
-they should provide an initialization function that takes the platform-specific
-data as arguments.
+--------------
 
-TF common code (under ``common/`` and ``include/common/``) is code that is re-used
-by other generic (non-platform-specific) TF code. It is effectively internal
-library code.
+*Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.*
 
+.. _`Linux master tree`: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/
+.. _`Procedure Call Standard for the Arm Architecture`: https://developer.arm.com/docs/ihi0042/latest/
+.. _`Procedure Call Standard for the Arm 64-bit Architecture`: https://developer.arm.com/docs/ihi0055/latest/
+.. _`EditorConfig`: http://editorconfig.org/
 .. _`Why the “volatile” type class should not be used`: https://www.kernel.org/doc/html/latest/process/volatile-considered-harmful.html
-.. _`Procedure Call Standard for the Arm Architecture`: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0042f/IHI0042F_aapcs.pdf
-.. _`Procedure Call Standard for the Arm 64-bit Architecture`: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf
+.. _`MISRA C:2012 Guidelines`: https://www.misra.org.uk/Activities/MISRAC/tabid/160/Default.aspx
+.. _`a spreadsheet`: https://developer.trustedfirmware.org/file/download/lamajxif3w7c4mpjeoo5/PHID-FILE-fp7c7acszn6vliqomyhn/MISRA-and-TF-Analysis-v1.3.ods
diff --git a/docs/process/coding-style.rst b/docs/process/coding-style.rst
new file mode 100644
index 0000000..fd1984d
--- /dev/null
+++ b/docs/process/coding-style.rst
@@ -0,0 +1,468 @@
+Coding Style
+============
+
+The following sections outline the |TF-A| coding style for *C* code. The style
+is based on the `Linux kernel coding style`_, with a few modifications.
+
+The style should not be considered *set in stone*. Feel free to provide feedback
+and suggestions.
+
+.. note::
+   You will almost certainly find code in the |TF-A| repository that does not
+   follow the style. The intent is for all code to do so eventually.
+
+File Encoding
+-------------
+
+The source code must use the **UTF-8** character encoding. Comments and
+documentation may use non-ASCII characters when required (e.g. Greek letters
+used for units) but code itself is still limited to ASCII characters.
+
+Newlines must be in **Unix** style, which means that only the Line Feed (``LF``)
+character is used to break a line and reset to the first column.
+
+Language
+--------
+
+The primary language for comments and naming must be International English. In
+cases where there is a conflict between the American English and British English
+spellings of a word, the American English spelling is used.
+
+Exceptions are made when referring directly to something that does not use
+international style, such as the name of a company. In these cases the existing
+name should be used as-is.
+
+C Language Standard
+-------------------
+
+The C language mode used for TF-A is *GNU99*. This is the "GNU dialect of ISO
+C99", which implies the *ISO C99* standard with GNU extensions.
+
+Both GCC and Clang compiler toolchains have support for *GNU99* mode, though
+Clang does lack support for a small number of GNU extensions. These
+missing extensions are rarely used, however, and should not pose a problem.
+
+MISRA Compliance
+----------------
+
+TF-A attempts to comply with the `MISRA C:2012 Guidelines`_. Coverity
+Static Analysis is used to regularly generate a report of current MISRA defects
+and to prevent the addition of new ones.
+
+It is not possible for the project to follow all MISRA guidelines. We maintain
+`a spreadsheet`_ that lists all rules and directives and whether we aim to
+comply with them or not. A rationale is given for each deviation.
+
+.. note::
+   Enforcing a rule does not mean that the codebase is free of defects
+   of that rule, only that they would ideally be removed.
+
+.. note::
+   Third-party libraries are not considered in our MISRA analysis and we do not
+   intend to modify them to make them MISRA compliant.
+
+Indentation
+-----------
+
+Use **tabs** for indentation. The use of spaces for indentation is forbidden
+except in the case where a term is being indented to a boundary that cannot be
+achieved using tabs alone.
+
+Tab spacing should be set to **8 characters**.
+
+Trailing whitespace is not allowed and must be trimmed.
+
+Spacing
+-------
+
+Single spacing should be used around most operators, including:
+
+- Arithmetic operators (``+``, ``-``, ``/``, ``*``)
+- Assignment operators (``=``, ``+=``, etc)
+- Boolean operators (``&&``, ``||``)
+- Comparison operators (``<``, ``>``, ``==``, etc)
+
+A space should also be used to separate parentheses and braces when they are not
+already separated by a newline, such as for the ``if`` statement in the
+following example:
+
+.. code:: c
+
+  int function_foo(bool bar)
+  {
+      if (bar) {
+          function_baz();
+      }
+  }
+
+Note that there is no space between the name of a function and the following
+parentheses.
+
+Control statements (``if``, ``for``, ``switch``, ``while``, etc) must be
+separated from the following open paranthesis by a single space. The previous
+example illustrates this for an ``if`` statement.
+
+Line Length
+-----------
+
+Line length *should* be at most **80 characters**. This limit does not include
+non-printing characters such as the line feed.
+
+This rule is a *should*, not a must, and it is acceptable to exceed the limit
+**slightly** where the readability of the code would otherwise be significantly
+reduced. Use your judgement in these cases.
+
+Blank Lines
+-----------
+
+Functions are usually separated by a single blank line. In certain cases it is
+acceptable to use additional blank lines for clarity, if required.
+
+The file must end with a single newline character. Many editors have the option
+to insert this automatically and to trim multiple blank lines at the end of the
+file.
+
+Braces
+------
+
+Opening Brace Placement
+^^^^^^^^^^^^^^^^^^^^^^^
+
+Braces follow the **Kernighan and Ritchie (K&R)** style, where the opening brace
+is **not** placed on a new line.
+
+Example for a ``while`` loop:
+
+.. code:: c
+
+  while (condition) {
+      foo();
+      bar();
+  }
+
+This style applies to all blocks except for functions which, following the Linux
+style, **do** place the opening brace on a new line.
+
+Example for a function:
+
+.. code:: c
+
+  int my_function(void)
+  {
+      int a;
+
+      a = 1;
+      return a;
+  }
+
+Conditional Statement Bodies
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Where conditional statements (such as ``if``, ``for``, ``while`` and ``do``) are
+used, braces must be placed around the statements that form the body of the
+conditional. This is the case regardless of the number of statements in the
+body.
+
+.. note::
+  This is a notable departure from the Linux coding style that has been
+  adopted to follow MISRA guidelines more closely and to help prevent errors.
+
+For example, use the following style:
+
+.. code:: c
+
+  if (condition) {
+      foo++;
+  }
+
+instead of omitting the optional braces around a single statement:
+
+.. code:: c
+
+  /* This is violating MISRA C 2012: Rule 15.6 */
+  if (condition)
+      foo++;
+
+The reason for this is to prevent accidental changes to control flow when
+modifying the body of the conditional. For example, at a quick glance it is easy
+to think that the value of ``bar`` is only incremented if ``condition``
+evaluates to ``true`` but this is not the case - ``bar`` will always be
+incremented regardless of the condition evaluation. If the developer forgets to
+add braces around the conditional body when adding the ``bar++;`` statement then
+the program execution will not proceed as intended.
+
+.. code:: c
+
+  /* This is violating MISRA C 2012: Rule 15.6 */
+  if (condition)
+      foo++;
+      bar++;
+
+Naming
+------
+
+Functions
+^^^^^^^^^
+
+Use lowercase for function names, separating multiple words with an underscore
+character (``_``). This is sometimes referred to as *Snake Case*. An example is
+given below:
+
+.. code:: c
+
+  void bl2_arch_setup(void)
+  {
+      ...
+  }
+
+Local Variables and Parameters
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Local variables and function parameters use the same format as function names:
+lowercase with underscore separation between multiple words. An example is
+given below:
+
+.. code:: c
+
+  static void set_scr_el3_from_rm(uint32_t type,
+                                  uint32_t interrupt_type_flags,
+                                  uint32_t security_state)
+  {
+      uint32_t flag, bit_pos;
+
+      ...
+
+  }
+
+Preprocessor Macros
+^^^^^^^^^^^^^^^^^^^
+
+Identifiers that are defined using preprocessor macros are written in all
+uppercase text.
+
+.. code:: c
+
+  #define BUFFER_SIZE_BYTES 64
+
+Function Attributes
+-------------------
+
+Place any function attributes after the function type and before the function
+name.
+
+.. code:: c
+
+   void __init plat_arm_interconnect_init(void);
+
+Alignment
+---------
+
+Alignment should be performed primarily with tabs, adding spaces if required to
+achieve a granularity that is smaller than the tab size. For example, with a tab
+size of eight columns it would be necessary to use one tab character and two
+spaces to indent text by ten columns.
+
+Switch Statement Alignment
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+When using ``switch`` statements, align each ``case`` statement with the
+``switch`` so that they are in the same column.
+
+.. code:: c
+
+  switch (condition) {
+  case A:
+      foo();
+  case B:
+      bar();
+  default:
+      baz();
+  }
+
+Pointer Alignment
+^^^^^^^^^^^^^^^^^
+
+The reference and dereference operators (ampersand and *pointer star*) must be
+aligned with the name of the object on which they are operating, as opposed to
+the type of the object.
+
+.. code:: c
+
+  uint8_t *foo;
+
+  foo = &bar;
+
+
+Comments
+--------
+
+The general rule for comments is that the double-slash style of comment (``//``)
+is not allowed. Examples of the allowed comment formats are shown below:
+
+.. code:: c
+
+  /*
+   * This example illustrates the first allowed style for multi-line comments.
+   *
+   * Blank lines within multi-lines are allowed when they add clarity or when
+   * they separate multiple contexts.
+   *
+   */
+
+.. code:: c
+
+  /**************************************************************************
+   * This is the second allowed style for multi-line comments.
+   *
+   * In this style, the first and last lines use asterisks that run the full
+   * width of the comment at its widest point.
+   *
+   * This style can be used for additional emphasis.
+   *
+   *************************************************************************/
+
+.. code:: c
+
+  /* Single line comments can use this format */
+
+.. code:: c
+
+  /***************************************************************************
+   * This alternative single-line comment style can also be used for emphasis.
+   **************************************************************************/
+
+Headers and inclusion
+---------------------
+
+Header guards
+^^^^^^^^^^^^^
+
+For a header file called "some_driver.h" the style used by |TF-A| is:
+
+.. code:: c
+
+  #ifndef SOME_DRIVER_H
+  #define SOME_DRIVER_H
+
+  <header content>
+
+  #endif /* SOME_DRIVER_H */
+
+Include statement ordering
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+All header files that are included by a source file must use the following,
+grouped ordering. This is to improve readability (by making it easier to quickly
+read through the list of headers) and maintainability.
+
+#. *System* includes: Header files from the standard *C* library, such as
+   ``stddef.h`` and ``string.h``.
+
+#. *Project* includes: Header files under the ``include/`` directory within
+   |TF-A| are *project* includes.
+
+#. *Platform* includes: Header files relating to a single, specific platform,
+   and which are located under the ``plat/<platform_name>`` directory within
+   |TF-A|, are *platform* includes.
+
+Within each group, ``#include`` statements must be in alphabetical order,
+taking both the file and directory names into account.
+
+Groups must be separated by a single blank line for clarity.
+
+The example below illustrates the ordering rules using some contrived header
+file names; this type of name reuse should be otherwise avoided.
+
+.. code:: c
+
+  #include <string.h>
+
+  #include <a_dir/example/a_header.h>
+  #include <a_dir/example/b_header.h>
+  #include <a_dir/test/a_header.h>
+  #include <b_dir/example/a_header.h>
+
+  #include "a_header.h"
+
+Include statement variants
+^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+Two variants of the ``#include`` directive are acceptable in the |TF-A|
+codebase. Correct use of the two styles improves readability by suggesting the
+location of the included header and reducing ambiguity in cases where generic
+and platform-specific headers share a name.
+
+For header files that are in the same directory as the source file that is
+including them, use the ``"..."`` variant.
+
+For header files that are **not** in the same directory as the source file that
+is including them, use the ``<...>`` variant.
+
+Example (bl1_fwu.c):
+
+.. code:: c
+
+  #include <assert.h>
+  #include <errno.h>
+  #include <string.h>
+
+  #include "bl1_private.h"
+
+Typedefs
+--------
+
+Avoid anonymous typedefs of structs/enums in headers
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+For example, the following definition:
+
+.. code:: c
+
+  typedef struct {
+          int arg1;
+          int arg2;
+  } my_struct_t;
+
+
+is better written as:
+
+.. code:: c
+
+  struct my_struct {
+          int arg1;
+          int arg2;
+  };
+
+This allows function declarations in other header files that depend on the
+struct/enum to forward declare the struct/enum instead of including the
+entire header:
+
+.. code:: c
+
+  struct my_struct;
+  void my_func(struct my_struct *arg);
+
+instead of:
+
+.. code:: c
+
+  #include <my_struct.h>
+  void my_func(my_struct_t *arg);
+
+Some TF definitions use both a struct/enum name **and** a typedef name. This
+is discouraged for new definitions as it makes it difficult for TF to comply
+with MISRA rule 8.3, which states that "All declarations of an object or
+function shall use the same names and type qualifiers".
+
+The Linux coding standards also discourage new typedefs and checkpatch emits
+a warning for this.
+
+Existing typedefs will be retained for compatibility.
+
+--------------
+
+*Copyright (c) 2020, Arm Limited. All rights reserved.*
+
+.. _`Linux kernel coding style`: https://www.kernel.org/doc/html/latest/process/coding-style.html
+.. _`MISRA C:2012 Guidelines`: https://www.misra.org.uk/Activities/MISRAC/tabid/160/Default.aspx
+.. _`a spreadsheet`: https://developer.trustedfirmware.org/file/download/lamajxif3w7c4mpjeoo5/PHID-FILE-fp7c7acszn6vliqomyhn/MISRA-and-TF-Analysis-v1.3.ods
diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst
index f569fcb..68c494b 100644
--- a/docs/process/contributing.rst
+++ b/docs/process/contributing.rst
@@ -23,7 +23,7 @@
 
 -  Make commits of logical units. See these general `Git guidelines`_ for
    contributing to a project.
--  Follow the :ref:`Coding Style & Guidelines`.
+-  Follow the :ref:`Coding Style` and :ref:`Coding Guidelines`.
 
    -  Use the checkpatch.pl script provided with the Linux source tree. A
       Makefile target is provided for convenience.
@@ -128,7 +128,7 @@
 
 --------------
 
-*Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
 
 .. _developer.trustedfirmware.org: https://developer.trustedfirmware.org
 .. _issue: https://developer.trustedfirmware.org/project/board/1/
diff --git a/docs/process/index.rst b/docs/process/index.rst
index 9c12de8..1cb5354 100644
--- a/docs/process/index.rst
+++ b/docs/process/index.rst
@@ -8,6 +8,7 @@
 
    security
    platform-compatibility-policy
+   coding-style
    coding-guidelines
    contributing
    faq
diff --git a/docs/process/security-hardening.rst b/docs/process/security-hardening.rst
index a18a792..43a5721 100644
--- a/docs/process/security-hardening.rst
+++ b/docs/process/security-hardening.rst
@@ -1,10 +1,30 @@
-Security hardening
-==================
+Secure Development Guidelines
+=============================
 
 This page contains guidance on what to check for additional security measures,
 including build options that can be modified to improve security or catch issues
 early in development.
 
+Security considerations
+-----------------------
+
+Part of the security of a platform is handling errors correctly, as described in
+the previous section. There are several other security considerations covered in
+this section.
+
+Do not leak secrets to the normal world
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The secure world **must not** leak secrets to the normal world, for example in
+response to an SMC.
+
+Handling Denial of Service attacks
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The secure world **should never** crash or become unusable due to receiving too
+many normal world requests (a *Denial of Service* or *DoS* attack). It should
+have a mechanism for throttling or ignoring normal world requests.
+
 Build options
 -------------
 
@@ -53,4 +73,4 @@
 
 --------------
 
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
diff --git a/drivers/arm/ccn/ccn.c b/drivers/arm/ccn/ccn.c
index d0c5abc..5b13250 100644
--- a/drivers/arm/ccn/ccn.c
+++ b/drivers/arm/ccn/ccn.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-#include <errno.h>
 #include <stdbool.h>
 
 #include <arch.h>
diff --git a/drivers/arm/gic/v2/gicv2_helpers.c b/drivers/arm/gic/v2/gicv2_helpers.c
index 6739a78..751316c 100644
--- a/drivers/arm/gic/v2/gicv2_helpers.c
+++ b/drivers/arm/gic/v2/gicv2_helpers.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +7,6 @@
 #include <assert.h>
 
 #include <arch.h>
-#include <arch_helpers.h>
 #include <common/debug.h>
 #include <common/interrupt_props.h>
 #include <drivers/arm/gic_common.h>
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index fb49a57..a672b18 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -235,7 +235,7 @@
 void gicv3_cpuif_enable(unsigned int proc_num)
 {
 	uintptr_t gicr_base;
-	unsigned int scr_el3;
+	u_register_t scr_el3;
 	unsigned int icc_sre_el3;
 
 	assert(gicv3_driver_data != NULL);
@@ -258,7 +258,7 @@
 	icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT);
 	write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3);
 
-	scr_el3 = (uint32_t) read_scr_el3();
+	scr_el3 = read_scr_el3();
 
 	/*
 	 * Switch to NS state to write Non secure ICC_SRE_EL1 and
diff --git a/drivers/auth/crypto_mod.c b/drivers/auth/crypto_mod.c
index 5e5ac2b..110c504 100644
--- a/drivers/auth/crypto_mod.c
+++ b/drivers/auth/crypto_mod.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -103,3 +103,24 @@
 	return crypto_lib_desc.verify_hash(data_ptr, data_len,
 					   digest_info_ptr, digest_info_len);
 }
+
+#if MEASURED_BOOT
+/*
+ * Calculate a hash
+ *
+ * Parameters:
+ *
+ *   alg: message digest algorithm
+ *   data_ptr, data_len: data to be hashed
+ *   output: resulting hash
+ */
+int crypto_mod_calc_hash(unsigned int alg, void *data_ptr,
+			 unsigned int data_len, unsigned char *output)
+{
+	assert(data_ptr != NULL);
+	assert(data_len != 0);
+	assert(output != NULL);
+
+	return crypto_lib_desc.calc_hash(alg, data_ptr, data_len, output);
+}
+#endif	/* MEASURED_BOOT */
diff --git a/drivers/auth/img_parser_mod.c b/drivers/auth/img_parser_mod.c
index c4688f8..535695d 100644
--- a/drivers/auth/img_parser_mod.c
+++ b/drivers/auth/img_parser_mod.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-#include <errno.h>
 #include <limits.h>
 #include <stdint.h>
 #include <string.h>
diff --git a/drivers/auth/mbedtls/mbedtls_crypto.c b/drivers/auth/mbedtls/mbedtls_crypto.c
index 33420fb..04fbc64 100644
--- a/drivers/auth/mbedtls/mbedtls_crypto.c
+++ b/drivers/auth/mbedtls/mbedtls_crypto.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -205,7 +205,32 @@
 	return CRYPTO_SUCCESS;
 }
 
+#if MEASURED_BOOT
+/*
+ * Calculate a hash
+ *
+ * output points to the computed hash
+ */
+int calc_hash(unsigned int alg, void *data_ptr,
+	      unsigned int data_len, unsigned char *output)
+{
+	const mbedtls_md_info_t *md_info;
+
+	md_info = mbedtls_md_info_from_type((mbedtls_md_type_t)alg);
+	if (md_info == NULL) {
+		return CRYPTO_ERR_HASH;
+	}
+
+	/* Calculate the hash of the data */
+	return mbedtls_md(md_info, data_ptr, data_len, output);
+}
+#endif /* MEASURED_BOOT */
+
 /*
  * Register crypto library descriptor
  */
+#if MEASURED_BOOT
+REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, calc_hash);
+#else
 REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash);
+#endif /* MEASURED_BOOT */
diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
index 8bb1bab..935bf77 100644
--- a/include/bl31/interrupt_mgmt.h
+++ b/include/bl31/interrupt_mgmt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -134,7 +134,7 @@
 /*******************************************************************************
  * Function & variable prototypes
  ******************************************************************************/
-uint32_t get_scr_el3_from_routing_model(uint32_t security_state);
+u_register_t get_scr_el3_from_routing_model(uint32_t security_state);
 int32_t set_routing_model(uint32_t type, uint32_t flags);
 int32_t register_interrupt_type_handler(uint32_t type,
 					interrupt_type_handler_t handler,
diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h
index 79d001d..f467958 100644
--- a/include/common/fdt_wrappers.h
+++ b/include/common/fdt_wrappers.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -20,5 +20,9 @@
 		char *str, size_t size);
 int fdtw_write_inplace_cells(void *dtb, int node, const char *prop,
 		unsigned int cells, void *value);
+int fdtw_read_bytes(const void *dtb, int node, const char *prop,
+		unsigned int length, void *value);
+int fdtw_write_inplace_bytes(void *dtb, int node, const char *prop,
+		unsigned int length, const void *data);
 
 #endif /* FDT_WRAPPERS_H */
diff --git a/include/drivers/auth/crypto_mod.h b/include/drivers/auth/crypto_mod.h
index 3a42105..f211035 100644
--- a/include/drivers/auth/crypto_mod.h
+++ b/include/drivers/auth/crypto_mod.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -37,6 +37,13 @@
 	/* Verify a hash. Return one of the 'enum crypto_ret_value' options */
 	int (*verify_hash)(void *data_ptr, unsigned int data_len,
 			   void *digest_info_ptr, unsigned int digest_info_len);
+
+#if MEASURED_BOOT
+	/* Calculate a hash. Return hash value */
+	int (*calc_hash)(unsigned int alg, void *data_ptr,
+			 unsigned int data_len, unsigned char *output);
+#endif /* MEASURED_BOOT */
+
 } crypto_lib_desc_t;
 
 /* Public functions */
@@ -48,7 +55,21 @@
 int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len,
 			   void *digest_info_ptr, unsigned int digest_info_len);
 
+#if MEASURED_BOOT
+int crypto_mod_calc_hash(unsigned int alg, void *data_ptr,
+			 unsigned int data_len, unsigned char *output);
+
 /* Macro to register a cryptographic library */
+#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash, \
+							     _calc_hash) \
+	const crypto_lib_desc_t crypto_lib_desc = { \
+		.name = _name, \
+		.init = _init, \
+		.verify_signature = _verify_signature, \
+		.verify_hash = _verify_hash, \
+		.calc_hash = _calc_hash \
+	}
+#else
 #define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash) \
 	const crypto_lib_desc_t crypto_lib_desc = { \
 		.name = _name, \
@@ -56,6 +77,7 @@
 		.verify_signature = _verify_signature, \
 		.verify_hash = _verify_hash \
 	}
+#endif	/* MEASURED_BOOT */
 
 extern const crypto_lib_desc_t crypto_lib_desc;
 
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index 7c996d1..17955e3 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -45,7 +45,7 @@
 			  uint32_t bit_pos,
 			  uint32_t value);
 void cm_set_next_eret_context(uint32_t security_state);
-uint32_t cm_get_scr_el3(uint32_t security_state);
+u_register_t cm_get_scr_el3(uint32_t security_state);
 
 /* Inline definitions */
 
diff --git a/include/lib/semihosting.h b/include/lib/semihosting.h
index 006c7b7..24b030c 100644
--- a/include/lib/semihosting.h
+++ b/include/lib/semihosting.h
@@ -23,6 +23,7 @@
 #define SEMIHOSTING_SYS_REMOVE          0x0E
 #define SEMIHOSTING_SYS_SYSTEM          0x12
 #define SEMIHOSTING_SYS_ERRNO           0x13
+#define SEMIHOSTING_SYS_EXIT            0x18
 
 #define FOPEN_MODE_R			0x0
 #define FOPEN_MODE_RB			0x1
@@ -54,5 +55,6 @@
 void semihosting_write_char(char character);
 void semihosting_write_string(char *string);
 char semihosting_read_char(void);
+void semihosting_exit(uint32_t reason, uint32_t subcode);
 
 #endif /* SEMIHOSTING_H */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index b419c85..5bd53f3 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -395,13 +395,21 @@
 /*******************************************************************************
  * BL31 specific defines.
  ******************************************************************************/
-#if ARM_BL31_IN_DRAM
+#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION
 /*
  * Put BL31 at the bottom of TZC secured DRAM
  */
 #define BL31_BASE			ARM_AP_TZC_DRAM1_BASE
 #define BL31_LIMIT			(ARM_AP_TZC_DRAM1_BASE +	\
 						PLAT_ARM_MAX_BL31_SIZE)
+/*
+ * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM.
+ * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten.
+ */
+#if SEPARATE_NOBITS_REGION
+#define BL31_NOBITS_BASE		BL2_BASE
+#define BL31_NOBITS_LIMIT		BL2_LIMIT
+#endif /* SEPARATE_NOBITS_REGION */
 #elif (RESET_TO_BL31)
 /* Ensure Position Independent support (PIE) is enabled for this config.*/
 # if !ENABLE_PIE
diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c
index f43b217..5d1e3c5 100644
--- a/lib/cpus/errata_report.c
+++ b/lib/cpus/errata_report.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,7 +14,6 @@
 #include <lib/cpus/errata_report.h>
 #include <lib/el3_runtime/cpu_data.h>
 #include <lib/spinlock.h>
-#include <lib/utils.h>
 
 #ifdef IMAGE_BL1
 # define BL_STRING	"BL1"
diff --git a/lib/debugfs/devfip.c b/lib/debugfs/devfip.c
index 5581b21..fc14e70 100644
--- a/lib/debugfs/devfip.c
+++ b/lib/debugfs/devfip.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -103,10 +103,6 @@
 		return -1;
 	}
 
-	if ((entry->size > LONG_MAX) || (entry->offset_address > LONG_MAX)) {
-		return -1;
-	}
-
 	if (entry->size == 0) {
 		return 0;
 	}
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 73d1e35..2443001 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,8 +17,6 @@
 #include <lib/el3_runtime/context_mgmt.h>
 #include <lib/extensions/amu.h>
 #include <lib/utils.h>
-#include <plat/common/platform.h>
-#include <smccc_helpers.h>
 
 /*******************************************************************************
  * Context management library initialisation routine. This library is used by
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index b7908ad..546e39e 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,8 +23,6 @@
 #include <lib/extensions/spe.h>
 #include <lib/extensions/sve.h>
 #include <lib/utils.h>
-#include <plat/common/platform.h>
-#include <smccc_helpers.h>
 
 
 /*******************************************************************************
@@ -66,7 +64,7 @@
 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
 {
 	unsigned int security_state;
-	uint32_t scr_el3;
+	u_register_t scr_el3;
 	el3_state_t *state;
 	gp_regs_t *gp_regs;
 	u_register_t sctlr_elx, actlr_elx;
@@ -87,7 +85,7 @@
 	 * the required value depending on the state of the SPSR_EL3 and the
 	 * Security state and entrypoint attributes of the next EL.
 	 */
-	scr_el3 = (uint32_t)read_scr();
+	scr_el3 = read_scr();
 	scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
 			SCR_ST_BIT | SCR_HCE_BIT);
 	/*
@@ -326,7 +324,7 @@
  ******************************************************************************/
 void cm_prepare_el3_exit(uint32_t security_state)
 {
-	uint32_t sctlr_elx, scr_el3, mdcr_el2;
+	u_register_t sctlr_elx, scr_el3, mdcr_el2;
 	cpu_context_t *ctx = cm_get_context(security_state);
 	bool el2_unused = false;
 	uint64_t hcr_el2 = 0U;
@@ -334,11 +332,11 @@
 	assert(ctx != NULL);
 
 	if (security_state == NON_SECURE) {
-		scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx),
+		scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
 						 CTX_SCR_EL3);
 		if ((scr_el3 & SCR_HCE_BIT) != 0U) {
 			/* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
-			sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx),
+			sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx),
 							   CTX_SCTLR_EL1);
 			sctlr_elx &= SCTLR_EE_BIT;
 			sctlr_elx |= SCTLR_EL2_RES1;
@@ -618,7 +616,7 @@
 {
 	cpu_context_t *ctx;
 	el3_state_t *state;
-	uint32_t scr_el3;
+	u_register_t scr_el3;
 
 	ctx = cm_get_context(security_state);
 	assert(ctx != NULL);
@@ -634,9 +632,9 @@
 	 * and set it to its new value.
 	 */
 	state = get_el3state_ctx(ctx);
-	scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
+	scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
 	scr_el3 &= ~(1U << bit_pos);
-	scr_el3 |= value << bit_pos;
+	scr_el3 |= (u_register_t)value << bit_pos;
 	write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
 }
 
@@ -644,7 +642,7 @@
  * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
  * given security state.
  ******************************************************************************/
-uint32_t cm_get_scr_el3(uint32_t security_state)
+u_register_t cm_get_scr_el3(uint32_t security_state)
 {
 	cpu_context_t *ctx;
 	el3_state_t *state;
@@ -654,7 +652,7 @@
 
 	/* Populate EL3 state so that ERET jumps to the correct entry */
 	state = get_el3state_ctx(ctx);
-	return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
+	return read_ctx_reg(state, CTX_SCR_EL3);
 }
 
 /*******************************************************************************
diff --git a/lib/el3_runtime/aarch64/cpu_data.S b/lib/el3_runtime/aarch64/cpu_data.S
index 2edf225..2392d6b 100644
--- a/lib/el3_runtime/aarch64/cpu_data.S
+++ b/lib/el3_runtime/aarch64/cpu_data.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -41,7 +41,8 @@
 func _cpu_data_by_index
 	mov_imm	x1, CPU_DATA_SIZE
 	mul	x0, x0, x1
-	adr	x1, percpu_data
+	adrp	x1, percpu_data
+	add	x1, x1, :lo12:percpu_data
 	add	x0, x0, x1
 	ret
 endfunc _cpu_data_by_index
diff --git a/lib/locks/bakery/bakery_lock_coherent.c b/lib/locks/bakery/bakery_lock_coherent.c
index 1634e3a..748eedd 100644
--- a/lib/locks/bakery/bakery_lock_coherent.c
+++ b/lib/locks/bakery/bakery_lock_coherent.c
@@ -137,10 +137,11 @@
 	}
 
 	/*
-	 * Lock acquired. Ensure that any reads from a shared resource in the
-	 * critical section read values after the lock is acquired.
+	 * Lock acquired. Ensure that any reads and writes from a shared
+	 * resource in the critical section read/write values after the lock is
+	 * acquired.
 	 */
-	dmbld();
+	dmbish();
 }
 
 
@@ -154,11 +155,14 @@
 
 	/*
 	 * Ensure that other observers see any stores in the critical section
-	 * before releasing the lock. Release the lock by resetting ticket.
-	 * Then signal other waiting contenders.
+	 * before releasing the lock. Also ensure all loads in the critical
+	 * section are complete before releasing the lock. Release the lock by
+	 * resetting ticket. Then signal other waiting contenders.
 	 */
-	dmbst();
+	dmbish();
 	bakery->lock_data[me] = 0U;
+
+	/* Required to ensure ordering of the following sev */
 	dsb();
 	sev();
 }
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index f906f51..caced8f 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -219,10 +219,11 @@
 	}
 
 	/*
-	 * Lock acquired. Ensure that any reads from a shared resource in the
-	 * critical section read values after the lock is acquired.
+	 * Lock acquired. Ensure that any reads and writes from a shared
+	 * resource in the critical section read/write values after the lock is
+	 * acquired.
 	 */
-	dmbld();
+	dmbish();
 }
 
 void bakery_lock_release(bakery_lock_t *lock)
@@ -240,11 +241,14 @@
 
 	/*
 	 * Ensure that other observers see any stores in the critical section
-	 * before releasing the lock. Release the lock by resetting ticket.
-	 * Then signal other waiting contenders.
+	 * before releasing the lock. Also ensure all loads in the critical
+	 * section are complete before releasing the lock. Release the lock by
+	 * resetting ticket. Then signal other waiting contenders.
 	 */
-	dmbst();
+	dmbish();
 	my_bakery_info->lock_data = 0U;
 	write_cache_op((uintptr_t)my_bakery_info, is_cached);
+
+	/* This sev is ordered by the dsbish in write_cahce_op */
 	sev();
 }
diff --git a/lib/optee/optee_utils.c b/lib/optee/optee_utils.c
index 2a40793..0ad1082 100644
--- a/lib/optee/optee_utils.c
+++ b/lib/optee/optee_utils.c
@@ -1,15 +1,12 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-#include <errno.h>
 
-#include <arch_helpers.h>
 #include <common/debug.h>
-#include <common/desc_image_load.h>
 #include <lib/optee_utils.h>
 
 /*
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index ea1a01d..5ab15c6 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -775,7 +775,7 @@
 	 * suspend.
 	 */
 	if (psci_get_aff_info_state() == AFF_STATE_OFF) {
-		ERROR("Unexpected affinity info state");
+		ERROR("Unexpected affinity info state.\n");
 		panic();
 	}
 
diff --git a/lib/romlib/jmptbl.i b/lib/romlib/jmptbl.i
index a7280d0..33710f5 100644
--- a/lib/romlib/jmptbl.i
+++ b/lib/romlib/jmptbl.i
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -17,6 +17,7 @@
 fdt	fdt_setprop_inplace
 fdt	fdt_check_header
 fdt	fdt_node_offset_by_compatible
+fdt     fdt_setprop_inplace_namelen_partial
 mbedtls	mbedtls_asn1_get_alg
 mbedtls	mbedtls_asn1_get_alg_null
 mbedtls	mbedtls_asn1_get_bitstring_null
diff --git a/lib/semihosting/semihosting.c b/lib/semihosting/semihosting.c
index 051dd00..60fc52a 100644
--- a/lib/semihosting/semihosting.c
+++ b/lib/semihosting/semihosting.c
@@ -15,7 +15,7 @@
 #endif
 
 long semihosting_call(unsigned long operation,
-			void *system_block_address);
+			uintptr_t system_block_address);
 
 typedef struct {
 	const char *file_name;
@@ -53,7 +53,7 @@
 	open_block.name_length = strlen(file_name);
 
 	return semihosting_call(SEMIHOSTING_SYS_OPEN,
-				(void *) &open_block);
+				(uintptr_t) &open_block);
 }
 
 long semihosting_file_seek(long file_handle, ssize_t offset)
@@ -65,7 +65,7 @@
 	seek_block.location = offset;
 
 	result = semihosting_call(SEMIHOSTING_SYS_SEEK,
-				  (void *) &seek_block);
+				  (uintptr_t) &seek_block);
 
 	if (result)
 		result = semihosting_call(SEMIHOSTING_SYS_ERRNO, 0);
@@ -86,7 +86,7 @@
 	read_block.length = *length;
 
 	result = semihosting_call(SEMIHOSTING_SYS_READ,
-				  (void *) &read_block);
+				  (uintptr_t) &read_block);
 
 	if (result == *length) {
 		return -EINVAL;
@@ -112,7 +112,7 @@
 	write_block.length = *length;
 
 	result = semihosting_call(SEMIHOSTING_SYS_WRITE,
-				   (void *) &write_block);
+				   (uintptr_t) &write_block);
 
 	*length = result;
 
@@ -122,28 +122,28 @@
 long semihosting_file_close(long file_handle)
 {
 	return semihosting_call(SEMIHOSTING_SYS_CLOSE,
-				(void *) &file_handle);
+				(uintptr_t) &file_handle);
 }
 
 long semihosting_file_length(long file_handle)
 {
 	return semihosting_call(SEMIHOSTING_SYS_FLEN,
-				(void *) &file_handle);
+				(uintptr_t) &file_handle);
 }
 
 char semihosting_read_char(void)
 {
-	return semihosting_call(SEMIHOSTING_SYS_READC, NULL);
+	return semihosting_call(SEMIHOSTING_SYS_READC, 0);
 }
 
 void semihosting_write_char(char character)
 {
-	semihosting_call(SEMIHOSTING_SYS_WRITEC, (void *) &character);
+	semihosting_call(SEMIHOSTING_SYS_WRITEC, (uintptr_t) &character);
 }
 
 void semihosting_write_string(char *string)
 {
-	semihosting_call(SEMIHOSTING_SYS_WRITE0, (void *) string);
+	semihosting_call(SEMIHOSTING_SYS_WRITE0, (uintptr_t) string);
 }
 
 long semihosting_system(char *command_line)
@@ -154,7 +154,7 @@
 	system_block.command_length = strlen(command_line);
 
 	return semihosting_call(SEMIHOSTING_SYS_SYSTEM,
-				(void *) &system_block);
+				(uintptr_t) &system_block);
 }
 
 long semihosting_get_flen(const char *file_name)
@@ -216,3 +216,15 @@
 	semihosting_file_close(file_handle);
 	return ret;
 }
+
+void semihosting_exit(uint32_t reason, uint32_t subcode)
+{
+#ifdef __aarch64__
+	uint64_t parameters[] = {reason, subcode};
+
+	(void) semihosting_call(SEMIHOSTING_SYS_EXIT, (uintptr_t) &parameters);
+#else
+	/* The subcode is not supported on AArch32. */
+	(void) semihosting_call(SEMIHOSTING_SYS_EXIT, reason);
+#endif
+}
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 53832c5..fff336c 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -139,6 +139,9 @@
 # Set the default algorithm for the generation of Trusted Board Boot keys
 KEY_ALG				:= rsa
 
+# Option to build TF with Measured Boot support
+MEASURED_BOOT			:= 0
+
 # NS timer register save and restore
 NS_TIMER_SWITCH			:= 0
 
@@ -201,6 +204,9 @@
 # Build option to choose whether Trusted Firmware uses library at ROM
 USE_ROMLIB			:= 0
 
+# Chain of trust.
+COT				:= tbbr
+
 # Use tbbr_oid.h instead of platform_oid.h
 USE_TBBR_DEFS			:= 1
 
diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c
index 89636d1..43b1374 100644
--- a/plat/arm/board/fvp/fvp_bl2_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c
@@ -1,12 +1,10 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <drivers/arm/sp804_delay_timer.h>
-#include <drivers/generic_delay_timer.h>
-#include <lib/mmio.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
 #include <platform_def.h>
diff --git a/plat/arm/board/fvp/fvp_err.c b/plat/arm/board/fvp/fvp_err.c
index 2437cd4..62ac882 100644
--- a/plat/arm/board/fvp/fvp_err.c
+++ b/plat/arm/board/fvp/fvp_err.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,7 +10,6 @@
 #include <drivers/arm/sp805.h>
 #include <drivers/cfi/v2m_flash.h>
 #include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
 #include <platform_def.h>
 
 /*
diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c
index 0a62543..c47d837 100644
--- a/plat/arm/board/fvp/fvp_pm.c
+++ b/plat/arm/board/fvp/fvp_pm.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-#include <errno.h>
 
 #include <arch_helpers.h>
 #include <common/debug.h>
@@ -16,7 +15,6 @@
 #include <lib/psci/psci.h>
 #include <plat/arm/common/arm_config.h>
 #include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
 #include <platform_def.h>
 
 #include "fvp_private.h"
diff --git a/plat/arm/board/fvp/jmptbl.i b/plat/arm/board/fvp/jmptbl.i
index bfa9b56..6ccdd28 100644
--- a/plat/arm/board/fvp/jmptbl.i
+++ b/plat/arm/board/fvp/jmptbl.i
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -19,6 +19,7 @@
 fdt     fdt_setprop_inplace
 fdt     fdt_check_header
 fdt     fdt_node_offset_by_compatible
+fdt     fdt_setprop_inplace_namelen_partial
 mbedtls mbedtls_asn1_get_alg
 mbedtls mbedtls_asn1_get_alg_null
 mbedtls mbedtls_asn1_get_bitstring_null
diff --git a/plat/arm/board/juno/jmptbl.i b/plat/arm/board/juno/jmptbl.i
index bfa9b56..6ccdd28 100644
--- a/plat/arm/board/juno/jmptbl.i
+++ b/plat/arm/board/juno/jmptbl.i
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -19,6 +19,7 @@
 fdt     fdt_setprop_inplace
 fdt     fdt_check_header
 fdt     fdt_node_offset_by_compatible
+fdt     fdt_setprop_inplace_namelen_partial
 mbedtls mbedtls_asn1_get_alg
 mbedtls mbedtls_asn1_get_alg_null
 mbedtls mbedtls_asn1_get_bitstring_null
diff --git a/plat/arm/board/juno/juno_err.c b/plat/arm/board/juno/juno_err.c
index 961bfda..60699cc 100644
--- a/plat/arm/board/juno/juno_err.c
+++ b/plat/arm/board/juno/juno_err.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,6 @@
 #include <arch_helpers.h>
 #include <drivers/arm/sp805.h>
 #include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
 #include <platform_def.h>
 
 /*
diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk
index db41e0e..43c37ff 100644
--- a/plat/arm/board/rde1edge/platform.mk
+++ b/plat/arm/board/rde1edge/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2019, Arm Limited. All rights reserved.
+# Copyright (c) 2018-2020, Arm Limited. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -24,6 +24,7 @@
 
 BL31_SOURCES		+=	${SGI_CPU_SOURCES}			\
 				${RDE1EDGE_BASE}/rde1edge_plat.c	\
+				${RDE1EDGE_BASE}/rde1edge_topology.c	\
 				drivers/cfi/v2m/v2m_flash.c		\
 				lib/utils/mem_region.c			\
 				plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/rde1edge/rde1edge_topology.c b/plat/arm/board/rde1edge/rde1edge_topology.c
new file mode 100644
index 0000000..0b56f20
--- /dev/null
+++ b/plat/arm/board/rde1edge/rde1edge_topology.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ ******************************************************************************/
+static const unsigned char rde1edge_pd_tree_desc[] = {
+	PLAT_ARM_CLUSTER_COUNT,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER
+};
+
+/******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	return rde1edge_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,		\
+	16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+};
diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk
index b44c70a..ca1e95e 100644
--- a/plat/arm/board/rdn1edge/platform.mk
+++ b/plat/arm/board/rdn1edge/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -24,6 +24,7 @@
 
 BL31_SOURCES		+=	${SGI_CPU_SOURCES}			\
 				${RDN1EDGE_BASE}/rdn1edge_plat.c	\
+				${RDN1EDGE_BASE}/rdn1edge_topology.c	\
 				drivers/cfi/v2m/v2m_flash.c		\
 				lib/utils/mem_region.c			\
 				plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/rdn1edge/rdn1edge_topology.c b/plat/arm/board/rdn1edge/rdn1edge_topology.c
new file mode 100644
index 0000000..687ae35
--- /dev/null
+++ b/plat/arm/board/rdn1edge/rdn1edge_topology.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ ******************************************************************************/
+static const unsigned char rdn1edge_pd_tree_desc[] = {
+	PLAT_ARM_CLUSTER_COUNT,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER
+};
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	return rdn1edge_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+	0, 1, 2, 3, 4, 5, 6, 7
+};
diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk
index b9fa099..ce2717f 100644
--- a/plat/arm/board/sgi575/platform.mk
+++ b/plat/arm/board/sgi575/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -24,6 +24,7 @@
 
 BL31_SOURCES		+=	${SGI_CPU_SOURCES}			\
 				${SGI575_BASE}/sgi575_plat.c		\
+				${SGI575_BASE}/sgi575_topology.c	\
 				drivers/cfi/v2m/v2m_flash.c		\
 				lib/utils/mem_region.c			\
 				plat/arm/common/arm_nor_psci_mem_protect.c
diff --git a/plat/arm/board/sgi575/sgi575_topology.c b/plat/arm/board/sgi575/sgi575_topology.c
new file mode 100644
index 0000000..f7c3856
--- /dev/null
+++ b/plat/arm/board/sgi575/sgi575_topology.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ ******************************************************************************/
+static const unsigned char sgi575_pd_tree_desc[] = {
+	PLAT_ARM_CLUSTER_COUNT,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER,
+	CSS_SGI_MAX_CPUS_PER_CLUSTER
+};
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+	return sgi575_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+	0, 1, 2, 3, 4, 5, 6, 7
+};
diff --git a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
index 7aeeb2a..78360b0 100644
--- a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
+++ b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,7 +8,6 @@
 
 #include <common/bl_common.h>
 #include <common/desc_image_load.h>
-#include <plat/common/platform.h>
 
 /*******************************************************************************
  * Following descriptor provides BL image/ep information that gets used
diff --git a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
index 0514b39..6a8943d 100644
--- a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
+++ b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,7 +8,6 @@
 
 #include <common/bl_common.h>
 #include <common/desc_image_load.h>
-#include <plat/common/platform.h>
 
 /*******************************************************************************
  * Following descriptor provides BL image/ep information that gets used
diff --git a/plat/arm/common/aarch64/execution_state_switch.c b/plat/arm/common/aarch64/execution_state_switch.c
index 8835fa1..bed929a 100644
--- a/plat/arm/common/aarch64/execution_state_switch.c
+++ b/plat/arm/common/aarch64/execution_state_switch.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,7 +12,6 @@
 #include <lib/el3_runtime/context_mgmt.h>
 #include <lib/psci/psci.h>
 #include <lib/utils.h>
-#include <plat/arm/common/arm_sip_svc.h>
 #include <plat/arm/common/plat_arm.h>
 #include <smccc_helpers.h>
 
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 939885f..c135d7f 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -14,7 +14,6 @@
 #include <lib/debugfs.h>
 #include <lib/extensions/ras.h>
 #include <lib/mmio.h>
-#include <lib/utils.h>
 #include <lib/xlat_tables/xlat_tables_compat.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
@@ -56,6 +55,14 @@
 					MT_CODE | MT_SECURE)
 #endif
 
+#if SEPARATE_NOBITS_REGION
+#define MAP_BL31_NOBITS		MAP_REGION_FLAT(			\
+					BL31_NOBITS_BASE,		\
+					BL31_NOBITS_LIMIT 		\
+						- BL31_NOBITS_BASE,	\
+					MT_MEMORY | MT_RW | MT_SECURE)
+
+#endif
 /*******************************************************************************
  * Return a pointer to the 'entry_point_info' structure of the next image for the
  * security state specified. BL33 corresponds to the non-secure image type
@@ -295,6 +302,9 @@
 #if RECLAIM_INIT_CODE
 		MAP_BL_INIT_CODE,
 #endif
+#if SEPARATE_NOBITS_REGION
+		MAP_BL31_NOBITS,
+#endif
 		ARM_MAP_BL_RO,
 #if USE_ROMLIB
 		ARM_MAP_ROMLIB_CODE,
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index 03d842a..d1e9620 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -16,7 +16,6 @@
 #include <lib/xlat_tables/xlat_tables_compat.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/common/platform.h>
-#include <services/spm_mm_partition.h>
 
 /* Weak definitions may be overridden in specific ARM standard platform */
 #pragma weak plat_get_ns_image_entrypoint
@@ -173,7 +172,7 @@
 int plat_sdei_validate_entry_point(uintptr_t ep, unsigned int client_mode)
 {
 	uint64_t par, pa;
-	uint32_t scr_el3;
+	u_register_t scr_el3;
 
 	/* Doing Non-secure address translation requires SCR_EL3.NS set */
 	scr_el3 = read_scr_el3();
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 9d4f05e..9f4bc21 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -125,6 +125,23 @@
 # mapping the former as executable and the latter as execute-never.
 SEPARATE_CODE_AND_RODATA	:=	1
 
+# On ARM platforms, disable SEPARATE_NOBITS_REGION by default. Both PROGBITS
+# and NOBITS sections of BL31 image are adjacent to each other and loaded
+# into Trusted SRAM.
+SEPARATE_NOBITS_REGION		:=	0
+
+# In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
+# BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
+# the build to require that ARM_BL31_IN_DRAM is enabled as well.
+ifeq ($(SEPARATE_NOBITS_REGION),1)
+    ifneq ($(ARM_BL31_IN_DRAM),1)
+         $(error For SEPARATE_NOBITS_REGION, ARM_BL31_IN_DRAM must be enabled)
+    endif
+    ifneq ($(RECLAIM_INIT_CODE),0)
+          $(error For SEPARATE_NOBITS_REGION, RECLAIM_INIT_CODE cannot be supported)
+    endif
+endif
+
 # Disable ARM Cryptocell by default
 ARM_CRYPTOCELL_INTEG		:=	0
 $(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
@@ -254,7 +271,13 @@
     AUTH_SOURCES	:=	drivers/auth/auth_mod.c				\
 				drivers/auth/crypto_mod.c			\
 				drivers/auth/img_parser_mod.c			\
-				drivers/auth/tbbr/tbbr_cot.c			\
+
+    # Include the selected chain of trust sources.
+    ifeq (${COT},tbbr)
+        AUTH_SOURCES	+=	drivers/auth/tbbr/tbbr_cot.c
+    else
+        $(error Unknown chain of trust ${COT})
+    endif
 
     BL1_SOURCES		+=	${AUTH_SOURCES}					\
 				bl1/tbbr/tbbr_img_desc.c			\
diff --git a/plat/arm/common/arm_dyn_cfg_helpers.c b/plat/arm/common/arm_dyn_cfg_helpers.c
index 36d37f8..daf0f0a 100644
--- a/plat/arm/common/arm_dyn_cfg_helpers.c
+++ b/plat/arm/common/arm_dyn_cfg_helpers.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,7 +8,6 @@
 
 #include <libfdt.h>
 
-#include <common/desc_image_load.h>
 #include <common/fdt_wrappers.h>
 #include <plat/arm/common/arm_dyn_cfg_helpers.h>
 #include <plat/arm/common/plat_arm.h>
diff --git a/plat/arm/common/arm_nor_psci_mem_protect.c b/plat/arm/common/arm_nor_psci_mem_protect.c
index b9181eb..1fa234d 100644
--- a/plat/arm/common/arm_nor_psci_mem_protect.c
+++ b/plat/arm/common/arm_nor_psci_mem_protect.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,7 +9,6 @@
 #include <common/debug.h>
 #include <drivers/cfi/v2m_flash.h>
 #include <lib/psci/psci.h>
-#include <lib/mmio.h>
 #include <lib/utils.h>
 #include <plat/arm/common/plat_arm.h>
 
diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c
index c95f452..5434c94 100644
--- a/plat/arm/common/arm_pm.c
+++ b/plat/arm/common/arm_pm.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-#include <errno.h>
 
 #include <platform_def.h>
 
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index bb69914..0cc746b 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -11,7 +11,6 @@
 #include <bl32/sp_min/platform_sp_min.h>
 #include <common/bl_common.h>
 #include <common/debug.h>
-#include <drivers/arm/pl011.h>
 #include <drivers/console.h>
 #include <lib/mmio.h>
 #include <plat/arm/common/plat_arm.h>
diff --git a/plat/arm/css/common/css_pm.c b/plat/arm/css/common/css_pm.c
index 01c674f..af69c6f 100644
--- a/plat/arm/css/common/css_pm.c
+++ b/plat/arm/css/common/css_pm.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-#include <errno.h>
 
 #include <platform_def.h>
 
@@ -15,7 +14,6 @@
 #include <lib/cassert.h>
 #include <plat/arm/common/plat_arm.h>
 #include <plat/arm/css/common/css_pm.h>
-#include <plat/common/platform.h>
 
 /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */
 #pragma weak plat_arm_psci_pm_ops
diff --git a/plat/arm/css/sgi/sgi_topology.c b/plat/arm/css/sgi/sgi_topology.c
index 7aa9e40..1c3b5bf 100644
--- a/plat/arm/css/sgi/sgi_topology.c
+++ b/plat/arm/css/sgi/sgi_topology.c
@@ -1,62 +1,14 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
 
-#include <sgi_variant.h>
-
-/* Topology */
 /*
- * The power domain tree descriptor. The cluster power domains are
- * arranged so that when the PSCI generic code creates the power domain tree,
- * the indices of the CPU power domain nodes it allocates match the linear
- * indices returned by plat_core_pos_by_mpidr().
+ * Common topology related methods for SGI and RD based platforms
  */
-const unsigned char sgi_pd_tree_desc[] = {
-	PLAT_ARM_CLUSTER_COUNT,
-	CSS_SGI_MAX_CPUS_PER_CLUSTER,
-	CSS_SGI_MAX_CPUS_PER_CLUSTER
-};
-
-/* RD-E1-Edge platform consists of 16 physical CPUS and 32 threads */
-const unsigned char rd_e1_edge_pd_tree_desc[] = {
-	PLAT_ARM_CLUSTER_COUNT,
-	CSS_SGI_MAX_CPUS_PER_CLUSTER,
-	CSS_SGI_MAX_CPUS_PER_CLUSTER,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU,
-	CSS_SGI_MAX_PE_PER_CPU
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
-	if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM &&
-	    sgi_plat_info.config_id == RD_E1_EDGE_CONFIG_ID)
-		return rd_e1_edge_pd_tree_desc;
-	else
-		return sgi_pd_tree_desc;
-}
-
 /*******************************************************************************
  * This function returns the core count within the cluster corresponding to
  * `mpidr`.
@@ -66,15 +18,7 @@
 	return CSS_SGI_MAX_CPUS_PER_CLUSTER;
 }
 
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[32] = {
-	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,		\
-	16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
-};
-
+#if ARM_PLAT_MT
 /******************************************************************************
  * Return the number of PE's supported by the CPU.
  *****************************************************************************/
@@ -82,3 +26,4 @@
 {
 	return CSS_SGI_MAX_PE_PER_CPU;
 }
+#endif
diff --git a/plat/common/plat_bl_common.c b/plat/common/plat_bl_common.c
index b46656c..6070db2 100644
--- a/plat/common/plat_bl_common.c
+++ b/plat/common/plat_bl_common.c
@@ -1,11 +1,10 @@
 /*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-#include <errno.h>
 
 #include <arch_helpers.h>
 #include <common/bl_common.h>
diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c
index c76de64..9232cbc 100644
--- a/plat/imx/imx8qm/imx8qm_bl31_setup.c
+++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,12 +27,13 @@
 #include <sci/sci.h>
 #include <sec_rsrc.h>
 
-IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
-IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
-IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START);
-IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END);
+static const unsigned long BL31_COHERENT_RAM_START	= BL_COHERENT_RAM_BASE;
+static const unsigned long BL31_COHERENT_RAM_END	= BL_COHERENT_RAM_END;
+static const unsigned long BL31_RO_START		= BL_CODE_BASE;
+static const unsigned long BL31_RO_END			= BL_CODE_END;
+static const unsigned long BL31_RW_END			= BL_END;
+
 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
-IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
 
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
diff --git a/plat/imx/imx8qx/imx8qx_bl31_setup.c b/plat/imx/imx8qx/imx8qx_bl31_setup.c
index bfe4052..58c82ce 100644
--- a/plat/imx/imx8qx/imx8qx_bl31_setup.c
+++ b/plat/imx/imx8qx/imx8qx_bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,12 +27,13 @@
 #include <sci/sci.h>
 #include <sec_rsrc.h>
 
-IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
-IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
-IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START);
-IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END);
+static const unsigned long BL31_COHERENT_RAM_START	= BL_COHERENT_RAM_BASE;
+static const unsigned long BL31_COHERENT_RAM_END	= BL_COHERENT_RAM_END;
+static const unsigned long BL31_RO_START		= BL_CODE_BASE;
+static const unsigned long BL31_RO_END			= BL_CODE_END;
+static const unsigned long BL31_RW_END			= BL_END;
+
 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START);
-IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END);
 
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index 375483d..13099b4 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -11,8 +11,10 @@
 #include <common/bl_common.h>
 #include <drivers/arm/gicv2.h>
 #include <drivers/ti/uart/uart_16550.h>
+#include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables.h>
 
+#include "socfpga_private.h"
 
 static entry_point_info_t bl32_image_ep_info;
 static entry_point_info_t bl33_image_ep_info;
@@ -44,23 +46,33 @@
 	void *from_bl2 = (void *) arg0;
 
 	bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
-
 	assert(params_from_bl2 != NULL);
-	assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
-	assert(params_from_bl2->h.version >= VERSION_2);
 
 	/*
 	 * Copy BL32 (if populated by BL31) and BL33 entry point information.
 	 * They are stored in Secure RAM, in BL31's address space.
 	 */
 
+	if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
+		params_from_bl2->h.version >= VERSION_2) {
+
-	bl_params_node_t *bl_params = params_from_bl2->head;
+		bl_params_node_t *bl_params = params_from_bl2->head;
 
-	while (bl_params) {
-		if (bl_params->image_id == BL33_IMAGE_ID)
-			bl33_image_ep_info = *bl_params->ep_info;
+		while (bl_params) {
+			if (bl_params->image_id == BL33_IMAGE_ID)
+				bl33_image_ep_info = *bl_params->ep_info;
 
-		bl_params = bl_params->next_params_info;
+			bl_params = bl_params->next_params_info;
+		}
+	} else {
+		struct socfpga_bl31_params *arg_from_bl2 =
+			(struct socfpga_bl31_params *) from_bl2;
+
+		assert(arg_from_bl2->h.type == PARAM_BL31);
+		assert(arg_from_bl2->h.version >= VERSION_1);
+
+		bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
+		bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
 	}
 	SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
 }
@@ -91,6 +103,10 @@
 	gicv2_distif_init();
 	gicv2_pcpu_distif_init();
 	gicv2_cpuif_enable();
+
+	/* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
+	mmio_write_64(PLAT_CPU_RELEASE_ADDR,
+		(uint64_t)plat_secondary_cpus_bl31_entry);
 }
 
 const mmap_region_t plat_agilex_mmap[] = {
diff --git a/plat/intel/soc/common/include/socfpga_system_manager.h b/plat/intel/soc/common/include/socfpga_system_manager.h
index f1637ae..68e30b8 100644
--- a/plat/intel/soc/common/include/socfpga_system_manager.h
+++ b/plat/intel/soc/common/include/socfpga_system_manager.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -106,7 +106,6 @@
 #define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0			0xf7004688
 #define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0				0xf7018628
 
-void enable_nonsecure_access(void);
 void enable_ns_peripheral_access(void);
 void enable_ns_bridge_access(void);
 
diff --git a/plat/mediatek/mt8173/plat_pm.c b/plat/mediatek/mt8173/plat_pm.c
index c8d4599..67f1c73 100644
--- a/plat/mediatek/mt8173/plat_pm.c
+++ b/plat/mediatek/mt8173/plat_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -236,7 +236,7 @@
 
 static void plat_cpu_standby(plat_local_state_t cpu_state)
 {
-	unsigned int scr;
+	u_register_t scr;
 
 	scr = read_scr_el3();
 	write_scr_el3(scr | SCR_IRQ_BIT);
diff --git a/plat/mediatek/mt8183/plat_pm.c b/plat/mediatek/mt8183/plat_pm.c
index 2358ec6..6094a17 100644
--- a/plat/mediatek/mt8183/plat_pm.c
+++ b/plat/mediatek/mt8183/plat_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, MediaTek Inc. All rights reserved.
+ * Copyright (c) 2019-2020, MediaTek Inc. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -197,7 +197,7 @@
 
 static void plat_cpu_standby(plat_local_state_t cpu_state)
 {
-	unsigned int scr;
+	u_register_t scr;
 
 	scr = read_scr_el3();
 	write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c
index ae899c4..eaf9675 100644
--- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c
+++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.c
@@ -316,7 +316,7 @@
 	/* prepare the MRQ_CLK command */
 	req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_ENABLE, clk_id);
 
-	ret = tegra_bpmp_ipc_send_req_atomic(MRQ_CLK, &req, sizeof(req),
+	ret = tegra_bpmp_ipc_send_req_atomic(MRQ_CLK, &req, (uint32_t)sizeof(req),
 			NULL, 0);
 	if (ret != 0) {
 		ERROR("%s: failed for module %d with error %d\n", __func__,
@@ -339,7 +339,7 @@
 	/* prepare the MRQ_CLK command */
 	req.cmd_and_id = make_mrq_clk_cmd(CMD_CLK_DISABLE, clk_id);
 
-	ret = tegra_bpmp_ipc_send_req_atomic(MRQ_CLK, &req, sizeof(req),
+	ret = tegra_bpmp_ipc_send_req_atomic(MRQ_CLK, &req, (uint32_t)sizeof(req),
 			NULL, 0);
 	if (ret != 0) {
 		ERROR("%s: failed for module %d with error %d\n", __func__,
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.h b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.h
index 7059c37..d85b906 100644
--- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.h
+++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/intf.h
@@ -1,17 +1,17 @@
 /*
- * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef INTF_H
-#define INTF_H
+#ifndef BPMP_INTF_H
+#define BPMP_INTF_H
 
 /**
  * Flags used in IPC req
  */
 #define FLAG_DO_ACK			(U(1) << 0)
-#define FLAG_RING_DOORBELL	(U(1) << 1)
+#define FLAG_RING_DOORBELL		(U(1) << 1)
 
 /* Bit 1 is designated for CCPlex in secure world */
 #define HSP_MASTER_CCPLEX_BIT	(U(1) << 1)
@@ -77,16 +77,16 @@
  *
  */
 enum {
-	CMD_CLK_GET_RATE = 1,
-	CMD_CLK_SET_RATE = 2,
-	CMD_CLK_ROUND_RATE = 3,
-	CMD_CLK_GET_PARENT = 4,
-	CMD_CLK_SET_PARENT = 5,
-	CMD_CLK_IS_ENABLED = 6,
-	CMD_CLK_ENABLE = 7,
-	CMD_CLK_DISABLE = 8,
-	CMD_CLK_GET_ALL_INFO = 14,
-	CMD_CLK_GET_MAX_CLK_ID = 15,
+	CMD_CLK_GET_RATE = U(1),
+	CMD_CLK_SET_RATE = U(2),
+	CMD_CLK_ROUND_RATE = U(3),
+	CMD_CLK_GET_PARENT = U(4),
+	CMD_CLK_SET_PARENT = U(5),
+	CMD_CLK_IS_ENABLED = U(6),
+	CMD_CLK_ENABLE = U(7),
+	CMD_CLK_DISABLE = U(8),
+	CMD_CLK_GET_ALL_INFO = U(14),
+	CMD_CLK_GET_MAX_CLK_ID = U(15),
 	CMD_CLK_MAX,
 };
 
@@ -124,4 +124,4 @@
  */
 #define make_mrq_clk_cmd(cmd, id)	(((cmd) << 24) | (id & 0xFFFFFF))
 
-#endif /* INTF_H */
+#endif /* BPMP_INTF_H */
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.h b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.h
index 42e6a1f..1b31821 100644
--- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.h
+++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.h
@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2017-2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef IVC_H
-#define IVC_H
+#ifndef BPMP_IVC_H
+#define BPMP_IVC_H
 
 #include <lib/utils_def.h>
 #include <stdint.h>
@@ -15,22 +15,21 @@
 #define IVC_CHHDR_TX_FIELDS	U(16)
 #define IVC_CHHDR_RX_FIELDS	U(16)
 
-struct ivc;
 struct ivc_channel_header;
 
-/* callback handler for notify on receiving a response */
-typedef void (* ivc_notify_function)(const struct ivc *);
-
 struct ivc {
 	struct ivc_channel_header *rx_channel;
 	struct ivc_channel_header *tx_channel;
 	uint32_t w_pos;
 	uint32_t r_pos;
-	ivc_notify_function notify;
+	void (*notify)(const struct ivc *);
 	uint32_t nframes;
 	uint32_t frame_size;
 };
 
+/* callback handler for notify on receiving a response */
+typedef void (* ivc_notify_function)(const struct ivc *);
+
 int32_t tegra_ivc_init(struct ivc *ivc, uintptr_t rx_base, uintptr_t tx_base,
 		uint32_t nframes, uint32_t frame_size,
 		ivc_notify_function notify);
@@ -48,4 +47,4 @@
 bool tegra_ivc_can_write(const struct ivc *ivc);
 bool tegra_ivc_can_read(const struct ivc *ivc);
 
-#endif /* IVC_H */
+#endif /* BPMP_IVC_H */
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index 2f31906..c2ef981 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,17 +27,6 @@
 static uint64_t video_mem_size_mb;
 
 /*
- * The following platform setup functions are weakly defined. They
- * provide typical implementations that will be overridden by a SoC.
- */
-#pragma weak plat_memctrl_tzdram_setup
-
-void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
-{
-	; /* do nothing */
-}
-
-/*
  * Init Memory controller during boot.
  */
 void tegra_memctrl_setup(void)
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 25fd84c..8a49e23 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -42,11 +42,12 @@
  ******************************************************************************/
 
 IMPORT_SYM(uint64_t, __RW_START__,	BL31_RW_START);
-IMPORT_SYM(uint64_t, __RW_END__,	BL31_RW_END);
-IMPORT_SYM(uint64_t, __RODATA_START__,	BL31_RODATA_BASE);
-IMPORT_SYM(uint64_t, __RODATA_END__,	BL31_RODATA_END);
-IMPORT_SYM(uint64_t, __TEXT_START__,	TEXT_START);
-IMPORT_SYM(uint64_t, __TEXT_END__,	TEXT_END);
+
+static const uint64_t BL31_RW_END	= BL_END;
+static const uint64_t BL31_RODATA_BASE	= BL_RO_DATA_BASE;
+static const uint64_t BL31_RODATA_END	= BL_RO_DATA_END;
+static const uint64_t TEXT_START	= BL_CODE_BASE;
+static const uint64_t TEXT_END		= BL_CODE_END;
 
 extern uint64_t tegra_bl31_phys_base;
 
@@ -64,35 +65,6 @@
 extern uint64_t ns_image_entrypoint;
 
 /*******************************************************************************
- * The following platform setup functions are weakly defined. They
- * provide typical implementations that will be overridden by a SoC.
- ******************************************************************************/
-#pragma weak plat_early_platform_setup
-#pragma weak plat_get_bl31_params
-#pragma weak plat_get_bl31_plat_params
-#pragma weak plat_late_platform_setup
-
-void plat_early_platform_setup(void)
-{
-	; /* do nothing */
-}
-
-struct tegra_bl31_params *plat_get_bl31_params(void)
-{
-	return NULL;
-}
-
-plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
-{
-	return NULL;
-}
-
-void plat_late_platform_setup(void)
-{
-	; /* do nothing */
-}
-
-/*******************************************************************************
  * Return a pointer to the 'entry_point_info' structure of the next image for
  * security state specified. BL33 corresponds to the non-secure image type
  * while BL32 corresponds to the secure image type.
@@ -136,8 +108,7 @@
 	/*
 	 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
 	 * there's no argument to relay from a previous bootloader. Platforms
-	 * might use custom ways to get arguments, so provide handlers which
-	 * they can override.
+	 * might use custom ways to get arguments.
 	 */
 	if (arg_from_bl2 == NULL) {
 		arg_from_bl2 = plat_get_bl31_params();
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index 34b5638..50c9592 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -25,7 +25,6 @@
 				plat/common/aarch64/crash_console_helpers.S	\
 				${TEGRA_GICv2_SOURCES}				\
 				${COMMON_DIR}/aarch64/tegra_helpers.S		\
-				${COMMON_DIR}/drivers/pmc/pmc.c			\
 				${COMMON_DIR}/lib/debug/profiler.c		\
 				${COMMON_DIR}/tegra_bl31_setup.c		\
 				${COMMON_DIR}/tegra_delay_timer.c		\
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 39dc42c..1f59f30 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,97 +28,6 @@
 extern uint64_t tegra_bl31_phys_base;
 extern uint64_t tegra_sec_entry_point;
 
-/*
- * The following platform setup functions are weakly defined. They
- * provide typical implementations that will be overridden by a SoC.
- */
-#pragma weak tegra_soc_pwr_domain_suspend_pwrdown_early
-#pragma weak tegra_soc_cpu_standby
-#pragma weak tegra_soc_pwr_domain_suspend
-#pragma weak tegra_soc_pwr_domain_on
-#pragma weak tegra_soc_pwr_domain_off
-#pragma weak tegra_soc_pwr_domain_on_finish
-#pragma weak tegra_soc_pwr_domain_power_down_wfi
-#pragma weak tegra_soc_prepare_system_reset
-#pragma weak tegra_soc_prepare_system_off
-#pragma weak tegra_soc_get_target_pwr_state
-
-int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
-{
-	return PSCI_E_NOT_SUPPORTED;
-}
-
-int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
-{
-	(void)cpu_state;
-	return PSCI_E_SUCCESS;
-}
-
-int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
-{
-	(void)target_state;
-	return PSCI_E_NOT_SUPPORTED;
-}
-
-int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
-{
-	(void)mpidr;
-	return PSCI_E_SUCCESS;
-}
-
-int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
-{
-	(void)target_state;
-	return PSCI_E_SUCCESS;
-}
-
-int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
-{
-	(void)target_state;
-	return PSCI_E_SUCCESS;
-}
-
-int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
-{
-	(void)target_state;
-	return PSCI_E_SUCCESS;
-}
-
-int32_t tegra_soc_prepare_system_reset(void)
-{
-	return PSCI_E_SUCCESS;
-}
-
-__dead2 void tegra_soc_prepare_system_off(void)
-{
-	ERROR("Tegra System Off: operation not handled.\n");
-	panic();
-}
-
-plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
-					     const plat_local_state_t *states,
-					     uint32_t ncpu)
-{
-	plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
-	uint32_t num_cpu = ncpu;
-	const plat_local_state_t *local_state = states;
-
-	(void)lvl;
-
-	assert(ncpu != 0U);
-
-	do {
-		temp = *local_state;
-		if ((temp < target)) {
-			target = temp;
-		}
-		--num_cpu;
-		local_state++;
-	} while (num_cpu != 0U);
-
-	return target;
-}
-
 /*******************************************************************************
  * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
  * call to get the `power_state` parameter. This allows the platform to encode
@@ -311,10 +221,10 @@
 	/* per-SoC system reset handler */
 	(void)tegra_soc_prepare_system_reset();
 
-	/*
-	 * Program the PMC in order to restart the system.
-	 */
-	tegra_pmc_system_reset();
+	/* wait for the system to reset */
+	for (;;) {
+		;
+	}
 }
 
 /*******************************************************************************
diff --git a/plat/nvidia/tegra/common/tegra_sip_calls.c b/plat/nvidia/tegra/common/tegra_sip_calls.c
index b8ba095..1d48cc0 100644
--- a/plat/nvidia/tegra/common/tegra_sip_calls.c
+++ b/plat/nvidia/tegra/common/tegra_sip_calls.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -26,32 +27,6 @@
 #define TEGRA_SIP_FIQ_NS_GET_CONTEXT		0x82000006
 
 /*******************************************************************************
- * SoC specific SiP handler
- ******************************************************************************/
-#pragma weak plat_sip_handler
-int32_t plat_sip_handler(uint32_t smc_fid,
-		     uint64_t x1,
-		     uint64_t x2,
-		     uint64_t x3,
-		     uint64_t x4,
-		     const void *cookie,
-		     void *handle,
-		     uint64_t flags)
-{
-	/* unused parameters */
-	(void)smc_fid;
-	(void)x1;
-	(void)x2;
-	(void)x3;
-	(void)x4;
-	(void)cookie;
-	(void)handle;
-	(void)flags;
-
-	return -ENOTSUP;
-}
-
-/*******************************************************************************
  * This function is responsible for handling all SiP calls
  ******************************************************************************/
 uintptr_t tegra_sip_handler(uint32_t smc_fid,
diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h
index dfed2aa..8e6c1fd 100644
--- a/plat/nvidia/tegra/include/t132/tegra_def.h
+++ b/plat/nvidia/tegra/include/t132/tegra_def.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -110,4 +111,10 @@
 #define TEGRA_TZRAM_BASE		U(0x7C010000)
 #define TEGRA_TZRAM_SIZE		U(0x10000)
 
+/*******************************************************************************
+ * Tegra DRAM memory base address
+ ******************************************************************************/
+#define TEGRA_DRAM_BASE			ULL(0x80000000)
+#define TEGRA_DRAM_END			ULL(0x27FFFFFFF)
+
 #endif /* TEGRA_DEF_H */
diff --git a/plat/nvidia/tegra/include/t186/tegra_def.h b/plat/nvidia/tegra/include/t186/tegra_def.h
index da050a8..f2a2334 100644
--- a/plat/nvidia/tegra/include/t186/tegra_def.h
+++ b/plat/nvidia/tegra/include/t186/tegra_def.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -279,4 +280,10 @@
 #define TEGRA_TZRAM_BASE		U(0x30000000)
 #define TEGRA_TZRAM_SIZE		U(0x40000)
 
+/*******************************************************************************
+ * Tegra DRAM memory base address
+ ******************************************************************************/
+#define TEGRA_DRAM_BASE			ULL(0x80000000)
+#define TEGRA_DRAM_END			ULL(0x27FFFFFFF)
+
 #endif /* TEGRA_DEF_H */
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index df1d656..a58ae9d 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -257,6 +257,12 @@
 #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET	U(0x6A0008)
 
 /*******************************************************************************
+ * Tegra DRAM memory base address
+ ******************************************************************************/
+#define TEGRA_DRAM_BASE			ULL(0x80000000)
+#define TEGRA_DRAM_END			ULL(0xFFFFFFFFF)
+
+/*******************************************************************************
  * XUSB STREAMIDs
  ******************************************************************************/
 #define TEGRA_SID_XUSB_HOST			U(0x1b)
diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h
index bbcfdc5..4a39aa1 100644
--- a/plat/nvidia/tegra/include/t210/tegra_def.h
+++ b/plat/nvidia/tegra/include/t210/tegra_def.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -268,4 +269,10 @@
 #define TEGRA_TZRAM_CARVEOUT_BASE	U(0x7C04C000)
 #define TEGRA_TZRAM_CARVEOUT_SIZE	U(0x4000)
 
+/*******************************************************************************
+ * Tegra DRAM memory base address
+ ******************************************************************************/
+#define TEGRA_DRAM_BASE			ULL(0x80000000)
+#define TEGRA_DRAM_END			ULL(0x27FFFFFFF)
+
 #endif /* TEGRA_DEF_H */
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index 761acde..b419d94 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,12 +19,6 @@
 #include <tegra_gic.h>
 
 /*******************************************************************************
- * Tegra DRAM memory base address
- ******************************************************************************/
-#define TEGRA_DRAM_BASE		ULL(0x80000000)
-#define TEGRA_DRAM_END		ULL(0x27FFFFFFF)
-
-/*******************************************************************************
  * Implementation defined ACTLR_EL1 bit definitions
  ******************************************************************************/
 #define ACTLR_EL1_PMSTATE_MASK		(ULL(0xF) << 0)
@@ -106,6 +101,7 @@
 int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state);
 int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state);
 int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state);
+int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state);
 int32_t tegra_soc_prepare_system_reset(void);
 __dead2 void tegra_soc_prepare_system_off(void);
 plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
diff --git a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
index bd3f46f..0e2edf0 100644
--- a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -35,6 +36,30 @@
 
 static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
 
+plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
+					     const plat_local_state_t *states,
+					     uint32_t ncpu)
+{
+	plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
+	uint32_t num_cpu = ncpu;
+	const plat_local_state_t *local_state = states;
+
+	(void)lvl;
+
+	assert(ncpu != 0U);
+
+	do {
+		temp = *local_state;
+		if ((temp < target)) {
+			target = temp;
+		}
+		--num_cpu;
+		local_state++;
+	} while (num_cpu != 0U);
+
+	return target;
+}
+
 int32_t tegra_soc_validate_power_state(unsigned int power_state,
 					psci_power_state_t *req_state)
 {
@@ -109,6 +134,12 @@
 	val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
 	write_actlr_el1(val | DENVER_CPU_STATE_POWER_DOWN);
 
+	return PSCI_E_SUCCESS;
+}
+
+int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
+{
+	(void)cpu_state;
 	return PSCI_E_SUCCESS;
 }
 
@@ -136,6 +167,16 @@
 	val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
 	write_actlr_el1(val | target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
 
+	return PSCI_E_SUCCESS;
+}
+
+int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
+{
+	return PSCI_E_NOT_SUPPORTED;
+}
+
+int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
+{
 	return PSCI_E_SUCCESS;
 }
 
@@ -152,5 +193,16 @@
 	/* Wait 1 ms to make sure clock source/device logic is stabilized. */
 	mdelay(1);
 
+	/*
+	 * Program the PMC in order to restart the system.
+	 */
+	tegra_pmc_system_reset();
+
 	return PSCI_E_SUCCESS;
 }
+
+__dead2 void tegra_soc_prepare_system_off(void)
+{
+	ERROR("Tegra System Off: operation not handled.\n");
+	panic();
+}
diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c
index df62678..2f54dd5 100644
--- a/plat/nvidia/tegra/soc/t132/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t132/plat_setup.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -121,3 +122,35 @@
 	tegra_gic_setup(NULL, 0);
 	tegra_gic_init();
 }
+
+/*******************************************************************************
+ * Return pointer to the BL31 params from previous bootloader
+ ******************************************************************************/
+struct tegra_bl31_params *plat_get_bl31_params(void)
+{
+	return NULL;
+}
+
+/*******************************************************************************
+ * Return pointer to the BL31 platform params from previous bootloader
+ ******************************************************************************/
+plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
+{
+	return NULL;
+}
+
+/*******************************************************************************
+ * Handler for early platform setup
+ ******************************************************************************/
+void plat_early_platform_setup(void)
+{
+	; /* do nothing */
+}
+
+/*******************************************************************************
+ * Handler for late platform setup
+ ******************************************************************************/
+void plat_late_platform_setup(void)
+{
+	; /* do nothing */
+}
diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk
index bb7b7ee..183e188 100644
--- a/plat/nvidia/tegra/soc/t132/platform_t132.mk
+++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk
@@ -1,5 +1,6 @@
 #
 # Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -23,6 +24,7 @@
 				lib/cpus/aarch64/denver.S		\
 				${COMMON_DIR}/drivers/flowctrl/flowctrl.c	\
 				${COMMON_DIR}/drivers/memctrl/memctrl_v1.c	\
+				${COMMON_DIR}/drivers/pmc/pmc.c			\
 				${SOC_DIR}/plat_psci_handlers.c		\
 				${SOC_DIR}/plat_sip_calls.c		\
 				${SOC_DIR}/plat_setup.c			\
diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
index df94396..4ca5e77 100644
--- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
@@ -95,71 +95,71 @@
  ******************************************************************************/
 const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
 	mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, DISABLE),
 	mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, DISABLE),
 	mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
 	mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, DISABLE),
 	mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, DISABLE),
 	mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, DISABLE),
 	mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
 	mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, DISABLE),
 	mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, DISABLE),
 	mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, DISABLE),
 	mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
 	mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, DISABLE),
 	mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
 	mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
 	mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
 	mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, DISABLE),
 	mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, DISABLE),
 	mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, DISABLE),
 	mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE),
 	mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
+	mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, DISABLE),
 	mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
-	mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
-	mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, DISABLE),
+	mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, DISABLE),
+	mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
 	mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE),
-	mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
+	mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, DISABLE),
 	mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
 	mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
 	mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 11394c0..2000e53 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -83,6 +84,12 @@
 	return ret;
 }
 
+int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
+{
+	(void)cpu_state;
+	return PSCI_E_SUCCESS;
+}
+
 int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 {
 	const plat_local_state_t *pwr_domain_state;
@@ -289,6 +296,11 @@
 	return PSCI_E_SUCCESS;
 }
 
+int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
+{
+	return PSCI_E_NOT_SUPPORTED;
+}
+
 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
 {
 	int32_t ret = PSCI_E_SUCCESS;
diff --git a/plat/nvidia/tegra/soc/t186/plat_setup.c b/plat/nvidia/tegra/soc/t186/plat_setup.c
index 1018caa..7e18b5c 100644
--- a/plat/nvidia/tegra/soc/t186/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t186/plat_setup.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -193,6 +194,14 @@
 	}
 }
 
+/*******************************************************************************
+ * Handler for late platform setup
+ ******************************************************************************/
+void plat_late_platform_setup(void)
+{
+	; /* do nothing */
+}
+
 /* Secure IRQs for Tegra186 */
 static const interrupt_prop_t tegra186_interrupt_props[] = {
 	INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
index b6572ff..1fe3aad 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
@@ -53,7 +53,6 @@
 int32_t nvg_is_sc7_allowed(void);
 int32_t nvg_online_core(uint32_t core);
 int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
-int32_t nvg_roc_clean_cache_trbits(void);
 int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
 int32_t nvg_roc_clean_cache_trbits(void);
 void nvg_enable_strict_checking_mode(void);
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
index ccc4665..9ccb823 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
@@ -19,123 +19,124 @@
  * occur when there is only new functionality.
  */
 enum {
-	TEGRA_NVG_VERSION_MAJOR = 6,
-	TEGRA_NVG_VERSION_MINOR = 6
+	TEGRA_NVG_VERSION_MAJOR = U(6),
+	TEGRA_NVG_VERSION_MINOR = U(6)
 };
 
 typedef enum {
-	TEGRA_NVG_CHANNEL_VERSION				= 0,
-	TEGRA_NVG_CHANNEL_POWER_PERF				= 1,
-	TEGRA_NVG_CHANNEL_POWER_MODES				= 2,
-	TEGRA_NVG_CHANNEL_WAKE_TIME				= 3,
-	TEGRA_NVG_CHANNEL_CSTATE_INFO				= 4,
-	TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND		= 5,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND		= 6,
-	TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND		= 8,
-	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST		= 10,
-	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE		= 11,
-	TEGRA_NVG_CHANNEL_NUM_CORES				= 20,
-	TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID			= 21,
-	TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING		= 22,
-	TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR			= 23,
-	TEGRA_NVG_CHANNEL_SHUTDOWN				= 42,
-	TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED			= 43,
-	TEGRA_NVG_CHANNEL_ONLINE_CORE				= 44,
-	TEGRA_NVG_CHANNEL_CC3_CTRL				= 45,
-	TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL			= 49,
-	TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC			= 50,
-	TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL			= 53,
-	TEGRA_NVG_CHANNEL_SECURITY_CONFIG			= 54,
-	TEGRA_NVG_CHANNEL_DEBUG_CONFIG				= 55,
-	TEGRA_NVG_CHANNEL_DDA_SNOC_MCF				= 56,
-	TEGRA_NVG_CHANNEL_DDA_MCF_ORD1				= 57,
-	TEGRA_NVG_CHANNEL_DDA_MCF_ORD2				= 58,
-	TEGRA_NVG_CHANNEL_DDA_MCF_ORD3				= 59,
-	TEGRA_NVG_CHANNEL_DDA_MCF_ISO				= 60,
-	TEGRA_NVG_CHANNEL_DDA_MCF_SISO				= 61,
-	TEGRA_NVG_CHANNEL_DDA_MCF_NISO				= 62,
-	TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE			= 63,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO			= 64,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO			= 65,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO			= 66,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE		= 67,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL			= 68,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR			= 69,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA		= 70,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA		= 71,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL			= 72,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL				= 73,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D			= 74,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD			= 75,
-	TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR			= 76,
-	TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL			= 77,
-	TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL		= 78,
-	TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL	= 79,
+	TEGRA_NVG_CHANNEL_VERSION				= U(0),
+	TEGRA_NVG_CHANNEL_POWER_PERF				= U(1),
+	TEGRA_NVG_CHANNEL_POWER_MODES				= U(2),
+	TEGRA_NVG_CHANNEL_WAKE_TIME				= U(3),
+	TEGRA_NVG_CHANNEL_CSTATE_INFO				= U(4),
+	TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND		= U(5),
+	TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND		= U(6),
+	TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND		= U(8),
+	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST		= U(10),
+	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE		= U(11),
+	TEGRA_NVG_CHANNEL_NUM_CORES				= U(20),
+	TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID			= U(21),
+	TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING		= U(22),
+	TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR			= U(23),
+	TEGRA_NVG_CHANNEL_SHUTDOWN				= U(42),
+	TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED			= U(43),
+	TEGRA_NVG_CHANNEL_ONLINE_CORE				= U(44),
+	TEGRA_NVG_CHANNEL_CC3_CTRL				= U(45),
+	TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL			= U(49),
+	TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC			= U(50),
+	TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL			= U(53),
+	TEGRA_NVG_CHANNEL_SECURITY_CONFIG			= U(54),
+	TEGRA_NVG_CHANNEL_DEBUG_CONFIG				= U(55),
+	TEGRA_NVG_CHANNEL_DDA_SNOC_MCF				= U(56),
+	TEGRA_NVG_CHANNEL_DDA_MCF_ORD1				= U(57),
+	TEGRA_NVG_CHANNEL_DDA_MCF_ORD2				= U(58),
+	TEGRA_NVG_CHANNEL_DDA_MCF_ORD3				= U(59),
+	TEGRA_NVG_CHANNEL_DDA_MCF_ISO				= U(60),
+	TEGRA_NVG_CHANNEL_DDA_MCF_SISO				= U(61),
+	TEGRA_NVG_CHANNEL_DDA_MCF_NISO				= U(62),
+	TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE			= U(63),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO			= U(64),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO			= U(65),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO			= U(66),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE		= U(67),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL			= U(68),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR			= U(69),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA		= U(70),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA		= U(71),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL			= U(72),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL				= U(73),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D			= U(74),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD			= U(75),
+	TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR			= U(76),
+	TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL			= U(77),
+	TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL		= U(78),
+	TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL	= U(79),
 
 	TEGRA_NVG_CHANNEL_LAST_INDEX
 } tegra_nvg_channel_id_t;
 
 typedef enum {
-	NVG_STAT_QUERY_SC7_ENTRIES		= 1,
-	NVG_STAT_QUERY_CC6_ENTRIES		= 6,
-	NVG_STAT_QUERY_CG7_ENTRIES		= 7,
-	NVG_STAT_QUERY_C6_ENTRIES		= 10,
-	NVG_STAT_QUERY_C7_ENTRIES		= 14,
-	NVG_STAT_QUERY_SC7_RESIDENCY_SUM	= 32,
-	NVG_STAT_QUERY_CC6_RESIDENCY_SUM	= 41,
-	NVG_STAT_QUERY_CG7_RESIDENCY_SUM	= 46,
-	NVG_STAT_QUERY_C6_RESIDENCY_SUM		= 51,
-	NVG_STAT_QUERY_C7_RESIDENCY_SUM		= 56,
-	NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM	= 60,
-	NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM	= 61,
-	NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM	= 62,
-	NVG_STAT_QUERY_C6_ENTRY_TIME_SUM	= 63,
-	NVG_STAT_QUERY_C7_ENTRY_TIME_SUM	= 64,
-	NVG_STAT_QUERY_SC7_EXIT_TIME_SUM	= 70,
-	NVG_STAT_QUERY_CC6_EXIT_TIME_SUM	= 71,
-	NVG_STAT_QUERY_CG7_EXIT_TIME_SUM	= 72,
-	NVG_STAT_QUERY_C6_EXIT_TIME_SUM		= 73,
-	NVG_STAT_QUERY_C7_EXIT_TIME_SUM		= 74,
-	NVG_STAT_QUERY_SC7_ENTRY_LAST		= 80,
-	NVG_STAT_QUERY_CC6_ENTRY_LAST		= 81,
-	NVG_STAT_QUERY_CG7_ENTRY_LAST		= 82,
-	NVG_STAT_QUERY_C6_ENTRY_LAST		= 83,
-	NVG_STAT_QUERY_C7_ENTRY_LAST		= 84,
-	NVG_STAT_QUERY_SC7_EXIT_LAST		= 90,
-	NVG_STAT_QUERY_CC6_EXIT_LAST		= 91,
-	NVG_STAT_QUERY_CG7_EXIT_LAST		= 92,
-	NVG_STAT_QUERY_C6_EXIT_LAST		= 93,
-	NVG_STAT_QUERY_C7_EXIT_LAST		= 94
+	NVG_STAT_QUERY_SC7_ENTRIES				= U(1),
+	NVG_STAT_QUERY_CC6_ENTRIES				= U(6),
+	NVG_STAT_QUERY_CG7_ENTRIES				= U(7),
+	NVG_STAT_QUERY_C6_ENTRIES				= U(10),
+	NVG_STAT_QUERY_C7_ENTRIES				= U(14),
+	NVG_STAT_QUERY_SC7_RESIDENCY_SUM			= U(32),
+	NVG_STAT_QUERY_CC6_RESIDENCY_SUM			= U(41),
+	NVG_STAT_QUERY_CG7_RESIDENCY_SUM			= U(46),
+	NVG_STAT_QUERY_C6_RESIDENCY_SUM				= U(51),
+	NVG_STAT_QUERY_C7_RESIDENCY_SUM				= U(56),
+	NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM			= U(60),
+	NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM			= U(61),
+	NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM			= U(62),
+	NVG_STAT_QUERY_C6_ENTRY_TIME_SUM			= U(63),
+	NVG_STAT_QUERY_C7_ENTRY_TIME_SUM			= U(64),
+	NVG_STAT_QUERY_SC7_EXIT_TIME_SUM			= U(70),
+	NVG_STAT_QUERY_CC6_EXIT_TIME_SUM			= U(71),
+	NVG_STAT_QUERY_CG7_EXIT_TIME_SUM			= U(72),
+	NVG_STAT_QUERY_C6_EXIT_TIME_SUM				= U(73),
+	NVG_STAT_QUERY_C7_EXIT_TIME_SUM				= U(74),
+	NVG_STAT_QUERY_SC7_ENTRY_LAST				= U(80),
+	NVG_STAT_QUERY_CC6_ENTRY_LAST				= U(81),
+	NVG_STAT_QUERY_CG7_ENTRY_LAST				= U(82),
+	NVG_STAT_QUERY_C6_ENTRY_LAST				= U(83),
+	NVG_STAT_QUERY_C7_ENTRY_LAST				= U(84),
+	NVG_STAT_QUERY_SC7_EXIT_LAST				= U(90),
+	NVG_STAT_QUERY_CC6_EXIT_LAST				= U(91),
+	NVG_STAT_QUERY_CG7_EXIT_LAST				= U(92),
+	NVG_STAT_QUERY_C6_EXIT_LAST				= U(93),
+	NVG_STAT_QUERY_C7_EXIT_LAST				= U(94)
+
 } tegra_nvg_stat_query_t;
 
 typedef enum {
-	TEGRA_NVG_CORE_C0 = 0,
-	TEGRA_NVG_CORE_C1 = 1,
-	TEGRA_NVG_CORE_C6 = 6,
-	TEGRA_NVG_CORE_C7 = 7,
-	TEGRA_NVG_CORE_WARMRSTREQ = 8
+	TEGRA_NVG_CORE_C0 = U(0),
+	TEGRA_NVG_CORE_C1 = U(1),
+	TEGRA_NVG_CORE_C6 = U(6),
+	TEGRA_NVG_CORE_C7 = U(7),
+	TEGRA_NVG_CORE_WARMRSTREQ = U(8)
 } tegra_nvg_core_sleep_state_t;
 
 typedef enum {
-	TEGRA_NVG_SHUTDOWN = 0U,
-	TEGRA_NVG_REBOOT = 1U
+	TEGRA_NVG_SHUTDOWN = U(0),
+	TEGRA_NVG_REBOOT = U(1)
 } tegra_nvg_shutdown_reboot_state_t;
 
 typedef enum {
-	TEGRA_NVG_CLUSTER_CC0 = 0,
-	TEGRA_NVG_CLUSTER_AUTO_CC1 = 1,
-	TEGRA_NVG_CLUSTER_CC6 = 6
+	TEGRA_NVG_CLUSTER_CC0		= U(0),
+	TEGRA_NVG_CLUSTER_AUTO_CC1	= U(1),
+	TEGRA_NVG_CLUSTER_CC6		= U(6)
 } tegra_nvg_cluster_sleep_state_t;
 
 typedef enum {
-	TEGRA_NVG_CG_CG0 = 0,
-	TEGRA_NVG_CG_CG7 = 7
+	TEGRA_NVG_CG_CG0 = U(0),
+	TEGRA_NVG_CG_CG7 = U(7)
 } tegra_nvg_cluster_group_sleep_state_t;
 
 typedef enum {
-	TEGRA_NVG_SYSTEM_SC0 = 0,
-	TEGRA_NVG_SYSTEM_SC7 = 7,
-	TEGRA_NVG_SYSTEM_SC8 = 8
+	TEGRA_NVG_SYSTEM_SC0 = U(0),
+	TEGRA_NVG_SYSTEM_SC7 = U(7),
+	TEGRA_NVG_SYSTEM_SC8 = U(8)
 } tegra_nvg_system_sleep_state_t;
 
 // ---------------------------------------------------------------------------
@@ -145,95 +146,95 @@
 typedef union {
 	uint64_t flat;
 	struct nvg_version_channel_t {
-		uint32_t minor_version	: 32;
-		uint32_t major_version	: 32;
+		uint32_t minor_version : U(32);
+		uint32_t major_version : U(32);
 	} bits;
 } nvg_version_data_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_power_perf_channel_t {
-		uint32_t perf_per_watt	: 1;
-		uint32_t reserved_31_1	: 31;
-		uint32_t reserved_63_32	: 32;
+		uint32_t perf_per_watt	: U(1);
+		uint32_t reserved_31_1	: U(31);
+		uint32_t reserved_63_32	: U(32);
 	} bits;
 } nvg_power_perf_channel_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_power_modes_channel_t {
-		uint32_t low_battery	: 1;
-		uint32_t reserved_1_1	: 1;
-		uint32_t battery_save	: 1;
-		uint32_t reserved_31_3	: 29;
-		uint32_t reserved_63_32	: 32;
+		uint32_t low_battery	: U(1);
+		uint32_t reserved_1_1	: U(1);
+		uint32_t battery_save	: U(1);
+		uint32_t reserved_31_3	: U(29);
+		uint32_t reserved_63_32	: U(32);
 	} bits;
 } nvg_power_modes_channel_t;
 
 typedef union nvg_channel_1_data_u {
 	uint64_t flat;
 	struct nvg_channel_1_data_s {
-		uint32_t perf_per_watt_mode	: 1;
-		uint32_t reserved_31_1		: 31;
-		uint32_t reserved_63_32		: 32;
+		uint32_t perf_per_watt_mode	: U(1);
+		uint32_t reserved_31_1		: U(31);
+		uint32_t reserved_63_32		: U(32);
 	} bits;
 } nvg_channel_1_data_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_ccplex_cache_control_channel_t {
-		uint32_t gpu_ways	: 5;
-		uint32_t reserved_7_5	: 3;
-		uint32_t gpu_only_ways	: 5;
-		uint32_t reserved_31_13	: 19;
-		uint32_t reserved_63_32	: 32;
+		uint32_t gpu_ways	: U(5);
+		uint32_t reserved_7_5	: U(3);
+		uint32_t gpu_only_ways	: U(5);
+		uint32_t reserved_31_13 : U(19);
+		uint32_t reserved_63_32 : U(32);
 	} bits;
 } nvg_ccplex_cache_control_channel_t;
 
 typedef union nvg_channel_2_data_u {
 	uint64_t flat;
 	struct nvg_channel_2_data_s {
-		uint32_t reserved_1_0		: 2;
-		uint32_t battery_saver_mode	: 1;
-		uint32_t reserved_31_3		: 29;
-		uint32_t reserved_63_32		: 32;
+		uint32_t reserved_1_0		: U(2);
+		uint32_t battery_saver_mode	: U(1);
+		uint32_t reserved_31_3		: U(29);
+		uint32_t reserved_63_32		: U(32);
 	} bits;
 } nvg_channel_2_data_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_wake_time_channel_t {
-		uint32_t wake_time	: 32;
-		uint32_t reserved_63_32	: 32;
+		uint32_t wake_time		: U(32);
+		uint32_t reserved_63_32		: U(32);
 	} bits;
 } nvg_wake_time_channel_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_cstate_info_channel_t {
-		uint32_t cluster_state			: 3;
-		uint32_t reserved_6_3			: 4;
-		uint32_t update_cluster			: 1;
-		uint32_t cg_cstate				: 3;
-		uint32_t reserved_14_11			: 4;
-		uint32_t update_cg				: 1;
-		uint32_t system_cstate			: 4;
-		uint32_t reserved_22_20			: 3;
-		uint32_t update_system			: 1;
-		uint32_t reserved_30_24			: 7;
-		uint32_t update_wake_mask		: 1;
+		uint32_t cluster_state			: U(3);
+		uint32_t reserved_6_3			: U(4);
+		uint32_t update_cluster			: U(1);
+		uint32_t cg_cstate			: U(3);
+		uint32_t reserved_14_11			: U(4);
+		uint32_t update_cg			: U(1);
+		uint32_t system_cstate			: U(4);
+		uint32_t reserved_22_20			: U(3);
+		uint32_t update_system			: U(1);
+		uint32_t reserved_30_24			: U(7);
+		uint32_t update_wake_mask		: U(1);
 		union {
-			uint32_t flat				: 32;
+			uint32_t flat			: U(32);
 			struct {
-				uint32_t vfiq			: 1;
-				uint32_t virq			: 1;
-				uint32_t fiq			: 1;
-				uint32_t irq			: 1;
-				uint32_t serror			: 1;
-				uint32_t reserved_10_5	: 6;
-				uint32_t fiqout			: 1;
-				uint32_t irqout			: 1;
-				uint32_t reserved_31_13	: 19;
+				uint32_t vfiq		: U(1);
+				uint32_t virq		: U(1);
+				uint32_t fiq		: U(1);
+				uint32_t irq		: U(1);
+				uint32_t serror		: U(1);
+				uint32_t reserved_10_5	: U(6);
+				uint32_t fiqout		: U(1);
+				uint32_t irqout		: U(1);
+				uint32_t reserved_31_13	: U(19);
 			} carmel;
 		} wake_mask;
 	} bits;
@@ -242,183 +243,182 @@
 typedef union {
 	uint64_t flat;
 	struct nvg_lower_bound_channel_t {
-		uint32_t crossover_value : 32;
-		uint32_t reserved_63_32	: 32;
+		uint32_t crossover_value	: U(32);
+		uint32_t reserved_63_32		: U(32);
 	} bits;
 } nvg_lower_bound_channel_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_cstate_stat_query_channel_t {
-		uint32_t unit_id	: 4;
-		uint32_t reserved_15_4	: 12;
-		uint32_t stat_id	: 16;
-		uint32_t reserved_63_32	: 32;
+		uint32_t unit_id		: U(4);
+		uint32_t reserved_15_4		: U(12);
+		uint32_t stat_id		: U(16);
+		uint32_t reserved_63_32		: U(32);
 	} bits;
 } nvg_cstate_stat_query_channel_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_num_cores_channel_t {
-		uint32_t num_cores		: 4;
-		uint32_t reserved_31_4	: 28;
-		uint32_t reserved_63_32 : 32;
+		uint32_t num_cores		: U(4);
+		uint32_t reserved_31_4		: U(28);
+		uint32_t reserved_63_32		: U(32);
 	} bits;
 } nvg_num_cores_channel_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_unique_logical_id_channel_t {
-		uint32_t unique_core_id	: 3;
-		uint32_t reserved_31_3	: 29;
-		uint32_t reserved_63_32 : 32;
+		uint32_t unique_core_id		: U(3);
+		uint32_t reserved_31_3		: U(29);
+		uint32_t reserved_63_32		: U(32);
 	} bits;
 } nvg_unique_logical_id_channel_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_logical_to_physical_mappings_channel_t {
-		uint32_t lcore0_pcore_id	: 4;
-		uint32_t lcore1_pcore_id	: 4;
-		uint32_t lcore2_pcore_id	: 4;
-		uint32_t lcore3_pcore_id	: 4;
-		uint32_t lcore4_pcore_id	: 4;
-		uint32_t lcore5_pcore_id	: 4;
-		uint32_t lcore6_pcore_id	: 4;
-		uint32_t lcore7_pcore_id	: 4;
-		uint32_t reserved_63_32		: 32;
+		uint32_t lcore0_pcore_id	: U(4);
+		uint32_t lcore1_pcore_id	: U(4);
+		uint32_t lcore2_pcore_id	: U(4);
+		uint32_t lcore3_pcore_id	: U(4);
+		uint32_t lcore4_pcore_id	: U(4);
+		uint32_t lcore5_pcore_id	: U(4);
+		uint32_t lcore6_pcore_id	: U(4);
+		uint32_t lcore7_pcore_id	: U(4);
+		uint32_t reserved_63_32		: U(32);
 	} bits;
 } nvg_logical_to_physical_mappings_channel_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_logical_to_mpidr_channel_write_t {
-		uint32_t lcore_id		: 3;
-		uint32_t reserved_31_3	: 29;
-		uint32_t reserved_63_32	: 32;
+		uint32_t lcore_id		: U(3);
+		uint32_t reserved_31_3		: U(29);
+		uint32_t reserved_63_32		: U(32);
 	} write;
 	struct nvg_logical_to_mpidr_channel_read_t {
-		uint32_t mpidr			: 32;
-		uint32_t reserved_63_32	: 32;
+		uint32_t mpidr			: U(32);
+		uint32_t reserved_63_32		: U(32);
 	} read;
 } nvg_logical_to_mpidr_channel_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_is_sc7_allowed_channel_t {
-		uint32_t is_sc7_allowed	: 1;
-		uint32_t reserved_31_1	: 31;
-		uint32_t reserved_63_32	: 32;
+		uint32_t is_sc7_allowed		: U(1);
+		uint32_t reserved_31_1		: U(31);
+		uint32_t reserved_63_32		: U(32);
 	} bits;
 } nvg_is_sc7_allowed_channel_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_core_online_channel_t {
-		uint32_t core_id	: 4;
-		uint32_t reserved_31_4	: 28;
-		uint32_t reserved_63_32	: 32;
+		uint32_t core_id		: U(4);
+		uint32_t reserved_31_4		: U(28);
+		uint32_t reserved_63_32		: U(32);
 	} bits;
 } nvg_core_online_channel_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_cc3_control_channel_t {
-		uint32_t freq_req	: 9;
-		uint32_t reserved_30_9	: 22;
-		uint32_t enable		: 1;
-		uint32_t reserved_63_32	: 32;
+		uint32_t freq_req		: U(9);
+		uint32_t reserved_30_9		: U(22);
+		uint32_t enable			: U(1);
+		uint32_t reserved_63_32		: U(32);
 	} bits;
 } nvg_cc3_control_channel_t;
 
 typedef enum {
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL			=	0,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC			=	1,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1			=	2,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2			=	3,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA			=	4,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB			=	5,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP			=	6,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_APE			=	7,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE			=	8,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE			=	9,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_APR			=	10,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM			=	11,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC		=	12,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE		=	13,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE		=	14,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7			=	15,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE		=	16,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE			=	17,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP		=	18,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1			=	19,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP		=	20,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7			=	21,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP	=	22,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW		=	23,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST		=	24,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB			=	25,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_CV				=	26,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2			=	27,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW		=	28,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES		=	29,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_30				=	30,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_31				=	31,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM			=	32,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK			=	33,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS			=	34,
-	TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR			=	35,
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL		=	U(0),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC		=	U(1),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1		=	U(2),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2		=	U(3),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA		=	U(4),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB		=	U(5),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP		=	U(6),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_APE		=	U(7),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE		=	U(8),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE		=	U(9),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_APR		=	U(10),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM		=	U(11),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC	=	U(12),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE	=	U(13),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE	=	U(14),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7		=	U(15),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE	=	U(16),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE		=	U(17),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP	=	U(18),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1		=	U(19),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP	=	U(20),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7		=	U(21),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP =	U(22),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW	=	U(23),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST	=	U(24),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB		=	U(25),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_CV			=	U(26),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2		=	U(27),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW	=	U(28),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES	=	U(29),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_30			=	U(30),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_31			=	U(31),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM		=	U(32),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK		=	U(33),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS		=	U(34),
+	TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR		=	U(35),
 	TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX
 } tegra_nvg_channel_update_gsc_gsc_enum_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_update_ccplex_gsc_channel_t {
-		uint32_t gsc_enum	: 16;
-		uint32_t reserved_31_16	: 16;
-		uint32_t reserved_63_32	: 32;
+		uint32_t gsc_enum	: U(16);
+		uint32_t reserved_31_16 : U(16);
+		uint32_t reserved_63_32 : U(32);
 	} bits;
 } nvg_update_ccplex_gsc_channel_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_security_config_channel_t {
-		uint32_t strict_checking_enabled : 1;
-		uint32_t strict_checking_locked	: 1;
-		uint32_t reserved_31_2		: 30;
-		uint32_t reserved_63_32		: 32;
+		uint32_t strict_checking_enabled	: U(1);
+		uint32_t strict_checking_locked		: U(1);
+		uint32_t reserved_31_2			: U(30);
+		uint32_t reserved_63_32			: U(32);
 	} bits;
 } nvg_security_config_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_shutdown_channel_t {
-		uint32_t reboot		: 1;
-		uint32_t reserved_31_1	: 31;
-		uint32_t reserved_63_32	: 32;
+		uint32_t reboot				: U(1);
+		uint32_t reserved_31_1			: U(31);
+		uint32_t reserved_63_32			: U(32);
 	} bits;
 } nvg_shutdown_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_debug_config_channel_t {
-		uint32_t enter_debug_state_on_mca : 1;
-		uint32_t reserved_31_1            : 31;
-		uint32_t reserved_63_32           : 32;
+		uint32_t enter_debug_state_on_mca	: U(1);
+		uint32_t reserved_31_1			: U(31);
+		uint32_t reserved_63_32			: U(32);
 	} bits;
 } nvg_debug_config_t;
 
 typedef union {
 	uint64_t flat;
 	struct nvg_hsm_error_ctrl_channel_t {
-		uint32_t uncorr			: 1;
-		uint32_t corr			: 1;
-		uint32_t reserved_31_2	: 30;
-		uint32_t reserved_63_32	: 32;
+		uint32_t uncorr				: U(1);
+		uint32_t corr				: U(1);
+		uint32_t reserved_31_2			: U(30);
+		uint32_t reserved_63_32			: U(32);
 	} bits;
 } nvg_hsm_error_ctrl_channel_t;
 
 extern nvg_debug_config_t nvg_debug_config;
 
-#endif
-
+#endif /* T194_NVG_H */
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
index 1012cdf..ef740a1 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
@@ -15,8 +15,8 @@
 #include <t194_nvg.h>
 #include <tegra_private.h>
 
-#define	ID_AFR0_EL1_CACHE_OPS_SHIFT	12
-#define	ID_AFR0_EL1_CACHE_OPS_MASK	0xFU
+#define	ID_AFR0_EL1_CACHE_OPS_SHIFT	U(12)
+#define	ID_AFR0_EL1_CACHE_OPS_MASK	U(0xF)
 /*
  * Reports the major and minor version of this interface.
  *
@@ -209,7 +209,7 @@
 	uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET |
 				     STRICT_CHECKING_LOCKED_SET);
 
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
+	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
 }
 #endif
 
@@ -221,7 +221,8 @@
 void nvg_system_reboot(void)
 {
 	/* issue command for reboot */
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_SHUTDOWN, TEGRA_NVG_REBOOT);
+	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SHUTDOWN,
+			     (uint64_t)TEGRA_NVG_REBOOT);
 }
 
 /*
@@ -232,5 +233,6 @@
 void nvg_system_shutdown(void)
 {
 	/* issue command for shutdown */
-	nvg_set_request_data(TEGRA_NVG_CHANNEL_SHUTDOWN, TEGRA_NVG_SHUTDOWN);
+	nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_SHUTDOWN,
+			     (uint64_t)TEGRA_NVG_SHUTDOWN);
 }
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
index 3a2e959..a3b3389 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/se/se.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
@@ -15,6 +15,7 @@
 #include <drivers/delay_timer.h>
 #include <lib/mmio.h>
 #include <lib/psci/psci.h>
+#include <se.h>
 #include <tegra_platform.h>
 
 #include "se_private.h"
@@ -54,7 +55,7 @@
 	 */
 	do {
 		val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
-		se_is_busy = !!(val & CTX_SAVE_AUTO_SE_BUSY);
+		se_is_busy = ((val & CTX_SAVE_AUTO_SE_BUSY) != 0U);
 
 		/* sleep until SE finishes */
 		if (se_is_busy) {
@@ -186,7 +187,8 @@
 	assert(tegra_bpmp_ipc_init() == 0);
 
 	/* Enable SE clock before SE context save */
-	tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+	ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+	assert(ret == 0);
 
 	/* save SE registers */
 	se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT);
@@ -201,7 +203,8 @@
 	}
 
 	/* Disable SE clock after SE context save */
-	tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+	ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+	assert(ret == 0);
 
 	return ret;
 }
@@ -211,11 +214,14 @@
  */
 void tegra_se_resume(void)
 {
+	int32_t ret = 0;
+
 	/* initialise communication channel with BPMP */
 	assert(tegra_bpmp_ipc_init() == 0);
 
 	/* Enable SE clock before SE context restore */
-	tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+	ret = tegra_bpmp_ipc_enable_clock(TEGRA_CLK_SE);
+	assert(ret == 0);
 
 	/*
 	 * When TZ takes over after System Resume, TZ should first reconfigure
@@ -229,5 +235,6 @@
 	mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
 
 	/* Disable SE clock after SE context restore */
-	tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+	ret = tegra_bpmp_ipc_disable_clock(TEGRA_CLK_SE);
+	assert(ret == 0);
 }
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
index a2c5d1c..577217b 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se_private.h
@@ -74,12 +74,12 @@
 
 static inline uint32_t tegra_se_read_32(uint32_t offset)
 {
-	return mmio_read_32(TEGRA_SE0_BASE + offset);
+	return mmio_read_32((uint32_t)(TEGRA_SE0_BASE + offset));
 }
 
 static inline void tegra_se_write_32(uint32_t offset, uint32_t val)
 {
-	mmio_write_32(TEGRA_SE0_BASE + offset, val);
+	mmio_write_32((uint32_t)(TEGRA_SE0_BASE + offset), val);
 }
 
 #endif /* SE_PRIVATE_H */
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index cc8be12..144e418 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -44,14 +44,6 @@
 	uint32_t wake_time;
 } __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT];
 
-/*
- * tegra_fake_system_suspend acts as a boolean var controlling whether
- * we are going to take fake system suspend code or normal system suspend code
- * path. This variable is set inside the sip call handlers, when the kernel
- * requests an SIP call to set the suspend debug flags.
- */
-bool tegra_fake_system_suspend;
-
 int32_t tegra_soc_validate_power_state(uint32_t power_state,
 					psci_power_state_t *req_state)
 {
@@ -171,30 +163,27 @@
 			assert(ret == 0);
 		}
 
-		if (!tegra_fake_system_suspend) {
-
-			/* Prepare for system suspend */
-			mce_update_cstate_info(&sc7_cstate_info);
+		/* Prepare for system suspend */
+		mce_update_cstate_info(&sc7_cstate_info);
 
-			do {
-				val = (uint32_t)mce_command_handler(
-						(uint32_t)MCE_CMD_IS_SC7_ALLOWED,
-						(uint32_t)TEGRA_NVG_CORE_C7,
-						MCE_CORE_SLEEP_TIME_INFINITE,
-						0U);
-			} while (val == 0U);
-
-			/* Instruct the MCE to enter system suspend state */
-			ret = mce_command_handler(
-					(uint64_t)MCE_CMD_ENTER_CSTATE,
-					(uint64_t)TEGRA_NVG_CORE_C7,
+		do {
+			val = (uint32_t)mce_command_handler(
+					(uint32_t)MCE_CMD_IS_SC7_ALLOWED,
+					(uint32_t)TEGRA_NVG_CORE_C7,
 					MCE_CORE_SLEEP_TIME_INFINITE,
 					0U);
-			assert(ret == 0);
+		} while (val == 0U);
 
-			/* set system suspend state for house-keeping */
-			tegra194_set_system_suspend_entry();
-		}
+		/* Instruct the MCE to enter system suspend state */
+		ret = mce_command_handler(
+				(uint64_t)MCE_CMD_ENTER_CSTATE,
+				(uint64_t)TEGRA_NVG_CORE_C7,
+				MCE_CORE_SLEEP_TIME_INFINITE,
+				0U);
+		assert(ret == 0);
+
+		/* set system suspend state for house-keeping */
+		tegra194_set_system_suspend_entry();
 	} else {
 		; /* do nothing */
 	}
@@ -301,7 +290,6 @@
 	uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
 		TEGRA194_STATE_ID_MASK;
 	uint64_t val;
-	u_register_t ns_sctlr_el1;
 
 	if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
 		/*
@@ -313,35 +301,16 @@
 		      tegra194_get_cpu_reset_handler_size();
 		memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
 		       (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE);
-
-		/*
-		 * In fake suspend mode, ensure that the loopback procedure
-		 * towards system suspend exit is started, instead of calling
-		 * WFI. This is done by disabling both MMU's of EL1 & El3
-		 * and calling tegra_secure_entrypoint().
-		 */
-		if (tegra_fake_system_suspend) {
-
-			/*
-			 * Disable EL1's MMU.
-			 */
-			ns_sctlr_el1 = read_sctlr_el1();
-			ns_sctlr_el1 &= (~((u_register_t)SCTLR_M_BIT));
-			write_sctlr_el1(ns_sctlr_el1);
-
-			/*
-			 * Disable MMU to power up the CPU in a "clean"
-			 * state
-			 */
-			disable_mmu_el3();
-			tegra_secure_entrypoint();
-			panic();
-		}
 	}
 
 	return PSCI_E_SUCCESS;
 }
 
+int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
+{
+	return PSCI_E_NOT_SUPPORTED;
+}
+
 int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
 {
 	uint64_t target_cpu = mpidr & MPIDR_CPU_MASK;
diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
index 8873358..33694a1 100644
--- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,12 +18,9 @@
 #include <tegra_platform.h>
 #include <stdbool.h>
 
-extern bool tegra_fake_system_suspend;
-
 /*******************************************************************************
  * Tegra194 SiP SMCs
  ******************************************************************************/
-#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND		0xC2FFFE03U
 
 /*******************************************************************************
  * This function is responsible for handling all T194 SiP calls
@@ -39,25 +36,11 @@
 {
 	int32_t ret = -ENOTSUP;
 
+	(void)smc_fid;
 	(void)x1;
 	(void)x4;
 	(void)cookie;
 	(void)flags;
 
-	if (smc_fid == TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND) {
-		/*
-		 * System suspend mode is set if the platform ATF is
-		 * running on VDK and there is a debug SIP call. This mode
-		 * ensures that the debug path is exercised, instead of
-		 * regular code path to suit the pre-silicon platform needs.
-		 * This includes replacing the call to WFI, with calls to
-		 * system suspend exit procedures.
-		 */
-		if (tegra_platform_is_virt_dev_kit()) {
-			tegra_fake_system_suspend = true;
-			ret = 0;
-		}
-	}
-
 	return ret;
 }
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index 1e49e51..78766fc 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -5,7 +5,7 @@
 #
 
 # platform configs
-ENABLE_CONSOLE_SPE			:= 0
+ENABLE_CONSOLE_SPE			:= 1
 $(eval $(call add_define,ENABLE_CONSOLE_SPE))
 
 ENABLE_STRICT_CHECKING_MODE		:= 1
diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index 12241c2..4ef9558 100644
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -184,6 +185,12 @@
 	return target;
 }
 
+int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
+{
+	(void)cpu_state;
+	return PSCI_E_SUCCESS;
+}
+
 int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
 {
 	u_register_t mpidr = read_mpidr();
@@ -412,6 +419,11 @@
 	return PSCI_E_SUCCESS;
 }
 
+int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
+{
+	return PSCI_E_NOT_SUPPORTED;
+}
+
 int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
 {
 	const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
@@ -567,5 +579,16 @@
 	/* Wait 1 ms to make sure clock source/device logic is stabilized. */
 	mdelay(1);
 
+	/*
+	 * Program the PMC in order to restart the system.
+	 */
+	tegra_pmc_system_reset();
+
 	return PSCI_E_SUCCESS;
 }
+
+__dead2 void tegra_soc_prepare_system_off(void)
+{
+	ERROR("Tegra System Off: operation not handled.\n");
+	panic();
+}
diff --git a/plat/nvidia/tegra/soc/t210/plat_setup.c b/plat/nvidia/tegra/soc/t210/plat_setup.c
index bfa8184..da1f1b3 100644
--- a/plat/nvidia/tegra/soc/t210/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t210/plat_setup.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -141,6 +142,22 @@
 }
 
 /*******************************************************************************
+ * Return pointer to the BL31 params from previous bootloader
+ ******************************************************************************/
+struct tegra_bl31_params *plat_get_bl31_params(void)
+{
+	return NULL;
+}
+
+/*******************************************************************************
+ * Return pointer to the BL31 platform params from previous bootloader
+ ******************************************************************************/
+plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
+{
+	return NULL;
+}
+
+/*******************************************************************************
  * Handler for early platform setup
  ******************************************************************************/
 void plat_early_platform_setup(void)
@@ -168,6 +185,9 @@
 			GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
 };
 
+/*******************************************************************************
+ * Handler for late platform setup
+ ******************************************************************************/
 void plat_late_platform_setup(void)
 {
 	const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index a11aef4..4f2db53 100644
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -1,5 +1,6 @@
 #
 # Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -33,6 +34,7 @@
 				${COMMON_DIR}/drivers/bpmp/bpmp.c		\
 				${COMMON_DIR}/drivers/flowctrl/flowctrl.c	\
 				${COMMON_DIR}/drivers/memctrl/memctrl_v1.c	\
+				${COMMON_DIR}/drivers/pmc/pmc.c			\
 				${SOC_DIR}/plat_psci_handlers.c			\
 				${SOC_DIR}/plat_setup.c				\
 				${SOC_DIR}/drivers/se/security_engine.c		\
diff --git a/plat/qemu/common/aarch32/plat_helpers.S b/plat/qemu/common/aarch32/plat_helpers.S
index aebcfa7..15e860b 100644
--- a/plat/qemu/common/aarch32/plat_helpers.S
+++ b/plat/qemu/common/aarch32/plat_helpers.S
@@ -72,8 +72,14 @@
 	/* Wait until we have a go */
 poll_mailbox:
 	ldr	r1, [r2, r0]
-        cmp     r1, #0
+        cmp     r1, #PLAT_QEMU_HOLD_STATE_WAIT
         beq     1f
+
+	/* Clear the mailbox again ready for next time. */
+	mov r1, #PLAT_QEMU_HOLD_STATE_WAIT
+	str r1, [r2, r0]
+
+	/* Jump to the provided entrypoint. */
 	mov_imm	r0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
 	ldr	r1, [r0]
 	bx	r1
diff --git a/plat/qemu/common/aarch64/plat_helpers.S b/plat/qemu/common/aarch64/plat_helpers.S
index 13a5ee4..dbcdc2d 100644
--- a/plat/qemu/common/aarch64/plat_helpers.S
+++ b/plat/qemu/common/aarch64/plat_helpers.S
@@ -70,6 +70,12 @@
 poll_mailbox:
 	ldr	x1, [x2, x0]
 	cbz	x1, 1f
+
+	/* Clear the mailbox again ready for next time. */
+	mov x1, #PLAT_QEMU_HOLD_STATE_WAIT
+	str x1, [x2, x0]
+
+	/* Jump to the provided entrypoint. */
 	mov_imm	x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE
 	ldr	x1, [x0]
 	br	x1
diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index 166d245..3e289fc 100644
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c
@@ -51,7 +51,7 @@
 static void update_dt(void)
 {
 	int ret;
-	void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE;
+	void *fdt = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE;
 
 	ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE);
 	if (ret < 0) {
@@ -172,12 +172,12 @@
 		 * OP-TEE expect to receive DTB address in x2.
 		 * This will be copied into x2 by dispatcher.
 		 */
-		bl_mem_params->ep_info.args.arg3 = PLAT_QEMU_DT_BASE;
+		bl_mem_params->ep_info.args.arg3 = ARM_PRELOADED_DTB_BASE;
 #else /* case AARCH32_SP_OPTEE */
 		bl_mem_params->ep_info.args.arg0 =
 					bl_mem_params->ep_info.args.arg1;
 		bl_mem_params->ep_info.args.arg1 = 0;
-		bl_mem_params->ep_info.args.arg2 = PLAT_QEMU_DT_BASE;
+		bl_mem_params->ep_info.args.arg2 = ARM_PRELOADED_DTB_BASE;
 		bl_mem_params->ep_info.args.arg3 = 0;
 #endif
 #endif
@@ -192,8 +192,23 @@
 		pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
 #endif
 
+#if ARM_LINUX_KERNEL_AS_BL33
+		/*
+		 * According to the file ``Documentation/arm64/booting.txt`` of
+		 * the Linux kernel tree, Linux expects the physical address of
+		 * the device tree blob (DTB) in x0, while x1-x3 are reserved
+		 * for future use and must be 0.
+		 */
+		bl_mem_params->ep_info.args.arg0 =
+			(u_register_t)ARM_PRELOADED_DTB_BASE;
+		bl_mem_params->ep_info.args.arg1 = 0U;
+		bl_mem_params->ep_info.args.arg2 = 0U;
+		bl_mem_params->ep_info.args.arg3 = 0U;
+#else
 		/* BL33 expects to receive the primary CPU MPID (through r0) */
 		bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
+#endif
+
 		bl_mem_params->ep_info.spsr = qemu_get_spsr_for_bl33_entry();
 		break;
 	default:
diff --git a/plat/qemu/common/qemu_gicv2.c b/plat/qemu/common/qemu_gicv2.c
index fb56622..2c358ea 100644
--- a/plat/qemu/common/qemu_gicv2.c
+++ b/plat/qemu/common/qemu_gicv2.c
@@ -37,3 +37,8 @@
 	/* Enable the gic cpu interface */
 	gicv2_cpuif_enable();
 }
+
+void qemu_pwr_gic_off(void)
+{
+	gicv2_cpuif_disable();
+}
diff --git a/plat/qemu/common/qemu_gicv3.c b/plat/qemu/common/qemu_gicv3.c
index 28572c5..0d35446 100644
--- a/plat/qemu/common/qemu_gicv3.c
+++ b/plat/qemu/common/qemu_gicv3.c
@@ -44,3 +44,9 @@
 	gicv3_rdistif_init(plat_my_core_pos());
 	gicv3_cpuif_enable(plat_my_core_pos());
 }
+
+void qemu_pwr_gic_off(void)
+{
+	gicv3_cpuif_disable(plat_my_core_pos());
+	gicv3_rdistif_off(plat_my_core_pos());
+}
diff --git a/plat/qemu/common/qemu_pm.c b/plat/qemu/common/qemu_pm.c
index a199688..cf80009 100644
--- a/plat/qemu/common/qemu_pm.c
+++ b/plat/qemu/common/qemu_pm.c
@@ -10,10 +10,13 @@
 #include <arch_helpers.h>
 #include <common/debug.h>
 #include <lib/psci/psci.h>
+#include <lib/semihosting.h>
 #include <plat/common/platform.h>
 
 #include "qemu_private.h"
 
+#define ADP_STOPPED_APPLICATION_EXIT 0x20026
+
 /*
  * The secure entry point to be used on warm reset.
  */
@@ -149,9 +152,18 @@
  * Platform handler called when a power domain is about to be turned off. The
  * target_state encodes the power state that each level should transition to.
  ******************************************************************************/
-void qemu_pwr_domain_off(const psci_power_state_t *target_state)
+static void qemu_pwr_domain_off(const psci_power_state_t *target_state)
 {
-	assert(0);
+	qemu_pwr_gic_off();
+}
+
+void __dead2 plat_secondary_cold_boot_setup(void);
+
+static void __dead2
+qemu_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state)
+{
+	disable_mmu_el3();
+	plat_secondary_cold_boot_setup();
 }
 
 /*******************************************************************************
@@ -191,7 +203,8 @@
  ******************************************************************************/
 static void __dead2 qemu_system_off(void)
 {
-	ERROR("QEMU System Off: operation not handled.\n");
+	semihosting_exit(ADP_STOPPED_APPLICATION_EXIT, 0);
+	ERROR("QEMU System Off: semihosting call unexpectedly returned.\n");
 	panic();
 }
 
@@ -205,6 +218,7 @@
 	.cpu_standby = qemu_cpu_standby,
 	.pwr_domain_on = qemu_pwr_domain_on,
 	.pwr_domain_off = qemu_pwr_domain_off,
+	.pwr_domain_pwr_down_wfi = qemu_pwr_domain_pwr_down_wfi,
 	.pwr_domain_suspend = qemu_pwr_domain_suspend,
 	.pwr_domain_on_finish = qemu_pwr_domain_on_finish,
 	.pwr_domain_suspend_finish = qemu_pwr_domain_suspend_finish,
diff --git a/plat/qemu/common/qemu_private.h b/plat/qemu/common/qemu_private.h
index 71ea4de..4dc62f5 100644
--- a/plat/qemu/common/qemu_private.h
+++ b/plat/qemu/common/qemu_private.h
@@ -32,5 +32,6 @@
 
 void plat_qemu_gic_init(void);
 void qemu_pwr_gic_on_finish(void);
+void qemu_pwr_gic_off(void);
 
 #endif /* QEMU_PRIVATE_H */
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 5fda2cd..b95bf5a 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -151,6 +151,8 @@
 BL31_SOURCES		+=	lib/cpus/aarch64/aem_generic.S		\
 				lib/cpus/aarch64/cortex_a53.S		\
 				lib/cpus/aarch64/cortex_a57.S		\
+				lib/semihosting/semihosting.c		\
+				lib/semihosting/${ARCH}/semihosting_call.S \
 				plat/common/plat_psci_common.c		\
 				${PLAT_QEMU_COMMON_PATH}/qemu_pm.c			\
 				${PLAT_QEMU_COMMON_PATH}/topology.c			\
@@ -186,5 +188,13 @@
 # Process flags
 $(eval $(call add_define,BL32_RAM_LOCATION_ID))
 
+# Don't have the Linux kernel as a BL33 image by default
+ARM_LINUX_KERNEL_AS_BL33	:=	0
+$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
+$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
+
+ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
+$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+
 # Do not enable SVE
 ENABLE_SVE_FOR_NS	:=	0
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 0d6047d..51832d0 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -71,6 +71,8 @@
 BL31_SOURCES		+=	lib/cpus/aarch64/aem_generic.S			\
 				lib/cpus/aarch64/cortex_a53.S			\
 				lib/cpus/aarch64/cortex_a57.S			\
+				lib/semihosting/semihosting.c			\
+				lib/semihosting/${ARCH}/semihosting_call.S	\
 				plat/common/plat_psci_common.c			\
 				${PLAT_QEMU_COMMON_PATH}/qemu_pm.c		\
 				${PLAT_QEMU_COMMON_PATH}/topology.c		\
@@ -97,5 +99,13 @@
 BL32_RAM_LOCATION_ID	= SEC_SRAM_ID
 $(eval $(call add_define,BL32_RAM_LOCATION_ID))
 
+# Don't have the Linux kernel as a BL33 image by default
+ARM_LINUX_KERNEL_AS_BL33	:=	0
+$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
+$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
+
+ARM_PRELOADED_DTB_BASE := PLAT_QEMU_DT_BASE
+$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+
 # Do not enable SVE
 ENABLE_SVE_FOR_NS	:= 0
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index 193d80e..578892e 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -39,12 +39,19 @@
 #include "rcar_version.h"
 #include "rom_api.h"
 
-IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE)
-IMPORT_SYM(unsigned long, __RO_END__, BL2_RO_LIMIT)
+#if RCAR_BL2_DCACHE == 1
+/*
+ * Following symbols are only used during plat_arch_setup() only
+ * when RCAR_BL2_DCACHE is enabled.
+ */
+static const uint64_t BL2_RO_BASE		= BL_CODE_BASE;
+static const uint64_t BL2_RO_LIMIT		= BL_CODE_END;
 
 #if USE_COHERENT_MEM
-IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL2_COHERENT_RAM_BASE)
-IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL2_COHERENT_RAM_LIMIT)
+static const uint64_t BL2_COHERENT_RAM_BASE	= BL_COHERENT_RAM_BASE;
+static const uint64_t BL2_COHERENT_RAM_LIMIT	= BL_COHERENT_RAM_END;
+#endif
+
 #endif
 
 extern void plat_rcar_gic_driver_init(void);
diff --git a/plat/renesas/rcar/bl31_plat_setup.c b/plat/renesas/rcar/bl31_plat_setup.c
index bd83c41..7bc0d8e 100644
--- a/plat/renesas/rcar/bl31_plat_setup.c
+++ b/plat/renesas/rcar/bl31_plat_setup.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -22,12 +22,12 @@
 #include "rcar_private.h"
 #include "rcar_version.h"
 
-IMPORT_SYM(uint64_t, __RO_START__, BL31_RO_BASE)
-IMPORT_SYM(uint64_t, __RO_END__, BL31_RO_LIMIT)
+static const uint64_t BL31_RO_BASE		= BL_CODE_BASE;
+static const uint64_t BL31_RO_LIMIT		= BL_CODE_END;
 
 #if USE_COHERENT_MEM
-IMPORT_SYM(uint64_t, __COHERENT_RAM_START__, BL31_COHERENT_RAM_BASE)
-IMPORT_SYM(uint64_t, __COHERENT_RAM_END__, BL31_COHERENT_RAM_LIMIT)
+static const uint64_t BL31_COHERENT_RAM_BASE	= BL_COHERENT_RAM_BASE;
+static const uint64_t BL31_COHERENT_RAM_LIMIT	= BL_COHERENT_RAM_END;
 #endif
 
 extern void plat_rcar_gic_driver_init(void);
diff --git a/plat/renesas/rcar/plat_pm.c b/plat/renesas/rcar/plat_pm.c
index e678da5..6fc47b9 100644
--- a/plat/renesas/rcar/plat_pm.c
+++ b/plat/renesas/rcar/plat_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -56,7 +56,7 @@
 
 static void rcar_cpu_standby(plat_local_state_t cpu_state)
 {
-	uint32_t scr_el3 = read_scr_el3();
+	u_register_t scr_el3 = read_scr_el3();
 
 	write_scr_el3(scr_el3 | SCR_IRQ_BIT);
 	dsb();
diff --git a/plat/rockchip/common/plat_pm.c b/plat/rockchip/common/plat_pm.c
index c9563c9..6926887 100644
--- a/plat/rockchip/common/plat_pm.c
+++ b/plat/rockchip/common/plat_pm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -182,7 +182,7 @@
  ******************************************************************************/
 void rockchip_cpu_standby(plat_local_state_t cpu_state)
 {
-	unsigned int scr;
+	u_register_t scr;
 
 	assert(cpu_state == PLAT_MAX_RET_STATE);
 
diff --git a/plat/socionext/synquacer/sq_psci.c b/plat/socionext/synquacer/sq_psci.c
index 731b19a..0c97fcf 100644
--- a/plat/socionext/synquacer/sq_psci.c
+++ b/plat/socionext/synquacer/sq_psci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -155,7 +155,7 @@
 
 void sq_cpu_standby(plat_local_state_t cpu_state)
 {
-	unsigned int scr;
+	u_register_t scr;
 
 	assert(cpu_state == SQ_LOCAL_STATE_RET);
 
diff --git a/plat/st/stm32mp1/include/stm32mp1_boot_device.h b/plat/st/stm32mp1/include/stm32mp1_boot_device.h
deleted file mode 100644
index a745983..0000000
--- a/plat/st/stm32mp1/include/stm32mp1_boot_device.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef STM32MP1_BOOT_DEVICE_H
-#define STM32MP1_BOOT_DEVICE_H
-
-#include <drivers/raw_nand.h>
-#include <drivers/spi_nand.h>
-#include <drivers/spi_nor.h>
-
-int plat_get_raw_nand_data(struct rawnand_device *device);
-int plat_get_spi_nand_data(struct spinand_device *device);
-int plat_get_nor_data(struct nor_device *device);
-
-#endif /* STM32MP1_BOOT_DEVICE_H */
diff --git a/plat/st/stm32mp1/stm32mp1_boot_device.c b/plat/st/stm32mp1/stm32mp1_boot_device.c
index 2d8eccf..997335d 100644
--- a/plat/st/stm32mp1/stm32mp1_boot_device.c
+++ b/plat/st/stm32mp1/stm32mp1_boot_device.c
@@ -7,6 +7,9 @@
 #include <errno.h>
 
 #include <drivers/nand.h>
+#include <drivers/raw_nand.h>
+#include <drivers/spi_nand.h>
+#include <drivers/spi_nor.h>
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 11b01ab..5dc5206 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -23,7 +23,6 @@
 #include <stm32mp_common.h>
 #include <stm32mp_dt.h>
 #include <stm32mp_shres_helpers.h>
-#include <stm32mp1_boot_device.h>
 #include <stm32mp1_dbgmcu.h>
 #include <stm32mp1_private.h>
 #endif
diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h
index c1a5966..0d45116 100644
--- a/plat/ti/k3/board/generic/include/board_def.h
+++ b/plat/ti/k3/board/generic/include/board_def.h
@@ -27,5 +27,6 @@
 
 #define PLAT_PROC_START_ID		32
 #define PLAT_PROC_DEVICE_START_ID	202
+#define PLAT_CLUSTER_DEVICE_START_ID	198
 
 #endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
index ac33278..e390efe 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
@@ -20,32 +20,10 @@
 #include "ti_sci_protocol.h"
 #include "ti_sci.h"
 
-/**
- * struct ti_sci_desc - Description of SoC integration
- * @host_id:		Host identifier representing the compute entity
- * @max_msg_size:	Maximum size of data per message that can be handled
- */
-struct ti_sci_desc {
-	uint8_t host_id;
-	int max_msg_size;
-};
-
-/**
- * struct ti_sci_info - Structure representing a TI SCI instance
- * @desc:	SoC description for this instance
- * @seq:	Seq id used for verification for tx and rx message
- */
-struct ti_sci_info {
-	const struct ti_sci_desc desc;
-	uint8_t seq;
-};
-
-static struct ti_sci_info info = {
-	.desc = {
-		.host_id = TI_SCI_HOST_ID,
-		.max_msg_size = TI_SCI_MAX_MESSAGE_SIZE,
-	},
-};
+#if USE_COHERENT_MEM
+__section("tzfw_coherent_mem")
+#endif
+static uint8_t message_sequence;
 
 /**
  * struct ti_sci_xfer - Structure representing a message flow
@@ -82,16 +60,16 @@
 	struct ti_sci_msg_hdr *hdr;
 
 	/* Ensure we have sane transfer sizes */
-	if (rx_message_size > info.desc.max_msg_size ||
-	    tx_message_size > info.desc.max_msg_size ||
+	if (rx_message_size > TI_SCI_MAX_MESSAGE_SIZE ||
+	    tx_message_size > TI_SCI_MAX_MESSAGE_SIZE ||
 	    rx_message_size < sizeof(*hdr) ||
 	    tx_message_size < sizeof(*hdr))
 		return -ERANGE;
 
 	hdr = (struct ti_sci_msg_hdr *)tx_buf;
-	hdr->seq = ++info.seq;
+	hdr->seq = ++message_sequence;
 	hdr->type = msg_type;
-	hdr->host = info.desc.host_id;
+	hdr->host = TI_SCI_HOST_ID;
 	hdr->flags = msg_flags | TI_SCI_FLAG_REQ_ACK_ON_PROCESSED;
 
 	xfer->tx_message.buf = tx_buf;
@@ -131,7 +109,7 @@
 		hdr = (struct ti_sci_msg_hdr *)msg->buf;
 
 		/* Sanity check for message response */
-		if (hdr->seq == info.seq)
+		if (hdr->seq == message_sequence)
 			break;
 		else
 			WARN("Message with sequence ID %u is not expected\n", hdr->seq);
@@ -141,9 +119,9 @@
 		return -EINVAL;
 	}
 
-	if (msg->len > info.desc.max_msg_size) {
+	if (msg->len > TI_SCI_MAX_MESSAGE_SIZE) {
 		ERROR("Unable to handle %lu xfer (max %d)\n",
-		      msg->len, info.desc.max_msg_size);
+		      msg->len, TI_SCI_MAX_MESSAGE_SIZE);
 		return -EINVAL;
 	}
 
@@ -425,13 +403,13 @@
 	int ret;
 
 	/* Ensure we have sane transfer size */
-	if (sizeof(req) > info.desc.max_msg_size)
+	if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE)
 		return -ERANGE;
 
 	hdr = (struct ti_sci_msg_hdr *)&req;
-	hdr->seq = ++info.seq;
+	hdr->seq = ++message_sequence;
 	hdr->type = TI_SCI_MSG_SET_DEVICE_STATE;
-	hdr->host = info.desc.host_id;
+	hdr->host = TI_SCI_HOST_ID;
 	/* Setup with NORESPONSE flag to keep response queue clean */
 	hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE;
 
@@ -1408,13 +1386,13 @@
 	int ret;
 
 	/* Ensure we have sane transfer size */
-	if (sizeof(req) > info.desc.max_msg_size)
+	if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE)
 		return -ERANGE;
 
 	hdr = (struct ti_sci_msg_hdr *)&req;
-	hdr->seq = ++info.seq;
+	hdr->seq = ++message_sequence;
 	hdr->type = TISCI_MSG_SET_PROC_BOOT_CTRL;
-	hdr->host = info.desc.host_id;
+	hdr->host = TI_SCI_HOST_ID;
 	/* Setup with NORESPONSE flag to keep response queue clean */
 	hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE;
 
@@ -1650,13 +1628,13 @@
 	int ret;
 
 	/* Ensure we have sane transfer size */
-	if (sizeof(req) > info.desc.max_msg_size)
+	if (sizeof(req) > TI_SCI_MAX_MESSAGE_SIZE)
 		return -ERANGE;
 
 	hdr = (struct ti_sci_msg_hdr *)&req;
-	hdr->seq = ++info.seq;
+	hdr->seq = ++message_sequence;
 	hdr->type = TISCI_MSG_WAIT_PROC_BOOT_STATUS;
-	hdr->host = info.desc.host_id;
+	hdr->host = TI_SCI_HOST_ID;
 	/* Setup with NORESPONSE flag to keep response queue clean */
 	hdr->flags = TI_SCI_FLAG_REQ_GENERIC_NORESPONSE;
 
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
index a921e51..2d23f9a 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
@@ -563,8 +563,13 @@
 	uint32_t config_flags_clear;
 } __packed;
 
+/* ARMV8 Control Flags */
+#define PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM      0x00000001
+#define PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS       0x00000002
+#define PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ    0x00000100
+
 /* R5 Control Flags */
-#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT                0x00000001
+#define PROC_BOOT_CTRL_FLAG_R5_CORE_HALT        0x00000001
 
 /**
  * struct ti_sci_msg_req_set_proc_boot_ctrl - Set Processor boot control flags
@@ -618,6 +623,8 @@
 /* ARMv8 Status Flags */
 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFE			0x00000001
 #define PROC_BOOT_STATUS_FLAG_ARMV8_WFI			0x00000002
+#define PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE		0x00000010
+#define PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2	0x00000020
 
 /* R5 Status Flags */
 #define PROC_BOOT_STATUS_FLAG_R5_WFE			0x00000001
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index de9cefe..d6ed766 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,11 +17,15 @@
 #include <k3_gicv3.h>
 #include <ti_sci.h>
 
+#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
+#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1])
+#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
+
 uintptr_t k3_sec_entrypoint;
 
 static void k3_cpu_standby(plat_local_state_t cpu_state)
 {
-	unsigned int scr;
+	u_register_t scr;
 
 	scr = read_scr_el3();
 	/* Enable the Non secure interrupt to wake the CPU */
@@ -37,30 +41,40 @@
 
 static int k3_pwr_domain_on(u_register_t mpidr)
 {
-	int core_id, proc, device, ret;
+	int core, proc_id, device_id, ret;
 
-	core_id = plat_core_pos_by_mpidr(mpidr);
-	if (core_id < 0) {
-		ERROR("Could not get target core id: %d\n", core_id);
+	core = plat_core_pos_by_mpidr(mpidr);
+	if (core < 0) {
+		ERROR("Could not get target core id: %d\n", core);
 		return PSCI_E_INTERN_FAIL;
 	}
 
-	proc = PLAT_PROC_START_ID + core_id;
-	device = PLAT_PROC_DEVICE_START_ID + core_id;
+	proc_id = PLAT_PROC_START_ID + core;
+	device_id = PLAT_PROC_DEVICE_START_ID + core;
 
-	ret = ti_sci_proc_request(proc);
+	ret = ti_sci_proc_request(proc_id);
 	if (ret) {
 		ERROR("Request for processor failed: %d\n", ret);
 		return PSCI_E_INTERN_FAIL;
 	}
 
-	ret = ti_sci_proc_set_boot_cfg(proc, k3_sec_entrypoint, 0, 0);
+	ret = ti_sci_proc_set_boot_cfg(proc_id, k3_sec_entrypoint, 0, 0);
 	if (ret) {
 		ERROR("Request to set core boot address failed: %d\n", ret);
 		return PSCI_E_INTERN_FAIL;
 	}
 
+	/* sanity check these are off before starting a core */
+	ret = ti_sci_proc_set_boot_ctrl(proc_id,
+			0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ |
+			   PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS |
+			   PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM);
+	if (ret) {
+		ERROR("Request to clear boot configuration failed: %d\n", ret);
+		return PSCI_E_INTERN_FAIL;
+	}
+
-	ret = ti_sci_device_get(device);
+	ret = ti_sci_device_get(device_id);
 	if (ret) {
 		ERROR("Request to start core failed: %d\n", ret);
 		return PSCI_E_INTERN_FAIL;
@@ -71,17 +85,35 @@
 
 void k3_pwr_domain_off(const psci_power_state_t *target_state)
 {
-	int core_id, proc, device, ret;
+	int core, cluster, proc_id, device_id, cluster_id, ret;
+
+	/* At very least the local core should be powering down */
+	assert(CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE);
 
 	/* Prevent interrupts from spuriously waking up this cpu */
 	k3_gic_cpuif_disable();
 
-	core_id = plat_my_core_pos();
-	proc = PLAT_PROC_START_ID + core_id;
-	device = PLAT_PROC_DEVICE_START_ID + core_id;
+	core = plat_my_core_pos();
+	cluster = MPIDR_AFFLVL1_VAL(read_mpidr_el1());
+	proc_id = PLAT_PROC_START_ID + core;
+	device_id = PLAT_PROC_DEVICE_START_ID + core;
+	cluster_id = PLAT_CLUSTER_DEVICE_START_ID + (cluster * 2);
+
+	/*
+	 * If we are the last core in the cluster then we take a reference to
+	 * the cluster device so that it does not get shutdown before we
+	 * execute the entire cluster L2 cleaning sequence below.
+	 */
+	if (CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) {
+		ret = ti_sci_device_get(cluster_id);
+		if (ret) {
+			ERROR("Request to get cluster failed: %d\n", ret);
+			return;
+		}
+	}
 
 	/* Start by sending wait for WFI command */
-	ret = ti_sci_proc_wait_boot_status_no_wait(proc,
+	ret = ti_sci_proc_wait_boot_status_no_wait(proc_id,
 			/*
 			 * Wait maximum time to give us the best chance to get
 			 * to WFI before this command timeouts
@@ -95,11 +127,72 @@
 	}
 
 	/* Now queue up the core shutdown request */
-	ret = ti_sci_device_put_no_wait(device);
+	ret = ti_sci_device_put_no_wait(device_id);
 	if (ret) {
 		ERROR("Sending core shutdown message failed (%d)\n", ret);
 		return;
 	}
+
+	/* If our cluster is not going down we stop here */
+	if (CLUSTER_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE)
+		return;
+
+	/* set AINACTS */
+	ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
+			PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS, 0);
+	if (ret) {
+		ERROR("Sending set control message failed (%d)\n", ret);
+		return;
+	}
+
+	/* set L2FLUSHREQ */
+	ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
+			PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ, 0);
+	if (ret) {
+		ERROR("Sending set control message failed (%d)\n", ret);
+		return;
+	}
+
+	/* wait for L2FLUSHDONE*/
+	ret = ti_sci_proc_wait_boot_status_no_wait(proc_id,
+			UINT8_MAX, 2, UINT8_MAX, UINT8_MAX,
+			PROC_BOOT_STATUS_FLAG_ARMV8_L2F_DONE, 0, 0, 0);
+	if (ret) {
+		ERROR("Sending wait message failed (%d)\n", ret);
+		return;
+	}
+
+	/* clear L2FLUSHREQ */
+	ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
+			0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ);
+	if (ret) {
+		ERROR("Sending set control message failed (%d)\n", ret);
+		return;
+	}
+
+	/* set ACINACTM */
+	ret = ti_sci_proc_set_boot_ctrl_no_wait(proc_id,
+			PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM, 0);
+	if (ret) {
+		ERROR("Sending set control message failed (%d)\n", ret);
+		return;
+	}
+
+	/* wait for STANDBYWFIL2 */
+	ret = ti_sci_proc_wait_boot_status_no_wait(proc_id,
+			UINT8_MAX, 2, UINT8_MAX, UINT8_MAX,
+			PROC_BOOT_STATUS_FLAG_ARMV8_STANDBYWFIL2, 0, 0, 0);
+	if (ret) {
+		ERROR("Sending wait message failed (%d)\n", ret);
+		return;
+	}
+
+	/* Now queue up the cluster shutdown request */
+	ret = ti_sci_device_put_no_wait(cluster_id);
+	if (ret) {
+		ERROR("Sending cluster shutdown message failed (%d)\n", ret);
+		return;
+	}
 }
 
 void k3_pwr_domain_on_finish(const psci_power_state_t *target_state)
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index c03629a..eff929e 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -10,53 +10,41 @@
 DEBUG		:= 0
 BINARY		:= ${PROJECT}${BIN_EXT}
 OPENSSL_DIR	:= /usr
-USE_TBBR_DEFS   := 1
+COT		:= tbbr
 
+MAKE_HELPERS_DIRECTORY := ../../make_helpers/
+include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
+include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+
+# Common source files.
 OBJECTS := src/cert.o \
            src/cmd_opt.o \
            src/ext.o \
            src/key.o \
            src/main.o \
-           src/sha.o \
-           src/tbbr/tbb_cert.o \
-           src/tbbr/tbb_ext.o \
-           src/tbbr/tbb_key.o
+           src/sha.o
 
-HOSTCCFLAGS := -Wall -std=c99
-
-MAKE_HELPERS_DIRECTORY := ../../make_helpers/
-include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
-include ${MAKE_HELPERS_DIRECTORY}build_env.mk
-
-ifeq (${USE_TBBR_DEFS},1)
-# In this case, cert_tool is platform-independent
-PLAT_MSG		:=	TBBR Generic
-PLAT_INCLUDE		:=	../../include/tools_share
+# Chain of trust.
+ifeq (${COT},tbbr)
+  include src/tbbr/tbbr.mk
 else
-PLAT_MSG		:=	${PLAT}
-
-TF_PLATFORM_ROOT		:=	../../plat/
-include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
-
-PLAT_INCLUDE		:=	$(wildcard ${PLAT_DIR}include)
-
-ifeq ($(PLAT_INCLUDE),)
-  $(error "Error: Invalid platform '${PLAT}' has no include directory.")
+  $(error Unknown chain of trust ${COT})
 endif
-endif
+
+HOSTCCFLAGS := -Wall -std=c99
 
 ifeq (${DEBUG},1)
   HOSTCCFLAGS += -g -O0 -DDEBUG -DLOG_LEVEL=40
 else
   HOSTCCFLAGS += -O2 -DLOG_LEVEL=20
 endif
+
 ifeq (${V},0)
   Q := @
 else
   Q :=
 endif
 
-$(eval $(call add_define,USE_TBBR_DEFS))
 HOSTCCFLAGS += ${DEFINES}
 
 # Make soft links and include from local directory otherwise wrong headers
diff --git a/tools/cert_create/src/ext.c b/tools/cert_create/src/ext.c
index 57fb47d..d9a92bb 100644
--- a/tools/cert_create/src/ext.c
+++ b/tools/cert_create/src/ext.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -33,11 +33,11 @@
 IMPLEMENT_ASN1_FUNCTIONS(HASH)
 
 /*
- * This function adds the TBB extensions to the internal extension list
+ * This function adds the CoT extensions to the internal extension list
  * maintained by OpenSSL so they can be used later.
  *
  * It also initializes the methods to print the contents of the extension. If an
- * alias is specified in the TBB extension, we reuse the methods of the alias.
+ * alias is specified in the CoT extension, we reuse the methods of the alias.
  * Otherwise, only methods for V_ASN1_INTEGER and V_ASN1_OCTET_STRING are
  * provided. Any other type will be printed as a raw ascii string.
  *
diff --git a/tools/cert_create/src/main.c b/tools/cert_create/src/main.c
index 863db7b..2ba1101 100644
--- a/tools/cert_create/src/main.c
+++ b/tools/cert_create/src/main.c
@@ -47,7 +47,7 @@
 	do { \
 		v = OBJ_txt2nid(oid); \
 		if (v == NID_undef) { \
-			ERROR("Cannot find TBB extension %s\n", oid); \
+			ERROR("Cannot find extension %s\n", oid); \
 			exit(1); \
 		} \
 	} while (0)
@@ -335,7 +335,7 @@
 
 	/* Initialize the new types and register OIDs for the extensions */
 	if (ext_init() != 0) {
-		ERROR("Cannot initialize TBB extensions\n");
+		ERROR("Cannot initialize extensions\n");
 		exit(1);
 	}
 
diff --git a/tools/cert_create/src/tbbr/tbbr.mk b/tools/cert_create/src/tbbr/tbbr.mk
new file mode 100644
index 0000000..ee82d31
--- /dev/null
+++ b/tools/cert_create/src/tbbr/tbbr.mk
@@ -0,0 +1,29 @@
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+USE_TBBR_DEFS   := 1
+$(eval $(call add_define,USE_TBBR_DEFS))
+
+ifeq (${USE_TBBR_DEFS},1)
+# In this case, cert_tool is platform-independent
+PLAT_MSG		:=	TBBR Generic
+PLAT_INCLUDE		:=	../../include/tools_share
+else
+PLAT_MSG		:=	${PLAT}
+
+TF_PLATFORM_ROOT	:=	../../plat/
+include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
+
+PLAT_INCLUDE		:=	$(wildcard ${PLAT_DIR}include)
+
+ifeq ($(PLAT_INCLUDE),)
+  $(error "Error: Invalid platform '${PLAT}' has no include directory.")
+endif
+endif
+
+OBJECTS += src/tbbr/tbb_cert.o \
+           src/tbbr/tbb_ext.o \
+           src/tbbr/tbb_key.o