tree 42053eaf84e75860390c2945e368bfac899f6094
parent b1997a7ca6e0fceaaf6eda5d977403e25446a14a
author Peng Fan <peng.fan@nxp.com> 1716877674 +0800
committer Peng Fan <peng.fan@nxp.com> 1723528494 +0200

fix(gicv3): wait rwp when gicr_ctrl.enablelpis from 1 to 0

Per GIC architecture version 3 and version 4, Where the GICR_CTRL.EnableLPIs
remains programmable:
- Software must observe GICR_CTLR.RWP==0 after clearing GICR_CTLR.EnableLPIs
  from 1 to 0 before writing GICR_PENDBASER or GICR_PROPBASER, otherwise
  behavior is UNPREDICTABLE.
- Software must observe GICR_CTLR.RWP==0 after clearing GICR_CTLR.EnableLPIs
  from 1 to 0 before setting GICR_CTLR.EnableLPIs to 1, otherwise behavior is
  UNPREDICTABLE.

After changing EnableLPIs from 1 to 0, wait RWP got cleared, otherwise
setting EnableLPIs from 0 to 1 may fail.

Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Tested-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I6aaf96dc9984376de9399d0dac8a8504ba095149