feat(intel): clock manager PLL configuration for Agilex5 platform
Read the hand-off data and configure the clock manager main
and peripheral PLL and few other misc updates.
Change-Id: I3c5cbaf7a677a022ef24b0e679860e6ee195f16a
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
diff --git a/plat/intel/soc/agilex5/bl2_plat_setup.c b/plat/intel/soc/agilex5/bl2_plat_setup.c
index 6d0f183..78a4889 100644
--- a/plat/intel/soc/agilex5/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl2_plat_setup.c
@@ -145,7 +145,8 @@
handoff reverse_handoff_ptr;
unsigned long offset = 0;
- struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc, get_mmc_clk());
+ struct cdns_sdmmc_params params = EMMC_INIT_PARAMS((uintptr_t) &cdns_desc,
+ clkmgr_get_rate(CLKMGR_SDMMC_CLK_ID));
mmc_info.mmc_dev_type = MMC_DEVICE_TYPE;
mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;