Merge "plat: imx: imx8qx: provide debug uart num as build param" into integration
diff --git a/Makefile b/Makefile
index 47a544d..ac461a5 100644
--- a/Makefile
+++ b/Makefile
@@ -84,26 +84,6 @@
export Q ECHO
-# Process Debug flag
-$(eval $(call add_define,DEBUG))
-ifneq (${DEBUG}, 0)
- BUILD_TYPE := debug
- TF_CFLAGS += -g
-
- ifneq ($(findstring clang,$(notdir $(CC))),)
- ASFLAGS += -g
- else
- ASFLAGS += -g -Wa,--gdwarf-2
- endif
-
- # Use LOG_LEVEL_INFO by default for debug builds
- LOG_LEVEL := 40
-else
- BUILD_TYPE := release
- # Use LOG_LEVEL_NOTICE by default for release builds
- LOG_LEVEL := 20
-endif
-
# Default build string (git branch and commit)
ifeq (${BUILD_STRING},)
BUILD_STRING := $(shell git describe --always --dirty --tags 2> /dev/null)
@@ -243,6 +223,26 @@
LD = $(LINKER)
endif
+# Process Debug flag
+$(eval $(call add_define,DEBUG))
+ifneq (${DEBUG}, 0)
+ BUILD_TYPE := debug
+ TF_CFLAGS += -g
+
+ ifneq ($(findstring clang,$(notdir $(CC))),)
+ ASFLAGS += -g
+ else
+ ASFLAGS += -g -Wa,--gdwarf-2
+ endif
+
+ # Use LOG_LEVEL_INFO by default for debug builds
+ LOG_LEVEL := 40
+else
+ BUILD_TYPE := release
+ # Use LOG_LEVEL_NOTICE by default for release builds
+ LOG_LEVEL := 20
+endif
+
ifeq (${AARCH32_INSTRUCTION_SET},A32)
TF_CFLAGS_aarch32 += -marm
else ifeq (${AARCH32_INSTRUCTION_SET},T32)
@@ -364,7 +364,12 @@
endif
DTC_FLAGS += -I dts -O dtb
-DTC_CPPFLAGS += -P -nostdinc -Iinclude -Ifdts -undef -x assembler-with-cpp
+DTC_CPPFLAGS += -P -nostdinc -Iinclude -Ifdts -undef \
+ -x assembler-with-cpp $(DEFINES)
+
+ifeq ($(MEASURED_BOOT),1)
+DTC_CPPFLAGS += -DMEASURED_BOOT -DBL2_HASH_SIZE=${TCG_DIGEST_SIZE}
+endif
################################################################################
# Common sources and include directories
@@ -503,6 +508,18 @@
endif
endif
+ifeq (${ARCH},aarch64)
+BL1_CFLAGS += -DIMAGE_AT_EL3
+ifeq ($(BL2_AT_EL3),1)
+BL2_CFLAGS += -DIMAGE_AT_EL3
+else
+BL2_CFLAGS += -DIMAGE_AT_EL1
+endif
+BL2U_CFLAGS += -DIMAGE_AT_EL1
+BL31_CFLAGS += -DIMAGE_AT_EL3
+BL32_CFLAGS += -DIMAGE_AT_EL1
+endif
+
# Include the CPU specific operations makefile, which provides default
# values for all CPU errata workarounds and CPU specific optimisations.
# This can be overridden by the platform.
@@ -826,7 +843,7 @@
$(eval $(call assert_boolean,TRUSTED_BOARD_BOOT))
$(eval $(call assert_boolean,USE_COHERENT_MEM))
$(eval $(call assert_boolean,USE_DEBUGFS))
-$(eval $(call assert_boolean,USE_FCONF_BASED_IO))
+$(eval $(call assert_boolean,ARM_IO_IN_DTB))
$(eval $(call assert_boolean,USE_ROMLIB))
$(eval $(call assert_boolean,USE_TBBR_DEFS))
$(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY))
@@ -904,7 +921,7 @@
$(eval $(call add_define,TRUSTED_BOARD_BOOT))
$(eval $(call add_define,USE_COHERENT_MEM))
$(eval $(call add_define,USE_DEBUGFS))
-$(eval $(call add_define,USE_FCONF_BASED_IO))
+$(eval $(call add_define,ARM_IO_IN_DTB))
$(eval $(call add_define,USE_ROMLIB))
$(eval $(call add_define,USE_TBBR_DEFS))
$(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY))
@@ -938,13 +955,18 @@
endif
# Generate and include sp_gen.mk if SPD is spmd and SP_LAYOUT_FILE is defined
-ifdef SP_LAYOUT_FILE
ifeq (${SPD},spmd)
+ifdef SP_LAYOUT_FILE
+ ifeq (${SPMD_SPM_AT_SEL2},0)
+ $(error "SPMD with SPM at S-EL1 does not require SP_LAYOUT_FILE")
+ endif
-include $(BUILD_PLAT)/sp_gen.mk
FIP_DEPS += sp
NEED_SP_PKG := yes
else
- $(error "SP_LAYOUT_FILE will be used only if SPD=spmd")
+ ifeq (${SPMD_SPM_AT_SEL2},1)
+ $(error "SPMD with SPM at S-EL2 require SP_LAYOUT_FILE")
+ endif
endif
endif
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S
index a90a805..66f3b11 100644
--- a/bl32/sp_min/sp_min.ld.S
+++ b/bl32/sp_min/sp_min.ld.S
@@ -56,7 +56,7 @@
KEEP(*(rt_svc_descs))
__RT_SVC_DESCS_END__ = .;
- . = ALIGN(8);
+ . = ALIGN(4);
__FCONF_POPULATOR_START__ = .;
KEEP(*(.fconf_populator))
__FCONF_POPULATOR_END__ = .;
@@ -98,7 +98,7 @@
KEEP(*(rt_svc_descs))
__RT_SVC_DESCS_END__ = .;
- . = ALIGN(8);
+ . = ALIGN(4);
__FCONF_POPULATOR_START__ = .;
KEEP(*(.fconf_populator))
__FCONF_POPULATOR_END__ = .;
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index c230e60..fb1e39b 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -40,7 +40,7 @@
+-----------------+---------------------------+------------------------------+
| v2.2 | 4th week of Oct '19 | 1st week of Oct '19 |
+-----------------+---------------------------+------------------------------+
-| v2.3 | 4th week of Mar '20 | 1st week of Mar '20 |
+| v2.3 | 4th week of Apr '20 | 1st week of Apr '20 |
+-----------------+---------------------------+------------------------------+
Removal of Deprecated Interfaces
@@ -65,4 +65,4 @@
--------------
-*Copyright (c) 2018-2019, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/change-log-upcoming.rst b/docs/change-log-upcoming.rst
index f86280f..f089a5e 100644
--- a/docs/change-log-upcoming.rst
+++ b/docs/change-log-upcoming.rst
@@ -20,15 +20,27 @@
^^^^^^^^^^^^
- Arm Architecture
+ - Add support for Armv8.4-SecEL2 extension through the SPCI defined SPMD/SPMC
+ components.
+ - Build option to support EL2 context save and restore in the secure world
+ (CTX_INCLUDE_EL2_REGS).
- Example: "Add support for Branch Target Identification (BTI)"
+- BL-specific
+ - Enhanced BL2 bootloader flow to load secure partitions based on firmware
+ configuration data (fconf).
+
- Build System
- Add support for documentation build as a target in Makefile
- Add ``COT`` build option to select the chain of trust to use when the
Trusted Boot feature is enabled (default: ``tbbr``).
+ - Added creation and injection of secure partition packages into the FIP.
+ - Build option to support SPMC component loading and run at S-EL1
+ or S-EL2 (SPMD_SPM_AT_SEL2).
- CPU Support
- Example: "cortex-a55: Workaround for erratum 1221012"
+ - Use Speculation Barrier instruction for v8.5+ cores
- Drivers
- Example: "console: Allow the console to register multiple times"
@@ -36,6 +48,7 @@
- Libraries
- Example: "Introduce BTI support in Library at ROM (romlib)"
- Add Firmware Configuration Framework (fconf).
+ - Add DebugFS functionality
- New Platforms Support
- Example: "qemu/qemu_sbsa: New platform support added for QEMU SBSA platform"
@@ -43,6 +56,8 @@
- Platforms
- Example: "arm/common: Introduce wrapper functions to setup secure watchdog"
- plat/arm: Add support for the new `dualroot` chain of trust.
+ - plat/arm/fvp: Add support for fconf in BL31 and SP_MIN. Populate power
+ domain desciptor dynamically by leveraging fconf APIs.
- PSCI
- Example: "Adding new optional PSCI hook ``pwr_domain_on_finish_late``"
@@ -51,6 +66,10 @@
- Example: "UBSAN support and handlers"
- Add support for optional firmware encryption feature (experimental).
- Introduce a new `dualroot` chain of trust.
+ - aarch32: stop speculative execution past exception returns.
+
+- SPCI
+ - Introduced the SPM Dispatcher (SPMD) component as a new standard service.
- Tools
- Example: "fiptool: Add support to build fiptool on Windows."
@@ -84,6 +103,7 @@
- Example: "Refactor SPSR initialisation code"
- Tools
+ - sptool updated to accomodate building secure partition packages.
- Example: "cert_create: Remove RSA PKCS#1 v1.5 support"
diff --git a/docs/components/spci-manifest-binding.rst b/docs/components/spci-manifest-binding.rst
new file mode 100644
index 0000000..66cca64
--- /dev/null
+++ b/docs/components/spci-manifest-binding.rst
@@ -0,0 +1,239 @@
+SPCI manifest binding to device tree
+====================================
+
+This document defines the nodes and properties used to define a partition,
+according to the SPCI specification.
+
+Version 1.0
+-----------
+
+spci-manifest-partition
+^^^^^^^^^^^^^^^^^^^^^^^
+
+- compatible [mandatory]
+ - value type: <string>
+ - Must be the string "arm,spci-manifest-X.Y" which specifies the major and
+ minor versions fo the device tree binding for the SPCI manifest represented
+ by this node. The minor number is incremented if the binding changes in a
+ backwards compatible manner.
+ - X is an integer representing the major version number of this document.
+ - Y is an integer representing the minor version number of this document.
+
+- spci-version [mandatory]
+ - value type: <u32>
+ - Must be two 16 bits values (X, Y), concatenated as 31:16 -> X,
+ 15:0 -> Y, where:
+ - X is the major version of PSA-FF-A expected by the partition at the SPCI
+ instance it will execute.
+ - Y is the minor version of PSA-FF-A expected by the partition at the SPCI
+ instance it will execute.
+
+- uuid [mandatory]
+ - value type: <prop-encoded-array>
+ - An array consisting of 4 <u32> values, identifying the UUID of the service
+ implemented by this partition. The UUID format is described in RFC 4122.
+ UUID can be shared by multiple instances of partitions that offer the same
+ service For example:
+ - If there are multiple instances of a Trusted OS, then the UUID can be
+ shared by all instances.
+ - The TEE driver in the HLOS can use the UUID with the
+ SPCI_PARTITION_INFO_GET interface to determine the:
+ - Number of Trusted OSs
+ - The partition ID of each instance of the Trusted OS
+
+- id
+ - value type: <u32>
+ - Pre-allocated partition ID.
+
+- auxiliary-id
+ - value type: <u32>
+ - Pre-allocated ID that could be used in memory management transactions.
+
+- description
+ - value type: <string>
+ - Name of the partition e.g. for debugging purposes.
+
+- execution-ctx-count [mandatory]
+ - value type: <u32>
+ - Number of vCPUs that a VM or SP wants to instantiate.
+ - In the absence of virtualization, this is the number of execution
+ contexts that a partition implements.
+ - If value of this field = 1 and number of PEs > 1 then the partition is
+ treated as UP & migrate capable.
+ - If the value of this field > 1 then the partition is treated as a MP
+ capable partition irrespective of the number of PEs.
+
+- exception-level [mandatory]
+ - value type: <u32>
+ - The target exception level for the partition:
+ - 0x0: EL1
+ - 0x1: S_EL0
+ - 0x2: S_EL1
+ - 0x3: EL2
+ - 0x4: Supervisor mode
+ - 0x5: Secure User mode
+
+- execution-state [mandatory]
+ - value type: <u32>
+ - The target execution state of the partition:
+ - 0: AArch64
+ - 1: AArch32
+
+- load-address
+ - value type: <u64>
+ - Physical base address of the partition in memory. Absence of this field
+ indicates that the partition is position independent and can be loaded at
+ any address chosen at boot time.
+
+- entrypoint-offset
+ - value type: <u64>
+ - Offset from the base of the partition's binary image to the entry point of
+ the partition. Absence of this field indicates that the entry point is at
+ offset 0x0 from the base of the partition's binary.
+
+- xlat-granule [mandatory]
+ - value type: <u32>
+ - Translation granule used with the partition:
+ - 0x0: 4k
+ - 0x1: 16k
+ - 0x2: 32k
+
+- boot-order
+ - value type: <u32>
+ - A unique number amongst all partitions that specifies if this partition
+ must be booted before others. The partition with the smaller number will be
+ booted first.
+
+- rx-tx-buffer
+ - value type: "memory-regions" node
+ - Specific "memory-regions" nodes that describe the RX/TX buffers expected
+ by the partition.
+ The "compatible" must be the string "arm,spci-manifest-rx_tx-buffer".
+
+- messaging-method [mandatory]
+ - value type: <u32>
+ - Specifies which messaging methods are supported by the partition:
+ - 0x0: direct messaging method
+ - 0x1: indirect messaging method
+ - 0x2: both direct and indirect messaging methods
+
+- has-primary-scheduler
+ - value type: <empty>
+ - Presence of this field indicates that the partition implements the primary
+ scheduler. If so, run-time EL must be EL1.
+
+- run-time-model
+ - value type: <u32>
+ - Run time model that the SPM must enforce for this SP:
+ - 0x0: Run to completion
+ - 0x1: Preemptible
+
+- time-slice-mem
+ - value type: <empty>
+ - Presence of this field indicates that the partition doesn't expect the
+ partition manager to time slice long running memory management functions.
+
+- gp-register-num
+ - value type: <u32>
+ - Presence of this field indicates that the partition expects the
+ spci_init_info structure to be passed in via the specified general purpose
+ register.
+ The field specifies the general purpose register number but not its width.
+ The width is derived from the partition's execution state, as specified in
+ the partition properties. For example, if the number value is 1 then the
+ general-purpose register used will be x1 in AArch64 state and w1 in AArch32
+ state.
+
+- stream-endpoint-ids
+ - value type: <prop-encoded-array>
+ - List of <u32> tuples, identifying the IDs this partition is acting as
+ proxy for.
+
+memory-regions
+--------------
+
+- compatible [mandatory]
+ - value type: <string>
+ - Must be the string "arm,spci-manifest-memory-regions".
+
+- description
+ - value type: <string>
+ - Name of the memory region e.g. for debugging purposes.
+
+- pages-count [mandatory]
+ - value type: <u32>
+ - Count of pages of memory region as a multiple of the translation granule
+ size
+
+- attributes [mandatory]
+ - value type: <u32>
+ - ?? TO DEFINE
+
+- base-address
+ - value type: <u64>
+ - Base address of the region. The address must be aligned to the translation
+ granule size.
+ The address given may be a Physical Address (PA), Virtual Address (VA), or
+ Intermediate Physical Address (IPA). Refer to the SPCI specification for
+ more information on the restrictions around the address type.
+ If the base address is omitted then the partition manager must map a memory
+ region of the specified size into the partition's translation regime and
+ then communicate the region properties (including the base address chosen
+ by the partition manager) to the partition.
+
+device-regions
+--------------
+
+- compatible [mandatory]
+ - value type: <string>
+ - Must be the string "arm,spci-manifest-device-regions".
+
+- description
+ - value type: <string>
+ - Name of the device region e.g. for debugging purposes.
+
+- reg [mandatory]
+ - value type: <prop-encoded-array>
+ - A (address, num-pages) pair describing the device, where:
+ - address: The physical base address <u64> value of the device MMIO
+ region.
+ - num-pages: The <u32> number of pages of the region. The total size of
+ the region is this value multiplied by the translation granule size.
+
+- attributes [mandatory]
+ - value type: <u32>
+ - ?? TO DEFINE
+
+- smmu-id
+ - value type: <u32>
+ - On systems with multiple System Memory Management Units (SMMUs) this
+ identifier is used to inform the partition manager which SMMU the device is
+ upstream of. If the field is omitted then it is assumed that the device is
+ not upstream of any SMMU.
+
+- stream-ids [mandatory]
+ - value type: <prop-encoded-array>
+ - A list of (id, mem-manage) pair, where:
+ - id: A unique <u32> value amongst all devices assigned to the partition.
+ - mem-manage: A <u32> value used in memory management operations.
+
+- interrupts [mandatory]
+ - value type: <prop-encoded-array>
+ - A list of (id, attributes) pair describing the device interrupts, where:
+ - id: The <u32> interrupt IDs.
+ - attributes: A ?? TO DEFINE value,
+ containing the attributes for each interrupt ID:
+ - Interrupt type: SPI, PPI, SGI
+ - Interrupt configuration: Edge triggered, Level triggered
+ - Interrupt security state: Secure, Non-secure
+ - Interrupt priority value
+ - Target execution context/vCPU for each SPI
+
+- exclusive-access
+ - value type: <empty>
+ - Presence of this field implies that this endpoint must be granted exclusive
+ access and ownership of this devices's MMIO region.
+
+--------------
+
+*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index f138feb..69e103d 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -146,6 +146,12 @@
is on hardware that does not implement AArch32, or at least not at EL1 and
higher ELs). Default value is 1.
+- ``CTX_INCLUDE_EL2_REGS`` : This boolean option provides context save/restore
+ operations when entering/exiting an EL2 execution context. This is of primary
+ interest when Armv8.4-SecEL2 extension is implemented. Default is 0 (disabled).
+ This option must be equal to 1 (enabled) when ``SPD=spmd`` and
+ ``SPMD_SPM_AT_SEL2`` is set.
+
- ``CTX_INCLUDE_FPREGS``: Boolean option that, when set to 1, will cause the FP
registers to be included when saving and restoring the CPU context. Default
is 0.
@@ -536,8 +542,8 @@
- ``SEPARATE_CODE_AND_RODATA``: Whether code and read-only data should be
isolated on separate memory pages. This is a trade-off between security and
memory usage. See "Isolating code and read-only data on separate memory
- pages" section in :ref:`Firmware Design`. This flag is disabled by default and
- affects all BL images.
+ pages" section in :ref:`Firmware Design`. This flag is disabled by default
+ and affects all BL images.
- ``SEPARATE_NOBITS_REGION``: Setting this option to ``1`` allows the NOBITS
sections of BL31 (.bss, stacks, page tables, and coherent memory) to be
@@ -550,7 +556,9 @@
This build option is only valid if ``ARCH=aarch64``. The value should be
the path to the directory containing the SPD source, relative to
``services/spd/``; the directory is expected to contain a makefile called
- ``<spd-value>.mk``.
+ ``<spd-value>.mk``. The SPM Dispatcher standard service is located in
+ services/std_svc/spmd and enabled by ``SPD=spmd``. The SPM Dispatcher
+ cannot be enabled when the ``SPM_MM`` option is enabled.
- ``SPIN_ON_BL1_EXIT``: This option introduces an infinite loop in BL1. It can
take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops
@@ -558,13 +566,23 @@
firmware images have been loaded in memory, and the MMU and caches are
turned off. Refer to the "Debugging options" section for more details.
+- ``SPMD_SPM_AT_SEL2`` : this boolean option is used jointly with the SPM
+ Dispatcher option (``SPD=spmd``). When enabled (1) it indicates the SPMC
+ component runs at the S-EL2 execution state provided by the Armv8.4-SecEL2
+ extension. This is the default when enabling the SPM Dispatcher. When
+ disabled (0) it indicates the SPMC component runs at the S-EL1 execution
+ state. This latter configuration supports pre-Armv8.4 platforms (aka not
+ implementing the Armv8.4-SecEL2 extension).
+
- ``SPM_MM`` : Boolean option to enable the Management Mode (MM)-based Secure
- Partition Manager (SPM) implementation. The default value is ``0``.
+ Partition Manager (SPM) implementation. The default value is ``0``
+ (disabled). This option cannot be enabled (``1``) when SPM Dispatcher is
+ enabled (``SPD=spmd``).
- ``SP_LAYOUT_FILE``: Platform provided path to JSON file containing the
- description of secure partitions. Build system will parse this file and
- package all secure partition blobs in FIP. This file not necessarily be
- part of TF-A tree. Only avaialbe when ``SPD=spmd``.
+ description of secure partitions. The build system will parse this file and
+ package all secure partition blobs into the FIP. This file is not
+ necessarily part of TF-A tree. Only available when ``SPD=spmd``.
- ``SP_MIN_WITH_SECURE_FIQ``: Boolean flag to indicate the SP_MIN handles
secure interrupts (caught through the FIQ line). Platforms can enable
@@ -622,8 +640,8 @@
exposing a virtual filesystem interface through BL31 as a SiP SMC function.
Default is 0.
-- ``USE_FCONF_BASED_IO``: This flag determines whether to use IO based on the
- firmware configuration framework. This allows moving the io_policies into a
+- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the
+ firmware configuration framework. This will move the io_policies into a
configuration device tree, instead of static structure in the code base.
@@ -649,6 +667,27 @@
cluster platforms). If this option is enabled, then warm boot path
enables D-caches immediately after enabling MMU. This option defaults to 0.
+GICv3 driver options
+--------------------
+
+GICv3 driver files are included using directive:
+
+``include drivers/arm/gic/v3/gicv3.mk``
+
+The driver can be configured with the following options set in the platform
+makefile:
+
+- ``GICV3_IMPL``: Selects between GIC-500 and GIC-600 variants of GICv3.
+ This option can take values GIC500 and GIC600 with default set to GIC500.
+
+- ``GICV3_IMPL_GIC600_MULTICHIP``: Selects GIC-600 variant with multichip
+ functionality. This option defaults to 0
+
+- ``GICV3_OVERRIDE_DISTIF_PWR_OPS``: Allows override of default implementation
+ of ``arm_gicv3_distif_pre_save`` and ``arm_gicv3_distif_post_restore``
+ functions. This is required for FVP platform which need to simulate GIC save
+ and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.
+
Debugging options
-----------------
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index d6572f5..2d17f12 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -1117,7 +1117,7 @@
increase the number of log levels.
Function : plat_get_soc_version()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
@@ -1132,7 +1132,7 @@
soc_version[23:16] = JEP-106 identification code with parity bit for the SiP
Function : plat_get_soc_revision()
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
::
diff --git a/drivers/arm/gic/v3/gicv3.mk b/drivers/arm/gic/v3/gicv3.mk
new file mode 100644
index 0000000..164f88e
--- /dev/null
+++ b/drivers/arm/gic/v3/gicv3.mk
@@ -0,0 +1,34 @@
+#
+# Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Default configuration values
+GICV3_IMPL ?= GIC500
+GICV3_IMPL_GIC600_MULTICHIP ?= 0
+GICV3_OVERRIDE_DISTIF_PWR_OPS ?= 0
+
+GICV3_SOURCES += drivers/arm/gic/common/gic_common.c \
+ drivers/arm/gic/v3/gicv3_main.c \
+ drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c
+
+ifeq (${GICV3_OVERRIDE_DISTIF_PWR_OPS}, 0)
+GICV3_SOURCES += drivers/arm/gic/v3/arm_gicv3_common.c
+endif
+
+# Either GIC-600 or GIC-500 can be selected at one time
+ifeq (${GICV3_IMPL}, GIC600)
+# GIC-600 sources
+GICV3_SOURCES += drivers/arm/gic/v3/gic600.c
+ifeq (${GICV3_IMPL_GIC600_MULTICHIP}, 1)
+GICV3_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
+endif
+else ifeq (${GICV3_IMPL}, GIC500)
+# GIC-500 sources
+GICV3_SOURCES += drivers/arm/gic/v3/gic500.c
+else
+$(error "Incorrect GICV3_IMPL value ${GICV3_IMPL}")
+endif
diff --git a/drivers/auth/mbedtls/mbedtls_common.mk b/drivers/auth/mbedtls/mbedtls_common.mk
index 044b368..564a4c9 100644
--- a/drivers/auth/mbedtls/mbedtls_common.mk
+++ b/drivers/auth/mbedtls/mbedtls_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -75,10 +75,19 @@
ifeq (${HASH_ALG}, sha384)
TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA384
+ MBEDTLS_MD_ID := MBEDTLS_MD_SHA384
+ TPM_ALG_ID := TPM_ALG_SHA384
+ TCG_DIGEST_SIZE := 48
else ifeq (${HASH_ALG}, sha512)
- TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA512
+ TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA512
+ MBEDTLS_MD_ID := MBEDTLS_MD_SHA512
+ TPM_ALG_ID := TPM_ALG_SHA512
+ TCG_DIGEST_SIZE := 64
else
TF_MBEDTLS_HASH_ALG_ID := TF_MBEDTLS_SHA256
+ MBEDTLS_MD_ID := MBEDTLS_MD_SHA256
+ TPM_ALG_ID := TPM_ALG_SHA256
+ TCG_DIGEST_SIZE := 32
endif
ifeq (${TF_MBEDTLS_KEY_ALG},ecdsa)
@@ -103,6 +112,11 @@
$(eval $(call add_define,TF_MBEDTLS_HASH_ALG_ID))
$(eval $(call add_define,TF_MBEDTLS_USE_AES_GCM))
+# Set definitions for measured boot driver
+$(eval $(call add_define,MBEDTLS_MD_ID))
+$(eval $(call add_define,TPM_ALG_ID))
+$(eval $(call add_define,TCG_DIGEST_SIZE))
+
$(eval $(call MAKE_LIB,mbedtls))
endif
diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c
index 4ae55fc..40cd455 100644
--- a/drivers/st/ddr/stm32mp1_ram.c
+++ b/drivers/st/ddr/stm32mp1_ram.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -250,8 +250,9 @@
VERBOSE("%s : ram size(%x, %x)\n", __func__,
(uint32_t)priv->info.base, (uint32_t)priv->info.size);
- write_sctlr(read_sctlr() & ~SCTLR_C_BIT);
- dcsw_op_all(DC_OP_CISW);
+ if (stm32mp_map_ddr_non_cacheable() != 0) {
+ panic();
+ }
uret = ddr_test_data_bus();
if (uret != 0U) {
@@ -274,7 +275,9 @@
panic();
}
- write_sctlr(read_sctlr() | SCTLR_C_BIT);
+ if (stm32mp_unmap_ddr() != 0) {
+ panic();
+ }
return 0;
}
diff --git a/drivers/st/fmc/stm32_fmc2_nand.c b/drivers/st/fmc/stm32_fmc2_nand.c
index b694fff..d2d7e06 100644
--- a/drivers/st/fmc/stm32_fmc2_nand.c
+++ b/drivers/st/fmc/stm32_fmc2_nand.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -365,7 +365,7 @@
xor_ecc_2b = ecc[1] ^ eccbuffer[1];
xor_ecc_3b = ecc[2] ^ eccbuffer[2];
- xor_ecc.val = 0L;
+ xor_ecc.val = 0U;
xor_ecc.bytes[2] = xor_ecc_3b;
xor_ecc.bytes[1] = xor_ecc_2b;
xor_ecc.bytes[0] = xor_ecc_1b;
diff --git a/drivers/st/io/io_stm32image.c b/drivers/st/io/io_stm32image.c
index 413521b..3e377cd 100644
--- a/drivers/st/io/io_stm32image.c
+++ b/drivers/st/io/io_stm32image.c
@@ -247,7 +247,7 @@
size_t length, size_t *length_read)
{
int result;
- uint8_t *local_buffer = (uint8_t *)buffer;
+ uint8_t *local_buffer;
boot_api_image_header_t *header =
(boot_api_image_header_t *)first_lba_buffer;
@@ -255,6 +255,7 @@
assert(buffer != 0U);
assert(length_read != NULL);
+ local_buffer = (uint8_t *)buffer;
*length_read = 0U;
while (*length_read == 0U) {
diff --git a/drivers/st/spi/stm32_qspi.c b/drivers/st/spi/stm32_qspi.c
index 188d2ff..c5e4ea8 100644
--- a/drivers/st/spi/stm32_qspi.c
+++ b/drivers/st/spi/stm32_qspi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -12,6 +12,7 @@
#include <drivers/delay_timer.h>
#include <drivers/spi_mem.h>
#include <drivers/st/stm32_gpio.h>
+#include <drivers/st/stm32_qspi.h>
#include <drivers/st/stm32mp_reset.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
@@ -172,9 +173,8 @@
static int stm32_qspi_poll(const struct spi_mem_op *op)
{
void (*fifo)(uint8_t *val, uintptr_t addr);
- uint32_t len = op->data.nbytes;
+ uint32_t len;
uint8_t *buf;
- uint64_t timeout;
if (op->data.dir == SPI_MEM_DATA_IN) {
fifo = stm32_qspi_read_fifo;
@@ -185,7 +185,8 @@
buf = (uint8_t *)op->data.buf;
for (len = op->data.nbytes; len != 0U; len--) {
- timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US);
+ uint64_t timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US);
+
while ((mmio_read_32(qspi_base() + QSPI_SR) &
QSPI_SR_FTF) == 0U) {
if (timeout_elapsed(timeout)) {
diff --git a/fdts/corstone700.dts b/fdts/corstone700.dts
index c13d3b2..851f5e6 100644
--- a/fdts/corstone700.dts
+++ b/fdts/corstone700.dts
@@ -15,8 +15,6 @@
chosen {
bootargs = "console=ttyAMA0 \
- root=mtd:physmap-flash.0 \
- ro \
loglevel=9";
};
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 240c1fb..7c30758 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -531,6 +531,23 @@
return GET_EL(read_CurrentEl());
}
+static inline unsigned int get_current_el_maybe_constant(void)
+{
+#if defined(IMAGE_AT_EL1)
+ return 1;
+#elif defined(IMAGE_AT_EL2)
+ return 2; /* no use-case in TF-A */
+#elif defined(IMAGE_AT_EL3)
+ return 3;
+#else
+ /*
+ * If we do not know which exception level this is being built for
+ * (e.g. built for library), fall back to run-time detection.
+ */
+ return get_current_el();
+#endif
+}
+
/*
* Check if an EL is implemented from AA64PFR0 register fields.
*/
diff --git a/include/bl32/payloads/tlk.h b/include/bl32/payloads/tlk.h
index 5162d13..290f329 100644
--- a/include/bl32/payloads/tlk.h
+++ b/include/bl32/payloads/tlk.h
@@ -24,6 +24,9 @@
#define TLK_SS_REGISTER_HANDLER TLK_TOS_YIELD_FID(0x3)
#define TLK_REGISTER_NS_DRAM_RANGES TLK_TOS_YIELD_FID(0x4)
#define TLK_SET_ROOT_OF_TRUST TLK_TOS_YIELD_FID(0x5)
+#define TLK_SET_BL_VERSION TLK_TOS_YIELD_FID(0x6)
+#define TLK_LOCK_BL_INTERFACE TLK_TOS_YIELD_FID(0x7)
+#define TLK_BL_RPMB_SERVICE TLK_TOS_YIELD_FID(0x8)
#define TLK_RESUME_FID TLK_TOS_YIELD_FID(0x100)
#define TLK_SYSTEM_SUSPEND TLK_TOS_YIELD_FID(0xE001)
#define TLK_SYSTEM_RESUME TLK_TOS_YIELD_FID(0xE002)
diff --git a/include/drivers/raw_nand.h b/include/drivers/raw_nand.h
index 18e4b73..9018f02 100644
--- a/include/drivers/raw_nand.h
+++ b/include/drivers/raw_nand.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,7 @@
#ifndef DRIVERS_RAW_NAND_H
#define DRIVERS_RAW_NAND_H
+#include <cdefs.h>
#include <stdint.h>
#include <drivers/nand.h>
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index e061950..0029658 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -183,7 +183,7 @@
#define CTX_SPSR_EL2 U(0xd0)
#define CTX_SP_EL2 U(0xd8)
#define CTX_TCR_EL2 U(0xe0)
-#define CTX_TRFCR_EL2 U(0xe8)
+#define CTX_TPIDR_EL2 U(0xe8)
#define CTX_TTBR0_EL2 U(0xf0)
#define CTX_VBAR_EL2 U(0xf8)
#define CTX_VMPIDR_EL2 U(0x100)
@@ -234,11 +234,13 @@
#define CTX_VSESR_EL2 U(0x228)
#define CTX_VSTCR_EL2 U(0x230)
#define CTX_VSTTBR_EL2 U(0x238)
+#define CTX_TRFCR_EL2 U(0x240)
// Starting with Armv8.5
-#define CTX_SCXTNUM_EL2 U(0x240)
+#define CTX_SCXTNUM_EL2 U(0x248)
/* Align to the next 16 byte boundary */
#define CTX_EL2_SYSREGS_END U(0x250)
+
#endif /* CTX_INCLUDE_EL2_REGS */
/*******************************************************************************
diff --git a/include/lib/pmf/pmf_helpers.h b/include/lib/pmf/pmf_helpers.h
index db38e55..cfb27f7 100644
--- a/include/lib/pmf/pmf_helpers.h
+++ b/include/lib/pmf/pmf_helpers.h
@@ -173,7 +173,7 @@
unsigned int tid, \
unsigned long long ts) \
{ \
- CASSERT(_flags, select_proper_config); \
+ CASSERT(_flags != 0, select_proper_config); \
PMF_VALIDATE_TID(_name, tid); \
uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \
if (((_flags) & PMF_STORE_ENABLE) != 0) \
@@ -185,7 +185,7 @@
unsigned int tid, \
unsigned long long ts) \
{ \
- CASSERT(_flags, select_proper_config); \
+ CASSERT(_flags != 0, select_proper_config); \
PMF_VALIDATE_TID(_name, tid); \
uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \
if (((_flags) & PMF_STORE_ENABLE) != 0) \
diff --git a/include/lib/xlat_tables/xlat_mmu_helpers.h b/include/lib/xlat_tables/xlat_mmu_helpers.h
index abdf1b6..269afd2 100644
--- a/include/lib/xlat_tables/xlat_mmu_helpers.h
+++ b/include/lib/xlat_tables/xlat_mmu_helpers.h
@@ -56,6 +56,8 @@
#include <stdint.h>
#include <string.h>
+#include <arch_helpers.h>
+
/*
* Return the values that the MMU configuration registers must contain for the
* specified translation context. `params` must be a pointer to array of size
@@ -70,6 +72,7 @@
void enable_mmu_el1(unsigned int flags);
void enable_mmu_el2(unsigned int flags);
void enable_mmu_el3(unsigned int flags);
+void enable_mmu(unsigned int flags);
void enable_mmu_direct_el1(unsigned int flags);
void enable_mmu_direct_el2(unsigned int flags);
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 7df6b0d..7c852e1 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -12,6 +12,7 @@
#include <drivers/arm/gic_common.h>
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h>
/******************************************************************************
diff --git a/include/plat/arm/common/arm_dyn_cfg_helpers.h b/include/plat/arm/common/arm_dyn_cfg_helpers.h
index 2dc94ab..34bf07c 100644
--- a/include/plat/arm/common/arm_dyn_cfg_helpers.h
+++ b/include/plat/arm/common/arm_dyn_cfg_helpers.h
@@ -14,4 +14,8 @@
int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr,
size_t heap_size);
+#if MEASURED_BOOT
+int arm_set_bl2_hash_info(void *dtb, void *data);
+#endif
+
#endif /* ARM_DYN_CFG_HELPERS_H */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index a84047a..1b59795 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -148,11 +148,6 @@
#define ARM_ROTPK_DEVEL_RSA_ID 2
#define ARM_ROTPK_DEVEL_ECDSA_ID 3
-/* Defines used to retrieve ARM SOC revision */
-#define ARM_SOC_CONTINUATION_CODE U(0x4)
-#define ARM_SOC_IDENTIFICATION_CODE U(0x3B)
-#define ARM_SOC_CONTINUATION_SHIFT U(24)
-#define ARM_SOC_IDENTIFICATION_SHIFT U(16)
/* IO storage utility functions */
int arm_io_setup(void);
@@ -238,6 +233,11 @@
void arm_bl1_set_mbedtls_heap(void);
int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
+#if MEASURED_BOOT
+/* Measured boot related functions */
+void arm_bl1_set_bl2_hash(image_desc_t *image_desc);
+#endif
+
/*
* Free the memory storing initialization code only used during an images boot
* time so it can be reclaimed for runtime data
diff --git a/include/plat/arm/common/smccc_def.h b/include/plat/arm/common/smccc_def.h
new file mode 100644
index 0000000..6e698e5
--- /dev/null
+++ b/include/plat/arm/common/smccc_def.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef SMCCC_DEF_H
+#define SMCCC_DEF_H
+
+/* Defines used to retrieve ARM SOC revision */
+#define ARM_SOC_CONTINUATION_CODE U(0x4)
+#define ARM_SOC_IDENTIFICATION_CODE U(0x3B)
+#define ARM_SOC_CONTINUATION_SHIFT U(24)
+#define ARM_SOC_IDENTIFICATION_SHIFT U(16)
+
+#endif /* SMCCC_DEF_H */
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 30ad7b7..221f33e 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -100,7 +100,7 @@
stp x10, x11, [x0, #CTX_SPSR_EL2]
mrs x12, tcr_el2
- mrs x13, TRFCR_EL2
+ mrs x13, tpidr_el2
stp x12, x13, [x0, #CTX_TCR_EL2]
mrs x14, ttbr0_el2
@@ -204,11 +204,14 @@
mrs x16, vsttbr_el2
str x16, [x0, #CTX_VSTTBR_EL2]
+
+ mrs x17, TRFCR_EL2
+ str x17, [x0, #CTX_TRFCR_EL2]
#endif
#if ARM_ARCH_AT_LEAST(8, 5)
- mrs x17, scxtnum_el2
- str x17, [x0, #CTX_SCXTNUM_EL2]
+ mrs x9, scxtnum_el2
+ str x9, [x0, #CTX_SCXTNUM_EL2]
#endif
ret
@@ -289,7 +292,7 @@
ldp x12, x13, [x0, #CTX_TCR_EL2]
msr tcr_el2, x12
- msr TRFCR_EL2, x13
+ msr tpidr_el2, x13
ldp x14, x15, [x0, #CTX_TTBR0_EL2]
msr ttbr0_el2, x14
@@ -391,11 +394,14 @@
ldr x16, [x0, #CTX_VSTTBR_EL2]
msr vsttbr_el2, x16
+
+ ldr x17, [x0, #CTX_TRFCR_EL2]
+ msr TRFCR_EL2, x17
#endif
#if ARM_ARCH_AT_LEAST(8, 5)
- ldr x17, [x0, #CTX_SCXTNUM_EL2]
- msr scxtnum_el2, x17
+ ldr x9, [x0, #CTX_SCXTNUM_EL2]
+ msr scxtnum_el2, x9
#endif
ret
diff --git a/lib/fconf/fconf.c b/lib/fconf/fconf.c
index 9ce4635..a5ec143 100644
--- a/lib/fconf/fconf.c
+++ b/lib/fconf/fconf.c
@@ -33,7 +33,7 @@
err = load_auth_image(TB_FW_CONFIG_ID, &arm_tb_fw_info);
if (err != 0) {
/* Return if FW_CONFIG is not loaded */
- VERBOSE("Failed to load FW_CONFIG\n");
+ VERBOSE("FW_CONFIG not loaded, continuing without it\n");
return;
}
diff --git a/lib/fconf/fconf.mk b/lib/fconf/fconf.mk
index 7031969..c087102 100644
--- a/lib/fconf/fconf.mk
+++ b/lib/fconf/fconf.mk
@@ -5,8 +5,8 @@
#
# Add Firmware Configuration files
-FCONF_SOURCES := lib/fconf/fconf.c \
- lib/fconf/fconf_dyn_cfg_getter.c
+FCONF_SOURCES := lib/fconf/fconf.c
+FCONF_DYN_SOURCES := lib/fconf/fconf_dyn_cfg_getter.c
BL1_SOURCES += ${FCONF_SOURCES}
-BL2_SOURCES += ${FCONF_SOURCES}
+BL2_SOURCES += ${FCONF_SOURCES} ${FCONF_DYN_SOURCES}
diff --git a/lib/xlat_tables_v2/xlat_tables_context.c b/lib/xlat_tables_v2/xlat_tables_context.c
index a1c974e..032e142 100644
--- a/lib/xlat_tables_v2/xlat_tables_context.c
+++ b/lib/xlat_tables_v2/xlat_tables_context.c
@@ -239,6 +239,23 @@
enable_mmu_direct_el3(flags);
}
+void enable_mmu(unsigned int flags)
+{
+ switch (get_current_el_maybe_constant()) {
+ case 1:
+ enable_mmu_el1(flags);
+ break;
+ case 2:
+ enable_mmu_el2(flags);
+ break;
+ case 3:
+ enable_mmu_el3(flags);
+ break;
+ default:
+ panic();
+ }
+}
+
#else /* !__aarch64__ */
void enable_mmu_svc_mon(unsigned int flags)
diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk
index 20a36fe..1c3d14d 100644
--- a/make_helpers/build_macros.mk
+++ b/make_helpers/build_macros.mk
@@ -273,12 +273,12 @@
$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
-$(eval IMAGE := IMAGE_BL$(call uppercase,$(3)))
+$(eval BL_CPPFLAGS := $(BL$(call uppercase,$(3))_CPPFLAGS) -DIMAGE_BL$(call uppercase,$(3)))
$(eval BL_CFLAGS := $(BL$(call uppercase,$(3))_CFLAGS))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
$$(ECHO) " CC $$<"
- $$(Q)$$(CC) $$(LTO_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(BL_CFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@
+ $$(Q)$$(CC) $$(LTO_CFLAGS) $$(TF_CFLAGS) $$(CFLAGS) $(BL_CPPFLAGS) $(BL_CFLAGS) $(MAKE_DEP) -c $$< -o $$@
-include $(DEP)
@@ -293,11 +293,12 @@
$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
$(eval DEP := $(patsubst %.o,%.d,$(OBJ)))
-$(eval IMAGE := IMAGE_BL$(call uppercase,$(3)))
+$(eval BL_CPPFLAGS := $(BL$(call uppercase,$(3))_CPPFLAGS) -DIMAGE_BL$(call uppercase,$(3)))
+$(eval BL_ASFLAGS := $(BL$(call uppercase,$(3))_ASFLAGS))
$(OBJ): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
$$(ECHO) " AS $$<"
- $$(Q)$$(AS) $$(ASFLAGS) -D$(IMAGE) $(MAKE_DEP) -c $$< -o $$@
+ $$(Q)$$(AS) $$(ASFLAGS) $(BL_CPPFLAGS) $(BL_ASFLAGS) $(MAKE_DEP) -c $$< -o $$@
-include $(DEP)
@@ -311,11 +312,11 @@
define MAKE_LD
$(eval DEP := $(1).d)
-$(eval IMAGE := IMAGE_BL$(call uppercase,$(3)))
+$(eval BL_CPPFLAGS := $(BL$(call uppercase,$(3))_CPPFLAGS) -DIMAGE_BL$(call uppercase,$(3)))
$(1): $(2) $(filter-out %.d,$(MAKEFILE_LIST)) | bl$(3)_dirs
$$(ECHO) " PP $$<"
- $$(Q)$$(CPP) $$(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) -P -x assembler-with-cpp -D__LINKER__ $(MAKE_DEP) -D$(IMAGE) -o $$@ $$<
+ $$(Q)$$(CPP) $$(CPPFLAGS) $(BL_CPPFLAGS) $(TF_CFLAGS_$(ARCH)) -P -x assembler-with-cpp -D__LINKER__ $(MAKE_DEP) -o $$@ $$<
-include $(DEP)
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 03322db..4e968e2 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -223,7 +223,7 @@
USE_DEBUGFS := 0
# Build option to fconf based io
-USE_FCONF_BASED_IO := 0
+ARM_IO_IN_DTB := 0
# Build option to choose whether Trusted Firmware uses library at ROM
USE_ROMLIB := 0
diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
index 0e204d0..702db77 100644
--- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
+++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
@@ -29,9 +29,9 @@
#define SUNXI_SID_BASE 0x03006000
#define SUNXI_DMA_BASE 0x03002000
#define SUNXI_MSGBOX_BASE 0x03003000
-#define SUNXI_CCU_BASE 0x03010000
+#define SUNXI_CCU_BASE 0x03001000
#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0xf00)
-#define SUNXI_PIO_BASE 0x030b0000
+#define SUNXI_PIO_BASE 0x0300b000
#define SUNXI_TIMER_BASE 0x03009000
#define SUNXI_WDOG_BASE 0x030090a0
#define SUNXI_THS_BASE 0x05070400
diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h
index 31dfb1c..ab0ff58 100644
--- a/plat/arm/board/a5ds/include/platform_def.h
+++ b/plat/arm/board/a5ds/include/platform_def.h
@@ -11,6 +11,7 @@
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/arm/board/common/v2m_def.h>
+#include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h>
/* Memory location options for TSP */
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
index 7198842..3a4d5e5 100644
--- a/plat/arm/board/a5ds/platform.mk
+++ b/plat/arm/board/a5ds/platform.mk
@@ -41,6 +41,7 @@
plat/arm/common/arm_err.c \
plat/arm/board/a5ds/a5ds_err.c \
plat/arm/common/arm_io_storage.c \
+ plat/arm/common/fconf/arm_fconf_io.c \
plat/arm/board/a5ds/${ARCH}/a5ds_helpers.S \
plat/arm/board/a5ds/a5ds_bl1_setup.c \
lib/aarch32/arm32_aeabi_divmod.c \
@@ -61,6 +62,7 @@
plat/arm/common/arm_err.c \
plat/arm/board/a5ds/a5ds_err.c \
plat/arm/common/arm_io_storage.c \
+ plat/arm/common/fconf/arm_fconf_io.c \
plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c \
plat/arm/common/arm_image_load.c \
common/desc_image_load.c \
diff --git a/plat/arm/board/arm_fpga/aarch64/fpga_helpers.S b/plat/arm/board/arm_fpga/aarch64/fpga_helpers.S
new file mode 100644
index 0000000..f350455
--- /dev/null
+++ b/plat/arm/board/arm_fpga/aarch64/fpga_helpers.S
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <platform_def.h>
+
+ .globl plat_get_my_entrypoint
+ .globl plat_secondary_cold_boot_setup
+ .globl plat_is_my_cpu_primary
+ .globl platform_mem_init
+ .globl plat_my_core_pos
+ .globl plat_fpga_calc_core_pos
+ .globl plat_crash_console_init
+ .globl plat_crash_console_putc
+ .globl plat_crash_console_flush
+
+/* -----------------------------------------------------------------------
+ * Indicate a cold boot for every CPU - warm boot is unsupported for the
+ * holding pen PSCI implementation.
+ * -----------------------------------------------------------------------
+ */
+func plat_get_my_entrypoint
+ mov x0, #0
+ ret
+endfunc plat_get_my_entrypoint
+
+/* -----------------------------------------------------------------------
+ * void plat_secondary_cold_boot_setup (void);
+ * -----------------------------------------------------------------------
+ */
+func plat_secondary_cold_boot_setup
+ /*
+ * Poll the CPU's hold entry until it indicates to jump
+ * to the entrypoint address.
+ */
+ bl plat_my_core_pos
+ lsl x0, x0, #PLAT_FPGA_HOLD_ENTRY_SHIFT
+ ldr x1, =hold_base
+ ldr x2, =fpga_sec_entrypoint
+poll_hold_entry:
+ ldr x3, [x1, x0]
+ cmp x3, #PLAT_FPGA_HOLD_STATE_GO
+ b.ne 1f
+ ldr x3, [x2]
+ br x3
+1:
+ wfe
+ b poll_hold_entry
+endfunc plat_secondary_cold_boot_setup
+
+/* -----------------------------------------------------------------------
+ * unsigned int plat_is_my_cpu_primary (void);
+ *
+ * Find out whether the current cpu is the primary cpu
+ * -----------------------------------------------------------------------
+ */
+func plat_is_my_cpu_primary
+ mrs x0, mpidr_el1
+ mov_imm x1, MPIDR_AFFINITY_MASK
+ and x0, x0, x1
+ cmp x0, #FPGA_PRIMARY_CPU
+ cset w0, eq
+ ret
+endfunc plat_is_my_cpu_primary
+
+func platform_mem_init
+ ret
+endfunc platform_mem_init
+
+func plat_my_core_pos
+ mrs x0, mpidr_el1
+ b plat_fpga_calc_core_pos
+endfunc plat_my_core_pos
+
+/* -----------------------------------------------------------------------
+ * unsigned int plat_fpga_calc_core_pos(u_register_t mpidr)
+ * -----------------------------------------------------------------------
+ */
+func plat_fpga_calc_core_pos
+ /*
+ * Check for MT bit in MPIDR, which may be either value for images
+ * running on the FPGA.
+ *
+ * If not set, shift MPIDR to left to make it look as if in a
+ * multi-threaded implementation.
+ */
+ tst x0, #MPIDR_MT_MASK
+ lsl x3, x0, #MPIDR_AFFINITY_BITS
+ csel x3, x3, x0, eq
+
+ /* Extract individual affinity fields from MPIDR */
+ ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+
+ /* Compute linear position */
+ mov x4, #FPGA_MAX_CPUS_PER_CLUSTER
+ madd x1, x2, x4, x1
+ mov x5, #FPGA_MAX_PE_PER_CPU
+ madd x0, x1, x5, x0
+ ret
+endfunc plat_fpga_calc_core_pos
+
+func plat_crash_console_init
+ mov_imm x0, PLAT_FPGA_CRASH_UART_BASE
+ mov_imm x1, PLAT_FPGA_CRASH_UART_CLK_IN_HZ
+ mov_imm x2, PLAT_FPGA_CONSOLE_BAUDRATE
+ b console_pl011_core_init
+endfunc plat_crash_console_init
+
+func plat_crash_console_putc
+ mov_imm x1, PLAT_FPGA_CRASH_UART_BASE
+ b console_pl011_core_putc
+endfunc plat_crash_console_putc
+
+func plat_crash_console_flush
+ mov_imm x0, PLAT_FPGA_CRASH_UART_BASE
+ b console_pl011_core_flush
+endfunc plat_crash_console_flush
diff --git a/plat/arm/board/arm_fpga/fpga_bl31_setup.c b/plat/arm/board/arm_fpga/fpga_bl31_setup.c
new file mode 100644
index 0000000..d499379
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_bl31_setup.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <lib/mmio.h>
+#include <drivers/generic_delay_timer.h>
+
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+#include "fpga_private.h"
+
+static entry_point_info_t bl33_image_ep_info;
+
+uintptr_t plat_get_ns_image_entrypoint(void)
+{
+#ifdef PRELOADED_BL33_BASE
+ return PRELOADED_BL33_BASE;
+#else
+ return 0;
+#endif
+}
+
+uint32_t fpga_get_spsr_for_bl33_entry(void)
+{
+ return SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+}
+
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ fpga_console_init();
+
+ bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
+ bl33_image_ep_info.spsr = fpga_get_spsr_for_bl33_entry();
+ SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
+
+ /* Set x0-x3 for the primary CPU as expected by the kernel */
+ bl33_image_ep_info.args.arg0 = (u_register_t)FPGA_PRELOADED_DTB_BASE;
+ bl33_image_ep_info.args.arg1 = 0U;
+ bl33_image_ep_info.args.arg2 = 0U;
+ bl33_image_ep_info.args.arg3 = 0U;
+}
+
+void bl31_plat_arch_setup(void)
+{
+}
+
+void bl31_platform_setup(void)
+{
+ /* Initialize the GIC driver, cpu and distributor interfaces */
+ plat_fpga_gic_init();
+
+ /* Write frequency to CNTCRL and initialize timer */
+ generic_delay_timer_init();
+ mmio_write_32(FPGA_TIMER_BASE, ((1 << 8) | 1UL));
+}
+
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+ entry_point_info_t *next_image_info;
+ next_image_info = &bl33_image_ep_info;
+
+ /* Only expecting BL33: the kernel will run in EL2NS */
+ assert(type == NON_SECURE);
+
+ /* None of the images can have 0x0 as the entrypoint */
+ if (next_image_info->pc) {
+ return next_image_info;
+ } else {
+ return NULL;
+ }
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return FPGA_TIMER_FREQUENCY;
+}
+
+void bl31_plat_enable_mmu(uint32_t flags)
+{
+ /* TODO: determine if MMU needs to be enabled */
+}
diff --git a/plat/arm/board/arm_fpga/fpga_console.c b/plat/arm/board/arm_fpga/fpga_console.c
new file mode 100644
index 0000000..b4ebf34
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_console.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/console.h>
+#include <drivers/arm/pl011.h>
+
+#include <platform_def.h>
+
+static console_t console;
+
+void fpga_console_init(void)
+{
+ (void)console_pl011_register(PLAT_FPGA_BOOT_UART_BASE,
+ PLAT_FPGA_BOOT_UART_CLK_IN_HZ,
+ PLAT_FPGA_CONSOLE_BAUDRATE,
+ &console);
+
+ console_set_scope(&console, CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME);
+}
diff --git a/plat/arm/board/arm_fpga/fpga_def.h b/plat/arm/board/arm_fpga/fpga_def.h
new file mode 100644
index 0000000..56ee166
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_def.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/utils_def.h>
+
+#ifndef FPGA_DEF_H
+#define FPGA_DEF_H
+
+/*
+ * These are set to large values to account for images describing systems with
+ * larger cluster configurations.
+ *
+ * For cases where the number of clusters, cores or threads is smaller than a
+ * maximum value below, this does not affect the PSCI functionality as any PEs
+ * that are present will still be indexed appropriately regardless of any empty
+ * entries in the array used to represent the topology.
+ */
+#define FPGA_MAX_CLUSTER_COUNT 2
+#define FPGA_MAX_CPUS_PER_CLUSTER 8
+#define FPGA_MAX_PE_PER_CPU 4
+
+#define FPGA_PRIMARY_CPU 0x0
+
+/*******************************************************************************
+ * FPGA image memory map related constants
+ ******************************************************************************/
+
+/* UART base address and clock frequency, as configured by the image */
+#define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000
+#define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 10000000
+
+#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE
+#define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ
+
+#define FPGA_TIMER_FREQUENCY 10000000
+#define FPGA_TIMER_BASE 0x2a830000
+
+#endif
diff --git a/plat/arm/board/arm_fpga/fpga_gicv3.c b/plat/arm/board/arm_fpga/fpga_gicv3.c
new file mode 100644
index 0000000..be1684e
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_gicv3.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <drivers/arm/gicv3.h>
+#include <drivers/arm/gic_common.h>
+
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+static const interrupt_prop_t fpga_interrupt_props[] = {
+ PLATFORM_G1S_PROPS(INTR_GROUP1S),
+ PLATFORM_G0_PROPS(INTR_GROUP0)
+};
+
+static uintptr_t fpga_rdistif_base_addrs[PLATFORM_CORE_COUNT];
+
+static unsigned int fpga_mpidr_to_core_pos(unsigned long mpidr)
+{
+ return (unsigned int)plat_core_pos_by_mpidr(mpidr);
+}
+
+static const gicv3_driver_data_t fpga_gicv3_driver_data = {
+ .gicd_base = GICD_BASE,
+ .gicr_base = GICR_BASE,
+ .interrupt_props = fpga_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(fpga_interrupt_props),
+ .rdistif_num = PLATFORM_CORE_COUNT,
+ .rdistif_base_addrs = fpga_rdistif_base_addrs,
+ .mpidr_to_core_pos = fpga_mpidr_to_core_pos
+};
+
+void plat_fpga_gic_init(void)
+{
+ gicv3_driver_init(&fpga_gicv3_driver_data);
+ gicv3_distif_init();
+ gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+void fpga_pwr_gic_on_finish(void)
+{
+ gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+void fpga_pwr_gic_off(void)
+{
+ gicv3_cpuif_disable(plat_my_core_pos());
+ gicv3_rdistif_off(plat_my_core_pos());
+}
diff --git a/plat/arm/board/arm_fpga/fpga_pm.c b/plat/arm/board/arm_fpga/fpga_pm.c
new file mode 100644
index 0000000..4c37217
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_pm.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+#include "fpga_private.h"
+#include <platform_def.h>
+
+/*
+ * This is a basic PSCI implementation that allows secondary CPUs to be
+ * released from their initial state and continue to the warm boot entrypoint.
+ *
+ * The secondary CPUs are placed in a holding pen and released by calls
+ * to fpga_pwr_domain_on(mpidr), which updates the hold entry for the CPU
+ * specified by the mpidr argument - the (polling) target CPU will then branch
+ * to the BL31 warm boot sequence at the entrypoint address.
+ *
+ * Additionally, the secondary CPUs are kept in a low-power wfe() state
+ * (placed there at the end of each poll) and woken when necessary through
+ * calls to sev() in fpga_pwr_domain_on(mpidr), once the hold state for the
+ * relevant CPU has been updated.
+ *
+ * Hotplug is currently implemented using a wfi-loop, which removes the
+ * dependencies on any power controllers or other mechanism that is specific
+ * to the running system as specified by the FPGA image.
+ */
+
+uint64_t hold_base[PLATFORM_CORE_COUNT];
+uintptr_t fpga_sec_entrypoint;
+
+/*
+ * Calls to the CPU specified by the mpidr will set its hold entry to a value
+ * indicating that it should stop polling and branch off to the warm entrypoint.
+ */
+static int fpga_pwr_domain_on(u_register_t mpidr)
+{
+ unsigned int pos = plat_core_pos_by_mpidr(mpidr);
+ unsigned long current_mpidr = read_mpidr_el1();
+
+ if (mpidr == current_mpidr) {
+ return PSCI_E_ALREADY_ON;
+ }
+ hold_base[pos] = PLAT_FPGA_HOLD_STATE_GO;
+ flush_dcache_range((uintptr_t)&hold_base[pos], sizeof(uint64_t));
+ sev(); /* Wake any CPUs from wfe */
+
+ return PSCI_E_SUCCESS;
+}
+
+void fpga_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ fpga_pwr_gic_on_finish();
+}
+
+static void fpga_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ fpga_pwr_gic_off();
+
+ while (1) {
+ wfi();
+ }
+}
+
+static void fpga_cpu_standby(plat_local_state_t cpu_state)
+{
+ /*
+ * Enter standby state
+ * dsb is good practice before using wfi to enter low power states
+ */
+ u_register_t scr = read_scr_el3();
+ write_scr_el3(scr|SCR_IRQ_BIT);
+ dsb();
+ wfi();
+ write_scr_el3(scr);
+}
+
+plat_psci_ops_t plat_fpga_psci_pm_ops = {
+ .pwr_domain_on = fpga_pwr_domain_on,
+ .pwr_domain_on_finish = fpga_pwr_domain_on_finish,
+ .pwr_domain_off = fpga_pwr_domain_off,
+ .cpu_standby = fpga_cpu_standby
+};
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ fpga_sec_entrypoint = sec_entrypoint;
+ flush_dcache_range((uint64_t)&fpga_sec_entrypoint,
+ sizeof(fpga_sec_entrypoint));
+ *psci_ops = &plat_fpga_psci_pm_ops;
+ return 0;
+}
diff --git a/plat/arm/board/arm_fpga/fpga_private.h b/plat/arm/board/arm_fpga/fpga_private.h
new file mode 100644
index 0000000..7545bd1
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_private.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FPGA_PRIVATE_H
+#define FPGA_PRIVATE_H
+
+unsigned int plat_fpga_calc_core_pos(u_register_t mpidr);
+
+void fpga_console_init(void);
+
+void plat_fpga_gic_init(void);
+void fpga_pwr_gic_on_finish(void);
+void fpga_pwr_gic_off(void);
+
+#endif
diff --git a/plat/arm/board/arm_fpga/fpga_topology.c b/plat/arm/board/arm_fpga/fpga_topology.c
new file mode 100644
index 0000000..a705429
--- /dev/null
+++ b/plat/arm/board/arm_fpga/fpga_topology.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+
+#include "fpga_private.h"
+#include <platform_def.h>
+
+static unsigned char fpga_power_domain_tree_desc[FPGA_MAX_CLUSTER_COUNT + 2];
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ int i;
+ /*
+ * The highest level is the system level. The next level is constituted
+ * by clusters and then cores in clusters.
+ *
+ * This description of the power domain topology is aligned with the CPU
+ * indices returned by the plat_core_pos_by_mpidr() and plat_my_core_pos()
+ * APIs.
+ */
+ fpga_power_domain_tree_desc[0] = 1;
+ fpga_power_domain_tree_desc[1] = FPGA_MAX_CLUSTER_COUNT;
+
+ for (i = 0; i < FPGA_MAX_CLUSTER_COUNT; i++) {
+ fpga_power_domain_tree_desc[i + 2] = FPGA_MAX_CPUS_PER_CLUSTER;
+ }
+
+ return fpga_power_domain_tree_desc;
+}
+
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id, thread_id;
+
+ mpidr &= MPIDR_AFFINITY_MASK;
+ if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
+ return -1;
+ }
+
+ if (mpidr & MPIDR_MT_MASK) {
+ thread_id = MPIDR_AFFLVL0_VAL(mpidr);
+ } else {
+ thread_id = 0;
+ }
+
+ cpu_id = MPIDR_AFFLVL1_VAL(mpidr);
+ cluster_id = MPIDR_AFFLVL2_VAL(mpidr);
+
+ if (cluster_id >= FPGA_MAX_CLUSTER_COUNT) {
+ return -1;
+ } else if (cpu_id >= FPGA_MAX_CPUS_PER_CLUSTER) {
+ return -1;
+ } else if (thread_id >= FPGA_MAX_PE_PER_CPU) {
+ return -1;
+ }
+
+ /*
+ * The image running on the FPGA may or may not implement multithreading,
+ * and it shouldn't be assumed this is consistent across all CPUs.
+ * This ensures that any passed mpidr values reflect the status of the
+ * primary CPU's MT bit.
+ */
+ mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
+
+ /* Calculate the correct core, catering for multi-threaded images */
+ return (int) plat_fpga_calc_core_pos(mpidr);
+}
diff --git a/plat/arm/board/arm_fpga/include/plat_macros.S b/plat/arm/board/arm_fpga/include/plat_macros.S
new file mode 100644
index 0000000..44cddeb
--- /dev/null
+++ b/plat/arm/board/arm_fpga/include/plat_macros.S
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+.macro plat_crash_print_regs
+.endm
+
+#endif
diff --git a/plat/arm/board/arm_fpga/include/platform_def.h b/plat/arm/board/arm_fpga/include/platform_def.h
new file mode 100644
index 0000000..5c8aff6
--- /dev/null
+++ b/plat/arm/board/arm_fpga/include/platform_def.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include <plat/common/common_def.h>
+#include <platform_def.h>
+#include "../fpga_def.h"
+
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+
+#define PLATFORM_LINKER_ARCH aarch64
+
+#define PLATFORM_STACK_SIZE UL(0x800)
+
+#define CACHE_WRITEBACK_SHIFT U(6)
+#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
+
+#define PLATFORM_CORE_COUNT \
+ (FPGA_MAX_CLUSTER_COUNT * FPGA_MAX_CPUS_PER_CLUSTER * FPGA_MAX_PE_PER_CPU)
+
+#define PLAT_NUM_PWR_DOMAINS (FPGA_MAX_CLUSTER_COUNT + \
+ PLATFORM_CORE_COUNT) + 1
+
+#if !ENABLE_PIE
+#define BL31_BASE UL(0x80000000)
+#define BL31_LIMIT UL(0x80100000)
+#else
+#define BL31_BASE UL(0x0)
+#define BL31_LIMIT UL(0x01000000)
+#endif
+
+#define GICD_BASE 0x30000000
+#define GICR_BASE 0x30040000
+
+#define PLAT_SDEI_NORMAL_PRI 0x70
+
+#define ARM_IRQ_SEC_PHY_TIMER 29
+
+#define ARM_IRQ_SEC_SGI_0 8
+#define ARM_IRQ_SEC_SGI_1 9
+#define ARM_IRQ_SEC_SGI_2 10
+#define ARM_IRQ_SEC_SGI_3 11
+#define ARM_IRQ_SEC_SGI_4 12
+#define ARM_IRQ_SEC_SGI_5 13
+#define ARM_IRQ_SEC_SGI_6 14
+#define ARM_IRQ_SEC_SGI_7 15
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLATFORM_G1S_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE)
+
+#define PLATFORM_G0_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE)
+
+#define PLAT_MAX_RET_STATE 1
+#define PLAT_MAX_OFF_STATE 2
+
+#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
+
+#define PLAT_FPGA_HOLD_ENTRY_SHIFT 3
+#define PLAT_FPGA_HOLD_STATE_WAIT 0
+#define PLAT_FPGA_HOLD_STATE_GO 1
+
+#define PLAT_FPGA_CONSOLE_BAUDRATE 38400
+
+#endif
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
new file mode 100644
index 0000000..b4f38fa
--- /dev/null
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -0,0 +1,93 @@
+#
+# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+RESET_TO_BL31 := 1
+ifeq (${RESET_TO_BL31}, 0)
+$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
+endif
+
+ifeq (${ENABLE_PIE}, 1)
+override SEPARATE_CODE_AND_RODATA := 1
+endif
+
+CTX_INCLUDE_AARCH32_REGS := 0
+ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1)
+$(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled")
+endif
+
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+$(error "TRUSTED_BOARD_BOOT must be disabled")
+endif
+
+ifndef PRELOADED_BL33_BASE
+$(error "PRELOADED_BL33_BASE is not set")
+endif
+
+ifndef FPGA_PRELOADED_DTB_BASE
+$(error "FPGA_PRELOADED_DTB_BASE is not set")
+else
+$(eval $(call add_define,FPGA_PRELOADED_DTB_BASE))
+endif
+
+# Treating this as a memory-constrained port for now
+USE_COHERENT_MEM := 0
+
+# This can be overridden depending on CPU(s) used in the FPGA image
+HW_ASSISTED_COHERENCY := 1
+
+FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
+
+# select a different set of CPU files, depending on whether we compile for
+# hardware assisted coherency cores or not
+ifeq (${HW_ASSISTED_COHERENCY}, 0)
+# Cores used without DSU
+ FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
+ lib/cpus/aarch64/cortex_a53.S \
+ lib/cpus/aarch64/cortex_a57.S \
+ lib/cpus/aarch64/cortex_a72.S \
+ lib/cpus/aarch64/cortex_a73.S
+else
+# AArch64-only cores
+ FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \
+ lib/cpus/aarch64/cortex_a76ae.S \
+ lib/cpus/aarch64/cortex_a77.S \
+ lib/cpus/aarch64/neoverse_n1.S \
+ lib/cpus/aarch64/neoverse_e1.S \
+ lib/cpus/aarch64/neoverse_zeus.S \
+ lib/cpus/aarch64/cortex_hercules.S \
+ lib/cpus/aarch64/cortex_hercules_ae.S \
+ lib/cpus/aarch64/cortex_a65.S \
+ lib/cpus/aarch64/cortex_a65ae.S
+# AArch64/AArch32 cores
+ FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
+ lib/cpus/aarch64/cortex_a75.S
+endif
+
+FPGA_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
+ drivers/arm/gic/v3/gicdv3_helpers.c \
+ drivers/arm/gic/v3/gicrv3_helpers.c \
+ drivers/arm/gic/v3/gicv3_main.c \
+ drivers/arm/gic/v3/gic600.c \
+ drivers/arm/gic/common/gic_common.c \
+ plat/common/plat_gicv3.c \
+ plat/arm/board/arm_fpga/fpga_gicv3.c
+
+PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
+
+PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
+
+BL31_SOURCES += drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ drivers/arm/pl011/${ARCH}/pl011_console.S \
+ plat/common/plat_psci_common.c \
+ plat/arm/board/arm_fpga/fpga_pm.c \
+ plat/arm/board/arm_fpga/fpga_topology.c \
+ plat/arm/board/arm_fpga/fpga_console.c \
+ plat/arm/board/arm_fpga/fpga_bl31_setup.c \
+ ${FPGA_CPU_LIBS} \
+ ${FPGA_GIC_SOURCES}
+
+all: bl31
diff --git a/plat/arm/board/corstone700/include/platform_def.h b/plat/arm/board/corstone700/include/platform_def.h
index 0fb74e4..cc4dc3a 100644
--- a/plat/arm/board/corstone700/include/platform_def.h
+++ b/plat/arm/board/corstone700/include/platform_def.h
@@ -9,9 +9,9 @@
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
-
#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/common/arm_spm_def.h>
+#include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h>
/* PL011 UART related constants */
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index 61bd69c..98ea857 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -67,6 +67,19 @@
*/
mbedtls_heap_addr = <0x0 0x0>;
mbedtls_heap_size = <0x0>;
+
+#if MEASURED_BOOT
+ /* BL2 image hash calculated by BL1 */
+ bl2_hash_data = [
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+#if BL2_HASH_SIZE > 32
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+#if BL2_HASH_SIZE > 48
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+#endif /* > 48 */
+#endif /* > 32 */
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
+#endif /* MEASURED_BOOT */
};
/*
@@ -75,6 +88,7 @@
* stored in machine order (little endian).
* This will be fixed in future.
*/
+#if ARM_IO_IN_DTB
arm-io_policies {
fip-handles {
compatible = "arm,io-fip-handle";
@@ -99,6 +113,7 @@
nt_fw_content_cert_uuid = <0xf3c1c48e 0x11e4635d 0xee87a9a7 0xa73fb240>;
};
};
+#endif /* ARM_IO_IN_DTB */
secure-partitions {
compatible = "arm,sp";
diff --git a/plat/arm/board/fvp/fvp_bl1_setup.c b/plat/arm/board/fvp/fvp_bl1_setup.c
index 8f6170d..d13cc81 100644
--- a/plat/arm/board/fvp/fvp_bl1_setup.c
+++ b/plat/arm/board/fvp/fvp_bl1_setup.c
@@ -1,9 +1,12 @@
/*
- * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <assert.h>
+
+#include <bl1/bl1.h>
#include <common/tbbr/tbbr_img_def.h>
#include <drivers/arm/smmu_v3.h>
#include <drivers/arm/sp805.h>
@@ -64,3 +67,52 @@
while (1)
wfi();
}
+
+#if MEASURED_BOOT
+/*
+ * Implementation for bl1_plat_handle_post_image_load(). This function
+ * populates the default arguments to BL2. The BL2 memory layout structure
+ * is allocated and the calculated layout is populated in arg1 to BL2.
+ */
+int bl1_plat_handle_post_image_load(unsigned int image_id)
+{
+ meminfo_t *bl2_tzram_layout;
+ meminfo_t *bl1_tzram_layout;
+ image_desc_t *image_desc;
+ entry_point_info_t *ep_info;
+
+ if (image_id != BL2_IMAGE_ID) {
+ return 0;
+ }
+
+ /* Get the image descriptor */
+ image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
+ assert(image_desc != NULL);
+
+ /* Calculate BL2 hash and set it in TB_FW_CONFIG */
+ arm_bl1_set_bl2_hash(image_desc);
+
+ /* Get the entry point info */
+ ep_info = &image_desc->ep_info;
+
+ /* Find out how much free trusted ram remains after BL1 load */
+ bl1_tzram_layout = bl1_plat_sec_mem_layout();
+
+ /*
+ * Create a new layout of memory for BL2 as seen by BL1 i.e.
+ * tell it the amount of total and free memory available.
+ * This layout is created at the first free address visible
+ * to BL2. BL2 will read the memory layout before using its
+ * memory for other purposes.
+ */
+ bl2_tzram_layout = (meminfo_t *)bl1_tzram_layout->total_base;
+
+ bl1_calc_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
+
+ ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout;
+
+ VERBOSE("BL1: BL2 memory layout address = %p\n",
+ (void *)bl2_tzram_layout);
+ return 0;
+}
+#endif /* MEASURED_BOOT */
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 4e20632..15cd691 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -10,11 +10,6 @@
# Use the SP804 timer instead of the generic one
FVP_USE_SP804_TIMER := 0
-# Use fconf based io for FVP
-ifeq ($(BL2_AT_EL3), 0)
-USE_FCONF_BASED_IO := 1
-endif
-
# Default cluster count for FVP
FVP_CLUSTER_COUNT := 2
@@ -53,21 +48,23 @@
$(eval $(call add_define,FVP_INTERCONNECT_DRIVER))
+# Choose the GIC sources depending upon the how the FVP will be invoked
+ifeq (${FVP_USE_GIC_DRIVER},$(filter ${FVP_USE_GIC_DRIVER},FVP_GICV3 FVP_GIC600))
+ ifeq (${FVP_USE_GIC_DRIVER}, FVP_GIC600)
+ GICV3_IMPL := GIC600
+ endif
+
-FVP_GICV3_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
+# GIC500 is the default option in case GICV3_IMPL is not set
+
+GICV3_OVERRIDE_DISTIF_PWR_OPS := 1
+
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+FVP_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
plat/arm/common/arm_gicv3.c
-# Choose the GIC sources depending upon the how the FVP will be invoked
-ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3)
-FVP_GIC_SOURCES := ${FVP_GICV3_SOURCES} \
- drivers/arm/gic/v3/gic500.c
-else ifeq (${FVP_USE_GIC_DRIVER},FVP_GIC600)
-FVP_GIC_SOURCES := ${FVP_GICV3_SOURCES} \
- drivers/arm/gic/v3/gic600.c
else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2)
FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
@@ -300,30 +297,30 @@
# Enable the dynamic translation tables library.
ifeq (${ARCH},aarch32)
ifeq (${RESET_TO_SP_MIN},1)
- BL32_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
+ BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
else # AArch64
ifeq (${RESET_TO_BL31},1)
- BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
+ BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
ifeq (${SPD},trusty)
- BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
+ BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
endif
ifeq (${ALLOW_RO_XLAT_TABLES}, 1)
ifeq (${ARCH},aarch32)
- BL32_CFLAGS += -DPLAT_RO_XLAT_TABLES=1
+ BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1
else # AArch64
- BL31_CFLAGS += -DPLAT_RO_XLAT_TABLES=1
+ BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1
ifeq (${SPD},tspd)
- BL32_CFLAGS += -DPLAT_RO_XLAT_TABLES=1
+ BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1
endif
endif
endif
ifeq (${USE_DEBUGFS},1)
- BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
+ BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
# Add support for platform supplied linker script for BL31 build
diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h
index 1b07a9b..70a12ea 100644
--- a/plat/arm/board/fvp_ve/include/platform_def.h
+++ b/plat/arm/board/fvp_ve/include/platform_def.h
@@ -11,6 +11,7 @@
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/arm/board/common/v2m_def.h>
+#include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h>
#include "../fvp_ve_def.h"
diff --git a/plat/arm/board/fvp_ve/platform.mk b/plat/arm/board/fvp_ve/platform.mk
index 7883719..9ada86b 100644
--- a/plat/arm/board/fvp_ve/platform.mk
+++ b/plat/arm/board/fvp_ve/platform.mk
@@ -42,6 +42,7 @@
plat/arm/common/arm_err.c \
plat/arm/board/fvp_ve/fvp_ve_err.c \
plat/arm/common/arm_io_storage.c \
+ plat/arm/common/fconf/arm_fconf_io.c \
drivers/cfi/v2m/v2m_flash.c \
plat/arm/board/fvp_ve/${ARCH}/fvp_ve_helpers.S \
plat/arm/board/fvp_ve/fvp_ve_bl1_setup.c \
@@ -63,6 +64,7 @@
plat/arm/common/arm_err.c \
plat/arm/board/fvp_ve/fvp_ve_err.c \
plat/arm/common/arm_io_storage.c \
+ plat/arm/common/fconf/arm_fconf_io.c \
plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c \
plat/arm/common/arm_image_load.c \
common/desc_image_load.c \
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index f07c1b1..dfdefa1 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -147,19 +147,19 @@
# Enable the dynamic translation tables library.
ifeq (${ARCH},aarch32)
ifeq (${RESET_TO_SP_MIN},1)
- BL32_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
+ BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
else
ifeq (${RESET_TO_BL31},1)
- BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
+ BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
endif
endif
ifeq (${ALLOW_RO_XLAT_TABLES}, 1)
ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1)
- BL32_CFLAGS += -DPLAT_RO_XLAT_TABLES=1
+ BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1
else
- BL31_CFLAGS += -DPLAT_RO_XLAT_TABLES=1
+ BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES=1
endif
endif
diff --git a/plat/arm/board/n1sdp/platform.mk b/plat/arm/board/n1sdp/platform.mk
index 5856c9f..44f7b8a 100644
--- a/plat/arm/board/n1sdp/platform.mk
+++ b/plat/arm/board/n1sdp/platform.mk
@@ -14,16 +14,16 @@
N1SDP_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
+# GIC-600 configuration
+GICV3_IMPL := GIC600
+GICV3_IMPL_GIC600_MULTICHIP := 1
-N1SDP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- drivers/arm/gic/v3/gic600_multichip.c \
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+N1SDP_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
plat/arm/common/arm_gicv3.c \
- drivers/arm/gic/v3/gic600.c
PLAT_BL_COMMON_SOURCES := ${N1SDP_BASE}/n1sdp_plat.c \
${N1SDP_BASE}/aarch64/n1sdp_helper.S
diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk
index 135676d..1daf85f 100644
--- a/plat/arm/board/rdn1edge/platform.mk
+++ b/plat/arm/board/rdn1edge/platform.mk
@@ -4,6 +4,9 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+# GIC-600 configuration
+GICV3_IMPL_GIC600_MULTICHIP := 1
+
include plat/arm/css/sgi/sgi-common.mk
RDN1EDGE_BASE = plat/arm/board/rdn1edge
@@ -26,7 +29,6 @@
${RDN1EDGE_BASE}/rdn1edge_plat.c \
${RDN1EDGE_BASE}/rdn1edge_topology.c \
drivers/cfi/v2m/v2m_flash.c \
- drivers/arm/gic/v3/gic600_multichip.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
@@ -36,7 +38,7 @@
endif
# Enable dynamic addition of MMAP regions in BL31
-BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
+BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
# Add the FDT_SOURCES and options for Dynamic Config
FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_fw_config.dts
diff --git a/plat/arm/board/sgm775/fdts/sgm775_fw_config.dts b/plat/arm/board/sgm775/fdts/sgm775_fw_config.dts
index a0d0ea9..c5702ca 100644
--- a/plat/arm/board/sgm775/fdts/sgm775_fw_config.dts
+++ b/plat/arm/board/sgm775/fdts/sgm775_fw_config.dts
@@ -18,12 +18,6 @@
max-size = <0x200>;
id = <TB_FW_CONFIG_ID>;
};
-
- hw-config {
- load-address = <0x0 0x83000000>;
- max-size = <0x01000000>;
- id = <HW_CONFIG_ID>;
- };
};
tb_fw-config {
@@ -31,5 +25,17 @@
/* Disable authentication for development */
disable_auth = <0x0>;
+
+ /*
+ * The following two entries are placeholders for Mbed TLS
+ * heap information. The default values don't matter since
+ * they will be overwritten by BL1.
+ * In case of having shared Mbed TLS heap between BL1 and BL2,
+ * BL1 will populate these two properties with the respective
+ * info about the shared heap. This info will be available for
+ * BL2 in order to locate and re-use the heap.
+ */
+ mbedtls_heap_addr = <0x0 0x0>;
+ mbedtls_heap_size = <0x0>;
};
};
diff --git a/plat/arm/board/sgm775/platform.mk b/plat/arm/board/sgm775/platform.mk
index 355b9ee..57edb92 100644
--- a/plat/arm/board/sgm775/platform.mk
+++ b/plat/arm/board/sgm775/platform.mk
@@ -8,7 +8,12 @@
SGM775_BASE= plat/arm/board/sgm775
-FDT_SOURCES += ${SGM775_BASE}/fdts/sgm775_fw_config.dts
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES += ${SGM775_BASE}/fdts/${PLAT}_fw_config.dts
+TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
+
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
PLAT_INCLUDES +=-I${SGM775_BASE}/include/
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index d9fc84e..6c3f64f 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -205,7 +205,7 @@
******************************************************************************/
int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
{
-#if defined(SPD_spmd)
+#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
/* For Secure Partitions we don't need post processing */
if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) &&
(image_id < MAX_NUMBER_IDS)) {
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 65f6bf3..3b0c39d 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -177,14 +177,12 @@
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
endif
-ifeq (${USE_FCONF_BASED_IO}, 0)
-ARM_IO_SOURCES += plat/arm/common/arm_io_storage.c
-else
-ARM_IO_SOURCES += plat/arm/common/arm_fconf_io_storage.c \
+ARM_IO_SOURCES += plat/arm/common/arm_io_storage.c \
plat/arm/common/fconf/arm_fconf_io.c
ifeq (${SPD},spmd)
-ARM_IO_SOURCES += plat/arm/common/fconf/arm_fconf_sp.c
-endif
+ ifeq (${SPMD_SPM_AT_SEL2},1)
+ ARM_IO_SOURCES += plat/arm/common/fconf/arm_fconf_sp.c
+ endif
endif
BL1_SOURCES += drivers/io/io_fip.c \
diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c
index df75307..ffa2a64 100644
--- a/plat/arm/common/arm_dyn_cfg.c
+++ b/plat/arm/common/arm_dyn_cfg.c
@@ -15,6 +15,10 @@
#include <common/tbbr/tbbr_img_def.h>
#if TRUSTED_BOARD_BOOT
#include <drivers/auth/mbedtls/mbedtls_config.h>
+#if MEASURED_BOOT
+#include <drivers/auth/crypto_mod.h>
+#include <mbedtls/md.h>
+#endif
#endif
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
@@ -87,7 +91,7 @@
* the default heap's address and size.
*/
- /* fconf FW_CONFIG and TB_FW_CONFIG are currently the same DTB*/
+ /* fconf FW_CONFIG and TB_FW_CONFIG are currently the same DTB */
tb_fw_cfg_dtb = FCONF_GET_PROPERTY(fconf, dtb, base_addr);
if ((tb_fw_cfg_dtb != 0UL) && (mbedtls_heap_addr != NULL)) {
@@ -100,15 +104,68 @@
ERROR("BL1: unable to write shared Mbed TLS heap information to DTB\n");
panic();
}
+#if !MEASURED_BOOT
/*
* Ensure that the info written to the DTB is visible to other
* images. It's critical because BL2 won't be able to proceed
* without the heap info.
+ *
+ * In MEASURED_BOOT case flushing is done in
+ * arm_bl1_set_bl2_hash() function which is called after heap
+ * information is written in the DTB.
*/
flush_dcache_range(tb_fw_cfg_dtb, fdt_totalsize(dtb));
+#endif /* !MEASURED_BOOT */
}
}
+#if MEASURED_BOOT
+/*
+ * Puts the BL2 hash data to TB_FW_CONFIG DTB.
+ * Executed only from BL1.
+ */
+void arm_bl1_set_bl2_hash(image_desc_t *image_desc)
+{
+ unsigned char hash_data[MBEDTLS_MD_MAX_SIZE];
+ image_info_t image_info = image_desc->image_info;
+ uintptr_t tb_fw_cfg_dtb;
+ int err;
+
+ /* fconf FW_CONFIG and TB_FW_CONFIG are currently the same DTB */
+ tb_fw_cfg_dtb = FCONF_GET_PROPERTY(fconf, dtb, base_addr);
+
+ /*
+ * If tb_fw_cfg_dtb==NULL then DTB is not present for the current
+ * platform. As such, we cannot write to the DTB at all and pass
+ * measured data.
+ */
+ if (tb_fw_cfg_dtb == 0UL) {
+ panic();
+ }
+
+ /* Calculate hash */
+ err = crypto_mod_calc_hash(MBEDTLS_MD_ID,
+ (void *)image_info.image_base,
+ image_info.image_size, hash_data);
+ if (err != 0) {
+ ERROR("BL1: unable to calculate BL2 hash\n");
+ panic();
+ }
+
+ err = arm_set_bl2_hash_info((void *)tb_fw_cfg_dtb, hash_data);
+ if (err < 0) {
+ ERROR("BL1: unable to write BL2 hash data to DTB\n");
+ panic();
+ }
+
+ /*
+ * Ensure that the info written to the DTB is visible to other
+ * images. It's critical because BL2 won't be able to proceed
+ * without the heap info and its hash data.
+ */
+ flush_dcache_range(tb_fw_cfg_dtb, fdt_totalsize((void *)tb_fw_cfg_dtb));
+}
+#endif /* MEASURED_BOOT */
#endif /* TRUSTED_BOARD_BOOT */
/*
diff --git a/plat/arm/common/arm_dyn_cfg_helpers.c b/plat/arm/common/arm_dyn_cfg_helpers.c
index 909c4a6..f110e3b 100644
--- a/plat/arm/common/arm_dyn_cfg_helpers.c
+++ b/plat/arm/common/arm_dyn_cfg_helpers.c
@@ -15,6 +15,12 @@
#define DTB_PROP_MBEDTLS_HEAP_ADDR "mbedtls_heap_addr"
#define DTB_PROP_MBEDTLS_HEAP_SIZE "mbedtls_heap_size"
+#if MEASURED_BOOT
+#define DTB_PROP_BL2_HASH_DATA "bl2_hash_data"
+
+static int dtb_root = -1;
+#endif /* MEASURED_BOOT */
+
/*******************************************************************************
* Validate the tb_fw_config is a valid DTB file and returns the node offset
* to "arm,tb_fw" property.
@@ -57,17 +63,18 @@
*
* Returns:
* 0 = success
- * 1 = error
+ * -1 = error
*/
int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr, size_t heap_size)
{
- int err, dtb_root;
-
+#if !MEASURED_BOOT
+ int dtb_root;
+#endif
/*
* Verify that the DTB is valid, before attempting to write to it,
* and get the DTB root node.
*/
- err = arm_dyn_tb_fw_cfg_init(dtb, &dtb_root);
+ int err = arm_dyn_tb_fw_cfg_init(dtb, &dtb_root);
if (err < 0) {
ERROR("Invalid TB_FW_CONFIG loaded. Unable to get root node\n");
return -1;
@@ -98,3 +105,26 @@
return 0;
}
+
+#if MEASURED_BOOT
+/*
+ * This function writes the BL2 hash data in HW_FW_CONFIG DTB.
+ * When it is called, it is guaranteed that a DTB is available.
+ *
+ * This function is supposed to be called only by BL1.
+ *
+ * Returns:
+ * 0 = success
+ * < 0 = error
+ */
+int arm_set_bl2_hash_info(void *dtb, void *data)
+{
+ assert(dtb_root >= 0);
+
+ /*
+ * Write the BL2 hash data in the DTB.
+ */
+ return fdtw_write_inplace_bytes(dtb, dtb_root, DTB_PROP_BL2_HASH_DATA,
+ TCG_DIGEST_SIZE, data);
+}
+#endif /* MEASURED_BOOT */
diff --git a/plat/arm/common/arm_fconf_io_storage.c b/plat/arm/common/arm_fconf_io_storage.c
deleted file mode 100644
index 6fcfbd6..0000000
--- a/plat/arm/common/arm_fconf_io_storage.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2015-2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <common/debug.h>
-#include <drivers/io/io_driver.h>
-#include <drivers/io/io_fip.h>
-#include <drivers/io/io_memmap.h>
-#include <drivers/io/io_storage.h>
-#include <lib/utils.h>
-
-#include <plat/arm/common/arm_fconf_getter.h>
-#include <plat/arm/common/arm_fconf_io_storage.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-
-/* IO devices */
-static const io_dev_connector_t *fip_dev_con;
-uintptr_t fip_dev_handle;
-static const io_dev_connector_t *memmap_dev_con;
-uintptr_t memmap_dev_handle;
-
-/* Weak definitions may be overridden in specific ARM standard platform */
-#pragma weak plat_arm_io_setup
-#pragma weak plat_arm_get_alt_image_source
-
-int open_fip(const uintptr_t spec)
-{
- int result;
- uintptr_t local_image_handle;
-
- /* See if a Firmware Image Package is available */
- result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
- if (result == 0) {
- result = io_open(fip_dev_handle, spec, &local_image_handle);
- if (result == 0) {
- VERBOSE("Using FIP\n");
- io_close(local_image_handle);
- }
- }
- return result;
-}
-
-int open_memmap(const uintptr_t spec)
-{
- int result;
- uintptr_t local_image_handle;
-
- result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
- if (result == 0) {
- result = io_open(memmap_dev_handle, spec, &local_image_handle);
- if (result == 0) {
- VERBOSE("Using Memmap\n");
- io_close(local_image_handle);
- }
- }
- return result;
-}
-
-int arm_io_setup(void)
-{
- int io_result;
-
- io_result = register_io_dev_fip(&fip_dev_con);
- if (io_result < 0) {
- return io_result;
- }
-
- io_result = register_io_dev_memmap(&memmap_dev_con);
- if (io_result < 0) {
- return io_result;
- }
-
- /* Open connections to devices and cache the handles */
- io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
- &fip_dev_handle);
- if (io_result < 0) {
- return io_result;
- }
-
- io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
- &memmap_dev_handle);
-
- return io_result;
-}
-
-void plat_arm_io_setup(void)
-{
- int err;
-
- err = arm_io_setup();
- if (err < 0) {
- panic();
- }
-}
-
-int plat_arm_get_alt_image_source(
- unsigned int image_id __unused,
- uintptr_t *dev_handle __unused,
- uintptr_t *image_spec __unused)
-{
- /* By default do not try an alternative */
- return -ENOENT;
-}
-
-/* Return an IO device handle and specification which can be used to access
- * an image. Use this to enforce platform load policy */
-int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
- uintptr_t *image_spec)
-{
- int result;
- const struct plat_io_policy *policy;
-
- assert(image_id < MAX_NUMBER_IDS);
-
- policy = FCONF_GET_PROPERTY(arm, io_policies, image_id);
- result = policy->check(policy->image_spec);
- if (result == 0) {
- *image_spec = policy->image_spec;
- *dev_handle = *(policy->dev_handle);
- } else {
- VERBOSE("Trying alternative IO\n");
- result = plat_arm_get_alt_image_source(image_id, dev_handle,
- image_spec);
- }
-
- return result;
-}
-
-/*
- * See if a Firmware Image Package is available,
- * by checking if TOC is valid or not.
- */
-bool arm_io_is_toc_valid(void)
-{
- return (io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID) == 0);
-}
diff --git a/plat/arm/common/arm_image_load.c b/plat/arm/common/arm_image_load.c
index 593199d..ed7f1f5 100644
--- a/plat/arm/common/arm_image_load.c
+++ b/plat/arm/common/arm_image_load.c
@@ -32,11 +32,11 @@
next_bl_params_cpy_ptr);
}
-#if defined(SPD_spmd)
+#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
/*******************************************************************************
* This function appends Secure Partitions to list of loadable images.
******************************************************************************/
-void plat_add_sp_images_load_info(struct bl_load_info *load_info)
+static void plat_add_sp_images_load_info(struct bl_load_info *load_info)
{
bl_load_info_node_t *node_info = load_info->head;
unsigned int index = 0;
@@ -78,7 +78,7 @@
******************************************************************************/
struct bl_load_info *plat_get_bl_image_load_info(void)
{
-#if defined(SPD_spmd)
+#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
bl_load_info_t *bl_load_info;
bl_load_info = get_bl_load_info_from_mem_params_desc();
diff --git a/plat/arm/common/arm_io_storage.c b/plat/arm/common/arm_io_storage.c
index f5d8a41..6fcfbd6 100644
--- a/plat/arm/common/arm_io_storage.c
+++ b/plat/arm/common/arm_io_storage.c
@@ -1,13 +1,10 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
-#include <string.h>
-
-#include <platform_def.h>
#include <common/debug.h>
#include <drivers/io/io_driver.h>
@@ -15,249 +12,24 @@
#include <drivers/io/io_memmap.h>
#include <drivers/io/io_storage.h>
#include <lib/utils.h>
+
+#include <plat/arm/common/arm_fconf_getter.h>
+#include <plat/arm/common/arm_fconf_io_storage.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
-#include <tools_share/firmware_image_package.h>
+#include <platform_def.h>
/* IO devices */
static const io_dev_connector_t *fip_dev_con;
-static uintptr_t fip_dev_handle;
+uintptr_t fip_dev_handle;
static const io_dev_connector_t *memmap_dev_con;
-static uintptr_t memmap_dev_handle;
-
-static const io_block_spec_t fip_block_spec = {
- .offset = PLAT_ARM_FIP_BASE,
- .length = PLAT_ARM_FIP_MAX_SIZE
-};
-
-static const io_uuid_spec_t bl2_uuid_spec = {
- .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
-};
-
-static const io_uuid_spec_t scp_bl2_uuid_spec = {
- .uuid = UUID_SCP_FIRMWARE_SCP_BL2,
-};
-
-static const io_uuid_spec_t bl31_uuid_spec = {
- .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
-};
-
-static const io_uuid_spec_t bl32_uuid_spec = {
- .uuid = UUID_SECURE_PAYLOAD_BL32,
-};
-
-static const io_uuid_spec_t bl32_extra1_uuid_spec = {
- .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
-};
-
-static const io_uuid_spec_t bl32_extra2_uuid_spec = {
- .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
-};
-
-static const io_uuid_spec_t bl33_uuid_spec = {
- .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
-};
-
-static const io_uuid_spec_t tb_fw_config_uuid_spec = {
- .uuid = UUID_TB_FW_CONFIG,
-};
-
-static const io_uuid_spec_t hw_config_uuid_spec = {
- .uuid = UUID_HW_CONFIG,
-};
-
-static const io_uuid_spec_t soc_fw_config_uuid_spec = {
- .uuid = UUID_SOC_FW_CONFIG,
-};
-
-static const io_uuid_spec_t tos_fw_config_uuid_spec = {
- .uuid = UUID_TOS_FW_CONFIG,
-};
-
-static const io_uuid_spec_t nt_fw_config_uuid_spec = {
- .uuid = UUID_NT_FW_CONFIG,
-};
-
-#if TRUSTED_BOARD_BOOT
-static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
- .uuid = UUID_TRUSTED_BOOT_FW_CERT,
-};
-
-static const io_uuid_spec_t trusted_key_cert_uuid_spec = {
- .uuid = UUID_TRUSTED_KEY_CERT,
-};
-
-static const io_uuid_spec_t scp_fw_key_cert_uuid_spec = {
- .uuid = UUID_SCP_FW_KEY_CERT,
-};
-
-static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = {
- .uuid = UUID_SOC_FW_KEY_CERT,
-};
-
-static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = {
- .uuid = UUID_TRUSTED_OS_FW_KEY_CERT,
-};
-
-static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = {
- .uuid = UUID_NON_TRUSTED_FW_KEY_CERT,
-};
-
-static const io_uuid_spec_t scp_fw_cert_uuid_spec = {
- .uuid = UUID_SCP_FW_CONTENT_CERT,
-};
-
-static const io_uuid_spec_t soc_fw_cert_uuid_spec = {
- .uuid = UUID_SOC_FW_CONTENT_CERT,
-};
-
-static const io_uuid_spec_t tos_fw_cert_uuid_spec = {
- .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT,
-};
-
-static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
- .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT,
-};
-#endif /* TRUSTED_BOARD_BOOT */
-
-
-static int open_fip(const uintptr_t spec);
-static int open_memmap(const uintptr_t spec);
-
-struct plat_io_policy {
- uintptr_t *dev_handle;
- uintptr_t image_spec;
- int (*check)(const uintptr_t spec);
-};
-
-/* By default, ARM platforms load images from the FIP */
-static const struct plat_io_policy policies[] = {
- [FIP_IMAGE_ID] = {
- &memmap_dev_handle,
- (uintptr_t)&fip_block_spec,
- open_memmap
- },
- [BL2_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl2_uuid_spec,
- open_fip
- },
- [SCP_BL2_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&scp_bl2_uuid_spec,
- open_fip
- },
- [BL31_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl31_uuid_spec,
- open_fip
- },
- [BL32_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl32_uuid_spec,
- open_fip
- },
- [BL32_EXTRA1_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl32_extra1_uuid_spec,
- open_fip
- },
- [BL32_EXTRA2_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl32_extra2_uuid_spec,
- open_fip
- },
- [BL33_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl33_uuid_spec,
- open_fip
- },
- [TB_FW_CONFIG_ID] = {
- &fip_dev_handle,
- (uintptr_t)&tb_fw_config_uuid_spec,
- open_fip
- },
- [HW_CONFIG_ID] = {
- &fip_dev_handle,
- (uintptr_t)&hw_config_uuid_spec,
- open_fip
- },
- [SOC_FW_CONFIG_ID] = {
- &fip_dev_handle,
- (uintptr_t)&soc_fw_config_uuid_spec,
- open_fip
- },
- [TOS_FW_CONFIG_ID] = {
- &fip_dev_handle,
- (uintptr_t)&tos_fw_config_uuid_spec,
- open_fip
- },
- [NT_FW_CONFIG_ID] = {
- &fip_dev_handle,
- (uintptr_t)&nt_fw_config_uuid_spec,
- open_fip
- },
-#if TRUSTED_BOARD_BOOT
- [TRUSTED_BOOT_FW_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&tb_fw_cert_uuid_spec,
- open_fip
- },
- [TRUSTED_KEY_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&trusted_key_cert_uuid_spec,
- open_fip
- },
- [SCP_FW_KEY_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&scp_fw_key_cert_uuid_spec,
- open_fip
- },
- [SOC_FW_KEY_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&soc_fw_key_cert_uuid_spec,
- open_fip
- },
- [TRUSTED_OS_FW_KEY_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&tos_fw_key_cert_uuid_spec,
- open_fip
- },
- [NON_TRUSTED_FW_KEY_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&nt_fw_key_cert_uuid_spec,
- open_fip
- },
- [SCP_FW_CONTENT_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&scp_fw_cert_uuid_spec,
- open_fip
- },
- [SOC_FW_CONTENT_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&soc_fw_cert_uuid_spec,
- open_fip
- },
- [TRUSTED_OS_FW_CONTENT_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&tos_fw_cert_uuid_spec,
- open_fip
- },
- [NON_TRUSTED_FW_CONTENT_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&nt_fw_cert_uuid_spec,
- open_fip
- },
-#endif /* TRUSTED_BOARD_BOOT */
-};
-
+uintptr_t memmap_dev_handle;
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak plat_arm_io_setup
#pragma weak plat_arm_get_alt_image_source
-
-static int open_fip(const uintptr_t spec)
+int open_fip(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
@@ -274,8 +46,7 @@
return result;
}
-
-static int open_memmap(const uintptr_t spec)
+int open_memmap(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
@@ -291,7 +62,6 @@
return result;
}
-
int arm_io_setup(void)
{
int io_result;
@@ -346,9 +116,9 @@
int result;
const struct plat_io_policy *policy;
- assert(image_id < ARRAY_SIZE(policies));
+ assert(image_id < MAX_NUMBER_IDS);
- policy = &policies[image_id];
+ policy = FCONF_GET_PROPERTY(arm, io_policies, image_id);
result = policy->check(policy->image_spec);
if (result == 0) {
*image_spec = policy->image_spec;
@@ -370,4 +140,3 @@
{
return (io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID) == 0);
}
-
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c
index 017af79..6ebc467 100644
--- a/plat/arm/common/fconf/arm_fconf_io.c
+++ b/plat/arm/common/fconf/arm_fconf_io.c
@@ -25,8 +25,31 @@
const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = {
[BL2_IMAGE_ID] = {UUID_TRUSTED_BOOT_FIRMWARE_BL2},
[TB_FW_CONFIG_ID] = {UUID_TB_FW_CONFIG},
+#if !ARM_IO_IN_DTB
+ [SCP_BL2_IMAGE_ID] = {UUID_SCP_FIRMWARE_SCP_BL2},
+ [BL31_IMAGE_ID] = {UUID_EL3_RUNTIME_FIRMWARE_BL31},
+ [BL32_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32},
+ [BL32_EXTRA1_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32_EXTRA1},
+ [BL32_EXTRA2_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32_EXTRA2},
+ [BL33_IMAGE_ID] = {UUID_NON_TRUSTED_FIRMWARE_BL33},
+ [HW_CONFIG_ID] = {UUID_HW_CONFIG},
+ [SOC_FW_CONFIG_ID] = {UUID_SOC_FW_CONFIG},
+ [TOS_FW_CONFIG_ID] = {UUID_TOS_FW_CONFIG},
+ [NT_FW_CONFIG_ID] = {UUID_NT_FW_CONFIG},
+#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT},
+#if !ARM_IO_IN_DTB
+ [TRUSTED_KEY_CERT_ID] = {UUID_TRUSTED_KEY_CERT},
+ [SCP_FW_KEY_CERT_ID] = {UUID_SCP_FW_KEY_CERT},
+ [SOC_FW_KEY_CERT_ID] = {UUID_SOC_FW_KEY_CERT},
+ [TRUSTED_OS_FW_KEY_CERT_ID] = {UUID_TRUSTED_OS_FW_KEY_CERT},
+ [NON_TRUSTED_FW_KEY_CERT_ID] = {UUID_NON_TRUSTED_FW_KEY_CERT},
+ [SCP_FW_CONTENT_CERT_ID] = {UUID_SCP_FW_CONTENT_CERT},
+ [SOC_FW_CONTENT_CERT_ID] = {UUID_SOC_FW_CONTENT_CERT},
+ [TRUSTED_OS_FW_CONTENT_CERT_ID] = {UUID_TRUSTED_OS_FW_CONTENT_CERT},
+ [NON_TRUSTED_FW_CONTENT_CERT_ID] = {UUID_NON_TRUSTED_FW_CONTENT_CERT},
+#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@@ -47,12 +70,111 @@
(uintptr_t)&arm_uuid_spec[TB_FW_CONFIG_ID],
open_fip
},
+#if !ARM_IO_IN_DTB
+ [SCP_BL2_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SCP_BL2_IMAGE_ID],
+ open_fip
+ },
+ [BL31_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[BL31_IMAGE_ID],
+ open_fip
+ },
+ [BL32_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[BL32_IMAGE_ID],
+ open_fip
+ },
+ [BL32_EXTRA1_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[BL32_EXTRA1_IMAGE_ID],
+ open_fip
+ },
+ [BL32_EXTRA2_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[BL32_EXTRA2_IMAGE_ID],
+ open_fip
+ },
+ [BL33_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[BL33_IMAGE_ID],
+ open_fip
+ },
+ [HW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[HW_CONFIG_ID],
+ open_fip
+ },
+ [SOC_FW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SOC_FW_CONFIG_ID],
+ open_fip
+ },
+ [TOS_FW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[TOS_FW_CONFIG_ID],
+ open_fip
+ },
+ [NT_FW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[NT_FW_CONFIG_ID],
+ open_fip
+ },
+#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&arm_uuid_spec[TRUSTED_BOOT_FW_CERT_ID],
open_fip
},
+#if !ARM_IO_IN_DTB
+ [TRUSTED_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[TRUSTED_KEY_CERT_ID],
+ open_fip
+ },
+ [SCP_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SCP_FW_KEY_CERT_ID],
+ open_fip
+ },
+ [SOC_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SOC_FW_KEY_CERT_ID],
+ open_fip
+ },
+ [TRUSTED_OS_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[TRUSTED_OS_FW_KEY_CERT_ID],
+ open_fip
+ },
+ [NON_TRUSTED_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[NON_TRUSTED_FW_KEY_CERT_ID],
+ open_fip
+ },
+ [SCP_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SCP_FW_CONTENT_CERT_ID],
+ open_fip
+ },
+ [SOC_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SOC_FW_CONTENT_CERT_ID],
+ open_fip
+ },
+ [TRUSTED_OS_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[TRUSTED_OS_FW_CONTENT_CERT_ID],
+ open_fip
+ },
+ [NON_TRUSTED_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[NON_TRUSTED_FW_CONTENT_CERT_ID],
+ open_fip
+ },
+#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@@ -138,6 +260,8 @@
return 0;
}
+#if ARM_IO_IN_DTB
FCONF_REGISTER_POPULATOR(TB_FW, arm_io, fconf_populate_arm_io_policies);
+#endif /* ARM_IO_IN_DTB */
#endif /* IMAGE_BL2 */
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index 9a482d0..8c8b231 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -56,7 +56,7 @@
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
* plus a little space for growth.
*/
-#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000
/*
* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
@@ -141,7 +141,7 @@
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
ARM_SHARED_RAM_BASE, \
ARM_SHARED_RAM_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE \
+ MT_NON_CACHEABLE | MT_RW | MT_SECURE \
)
#define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index ea5a563..2504581 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -22,15 +22,15 @@
PLAT_INCLUDES += -I${CSS_ENT_BASE}/include
-ENT_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- plat/common/plat_gicv3.c \
- plat/arm/common/arm_gicv3.c \
- drivers/arm/gic/v3/gic600.c
+# GIC-600 configuration
+GICV3_IMPL := GIC600
+
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+ENT_GIC_SOURCES := ${GICV3_SOURCES} \
+ plat/common/plat_gicv3.c \
+ plat/arm/common/arm_gicv3.c
PLAT_BL_COMMON_SOURCES += ${CSS_ENT_BASE}/sgi_plat.c \
${CSS_ENT_BASE}/aarch64/sgi_helper.S
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index fcb7e1f..a4aed00 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -75,7 +75,7 @@
{
if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_DANIEL_SID_VER_PART_NUM) {
- if (channel_id >= sizeof(rd_n1e1_edge_scmi_plat_info))
+ if (channel_id >= ARRAY_SIZE(rd_n1e1_edge_scmi_plat_info))
panic();
return &rd_n1e1_edge_scmi_plat_info[channel_id];
}
diff --git a/plat/arm/css/sgm/sgm-common.mk b/plat/arm/css/sgm/sgm-common.mk
index 49fc717..60e9fb2 100644
--- a/plat/arm/css/sgm/sgm-common.mk
+++ b/plat/arm/css/sgm/sgm-common.mk
@@ -22,15 +22,15 @@
INTERCONNECT_SOURCES := ${CSS_SGM_BASE}/sgm_interconnect.c
-SGM_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
+# GIC-600 configuration
+GICV3_IMPL := GIC600
+
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+SGM_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
- plat/arm/common/arm_gicv3.c \
- drivers/arm/gic/v3/gic600.c \
- drivers/arm/gic/v3/arm_gicv3_common.c
+ plat/arm/common/arm_gicv3.c
BL1_SOURCES += $(SGM_CPU_SOURCES) \
${INTERCONNECT_SOURCES} \
diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c
index bed8890..c32e59f 100644
--- a/plat/common/plat_psci_common.c
+++ b/plat/common/plat_psci_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -63,7 +63,6 @@
/*
* Capture timestamp before entering a low power state.
- * No cache maintenance is required when capturing the timestamp.
* Cache maintenance may be needed when reading these timestamps.
*/
void plat_psci_stat_accounting_start(
@@ -71,12 +70,11 @@
{
assert(state_info != NULL);
PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR,
- PMF_NO_CACHE_MAINT);
+ PMF_CACHE_MAINT);
}
/*
* Capture timestamp after exiting a low power state.
- * No cache maintenance is required when capturing the timestamp.
* Cache maintenance may be needed when reading these timestamps.
*/
void plat_psci_stat_accounting_stop(
@@ -84,7 +82,7 @@
{
assert(state_info != NULL);
PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR,
- PMF_NO_CACHE_MAINT);
+ PMF_CACHE_MAINT);
}
/*
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 5fa3003..3ead7b0 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -8,13 +8,10 @@
-Iplat/imx/imx8m/include \
-Iplat/imx/imx8m/imx8mm/include
-IMX_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- drivers/arm/gic/v3/arm_gicv3_common.c \
- drivers/arm/gic/v3/gic500.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/common/gic_common.c \
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+IMX_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
plat/common/plat_psci_common.c \
plat/imx/common/plat_imx8_gic.c
diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk
index e419f05..5461010 100644
--- a/plat/imx/imx8m/imx8mq/platform.mk
+++ b/plat/imx/imx8m/imx8mq/platform.mk
@@ -8,13 +8,10 @@
-Iplat/imx/imx8m/include \
-Iplat/imx/imx8m/imx8mq/include
-IMX_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- drivers/arm/gic/v3/arm_gicv3_common.c \
- drivers/arm/gic/v3/gic500.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/common/gic_common.c \
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+IMX_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
plat/common/plat_psci_common.c \
plat/imx/common/plat_imx8_gic.c
diff --git a/plat/imx/imx8qm/platform.mk b/plat/imx/imx8qm/platform.mk
index 20ee05b..f35fa00 100644
--- a/plat/imx/imx8qm/platform.mk
+++ b/plat/imx/imx8qm/platform.mk
@@ -7,13 +7,10 @@
PLAT_INCLUDES := -Iplat/imx/imx8qm/include \
-Iplat/imx/common/include \
-IMX_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- drivers/arm/gic/v3/arm_gicv3_common.c \
- drivers/arm/gic/v3/gic500.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/common/gic_common.c \
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+IMX_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
plat/common/plat_psci_common.c \
plat/imx/common/plat_imx8_gic.c
diff --git a/plat/imx/imx8qx/platform.mk b/plat/imx/imx8qx/platform.mk
index a823330..b25be07 100644
--- a/plat/imx/imx8qx/platform.mk
+++ b/plat/imx/imx8qx/platform.mk
@@ -7,13 +7,10 @@
PLAT_INCLUDES := -Iplat/imx/imx8qx/include \
-Iplat/imx/common/include \
-IMX_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- drivers/arm/gic/v3/arm_gicv3_common.c \
- drivers/arm/gic/v3/gic500.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/common/gic_common.c \
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+IMX_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
plat/imx/common/plat_imx8_gic.c
diff --git a/plat/marvell/a3700/common/a3700_common.mk b/plat/marvell/a3700/common/a3700_common.mk
index fd2b7ed..76c0677 100644
--- a/plat/marvell/a3700/common/a3700_common.mk
+++ b/plat/marvell/a3700/common/a3700_common.mk
@@ -78,14 +78,11 @@
# CCI-400
$(eval $(call add_define,USE_CCI))
-MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- drivers/arm/gic/v3/arm_gicv3_common.c \
- plat/common/plat_gicv3.c \
- drivers/arm/gic/v3/gic500.c
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+MARVELL_GIC_SOURCES := ${GICV3_SOURCES} \
+ plat/common/plat_gicv3.c
PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \
-I$(PLAT_COMMON_BASE)/include \
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index 59ffe5d..3ccc928 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -26,15 +26,12 @@
plat/common/plat_psci_common.c \
plat/common/aarch64/crash_console_helpers.S
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
BL31_SOURCES += common/desc_image_load.c \
drivers/arm/cci/cci.c \
- drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v3/arm_gicv3_common.c \
- drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- drivers/arm/gic/v3/gic500.c \
- drivers/arm/gic/v3/gicv3_main.c \
+ ${GICV3_SOURCES} \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/gpio/gpio.c \
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c
index 57daf6a..d964fc0 100644
--- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c
+++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c
@@ -8,6 +8,7 @@
#include <assert.h>
#include <common/debug.h>
#include <errno.h>
+#include <stdbool.h>
#include <stddef.h>
#include <string.h>
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
index 92fa273..c3f95db 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -117,7 +117,8 @@
ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
non_overlap_area_start, /* VA */
non_overlap_area_size, /* size */
- MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
+ MT_NS | MT_RW | MT_EXECUTE_NEVER |
+ MT_NON_CACHEABLE); /* attrs */
assert(ret == 0);
zeromem((void *)non_overlap_area_start, non_overlap_area_size);
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index a53f660..5555f5d 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -159,69 +159,7 @@
*/
void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
{
- uint32_t index;
- uint32_t total_128kb_blocks = size_in_bytes >> 17;
- uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
- uint32_t val;
-
- INFO("Configuring TrustZone SRAM Memory Carveout\n");
-
- /*
- * Reset the access configuration registers to restrict access
- * to the TZRAM aperture
- */
- for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0;
- index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
- index += 4U) {
- tegra_mc_write_32(index, 0);
- }
-
- /*
- * Enable CPU access configuration registers to access the TZRAM aperture
- */
- if (!tegra_chipid_is_t186()) {
- val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0);
- val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW;
- tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val);
- }
-
- /*
- * Set the TZRAM base. TZRAM base must be 4k aligned, at least.
- */
- assert((phys_base & (uint64_t)0xFFF) == 0U);
- tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base);
- tegra_mc_write_32(MC_TZRAM_BASE_HI,
- (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK);
-
- /*
- * Set the TZRAM size
- *
- * total size = (number of 128KB blocks) + (number of remaining 4KB
- * blocks)
- *
- */
- val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
- total_128kb_blocks;
- tegra_mc_write_32(MC_TZRAM_SIZE, val);
-
- /*
- * Lock the configuration settings by disabling TZ-only lock
- * and locking the configuration against any future changes
- * at all.
- */
- val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
- val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT;
- val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
- if (!tegra_chipid_is_t186()) {
- val |= MC_GSC_ENABLE_CPU_SECURE_BIT;
- }
- tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
-
- /*
- * MCE propagates the security configuration values across the
- * CCPLEX.
- */
- mce_update_gsc_tzram();
+ ; /* do nothing */
}
/*
@@ -348,7 +286,8 @@
ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
non_overlap_area_start, /* VA */
non_overlap_area_size, /* size */
- MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
+ MT_NS | MT_RW | MT_EXECUTE_NEVER |
+ MT_NON_CACHEABLE); /* attrs */
assert(ret == 0);
zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size);
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 46686c3..269afb1 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -39,15 +39,8 @@
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
-
IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
-static const uint64_t BL31_RW_END = BL_END;
-static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE;
-static const uint64_t BL31_RODATA_END = BL_RO_DATA_END;
-static const uint64_t TEXT_START = BL_CODE_BASE;
-static const uint64_t TEXT_END = BL_CODE_END;
-
extern uint64_t tegra_bl31_phys_base;
static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
@@ -314,15 +307,12 @@
void bl31_plat_arch_setup(void)
{
uint64_t rw_start = BL31_RW_START;
- uint64_t rw_size = BL31_RW_END - BL31_RW_START;
- uint64_t rodata_start = BL31_RODATA_BASE;
- uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
- uint64_t code_base = TEXT_START;
- uint64_t code_size = TEXT_END - TEXT_START;
+ uint64_t rw_size = BL_END - BL31_RW_START;
+ uint64_t rodata_start = BL_RO_DATA_BASE;
+ uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE;
+ uint64_t code_base = BL_CODE_BASE;
+ uint64_t code_size = BL_CODE_END - BL_CODE_BASE;
const mmap_region_t *plat_mmio_map = NULL;
-#if USE_COHERENT_MEM
- uint32_t coh_start, coh_size;
-#endif
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
/*
@@ -349,15 +339,6 @@
code_size,
MT_CODE | MT_SECURE);
-#if USE_COHERENT_MEM
- coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
- coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
-
- mmap_add_region(coh_start, coh_start,
- coh_size,
- (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
-#endif
-
/* map TZDRAM used by BL31 as coherent memory */
if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
mmap_add_region(params_from_bl2->tzdram_base,
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index 66d037f..c946a75 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -6,8 +6,7 @@
PLAT_INCLUDES := -Iplat/nvidia/tegra/include/drivers \
-Iplat/nvidia/tegra/include/lib \
- -Iplat/nvidia/tegra/include \
- -Iplat/nvidia/tegra/include/${TARGET_SOC}
+ -Iplat/nvidia/tegra/include
include lib/xlat_tables_v2/xlat_tables.mk
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
diff --git a/plat/nvidia/tegra/common/tegra_gicv2.c b/plat/nvidia/tegra/common/tegra_gicv2.c
index 293df8d..012107e 100644
--- a/plat/nvidia/tegra/common/tegra_gicv2.c
+++ b/plat/nvidia/tegra/common/tegra_gicv2.c
@@ -1,20 +1,23 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
-
#include <platform_def.h>
#include <common/bl_common.h>
#include <drivers/arm/gicv2.h>
#include <lib/utils.h>
+#include <plat/common/platform.h>
#include <tegra_private.h>
#include <tegra_def.h>
+static unsigned int tegra_target_masks[PLATFORM_CORE_COUNT];
+
/******************************************************************************
* Tegra common helper to setup the GICv2 driver data.
*****************************************************************************/
@@ -33,6 +36,8 @@
tegra_gic_data.gicc_base = TEGRA_GICC_BASE;
tegra_gic_data.interrupt_props = interrupt_props;
tegra_gic_data.interrupt_props_num = interrupt_props_num;
+ tegra_gic_data.target_masks = tegra_target_masks;
+ tegra_gic_data.target_masks_num = ARRAY_SIZE(tegra_target_masks);
gicv2_driver_init(&tegra_gic_data);
}
@@ -43,6 +48,7 @@
{
gicv2_distif_init();
gicv2_pcpu_distif_init();
+ gicv2_set_pe_target_mask(plat_my_core_pos());
gicv2_cpuif_enable();
}
@@ -61,5 +67,6 @@
void tegra_gic_pcpu_init(void)
{
gicv2_pcpu_distif_init();
+ gicv2_set_pe_target_mask(plat_my_core_pos());
gicv2_cpuif_enable();
}
diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c
index 5ec6f84..0430048 100644
--- a/plat/nvidia/tegra/common/tegra_pm.c
+++ b/plat/nvidia/tegra/common/tegra_pm.c
@@ -152,16 +152,18 @@
const plat_params_from_bl2_t *plat_params;
/*
- * Initialize the GIC cpu and distributor interfaces
- */
- tegra_gic_pcpu_init();
-
- /*
* Check if we are exiting from deep sleep.
*/
if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] ==
PSTATE_ID_SOC_POWERDN) {
+ /*
+ * On entering System Suspend state, the GIC loses power
+ * completely. Initialize the GIC global distributor and
+ * GIC cpu interfaces.
+ */
+ tegra_gic_init();
+
/* Restart console output. */
console_switch_state(CONSOLE_FLAG_RUNTIME);
@@ -183,6 +185,11 @@
* access
*/
tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE);
+ } else {
+ /*
+ * Initialize the GIC cpu and distributor interfaces
+ */
+ tegra_gic_pcpu_init();
}
/*
diff --git a/plat/nvidia/tegra/include/drivers/flowctrl.h b/plat/nvidia/tegra/include/drivers/flowctrl.h
index 54336b0..e5ab600 100644
--- a/plat/nvidia/tegra/include/drivers/flowctrl.h
+++ b/plat/nvidia/tegra/include/drivers/flowctrl.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +10,8 @@
#include <lib/mmio.h>
+#include <stdbool.h>
+
#include <tegra_def.h>
#define FLOWCTRL_HALT_CPU0_EVENTS (0x0U)
diff --git a/plat/nvidia/tegra/include/drivers/mce.h b/plat/nvidia/tegra/include/drivers/mce.h
index 4470b6b..5f1bb4f 100644
--- a/plat/nvidia/tegra/include/drivers/mce.h
+++ b/plat/nvidia/tegra/include/drivers/mce.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,7 +69,6 @@
int mce_update_reset_vector(void);
int mce_update_gsc_videomem(void);
int mce_update_gsc_tzdram(void);
-int mce_update_gsc_tzram(void);
__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
void mce_update_cstate_info(const mce_cstate_info_t *cstate);
void mce_verify_firmware_version(void);
diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h
index eb55def..91a24ca 100644
--- a/plat/nvidia/tegra/include/platform_def.h
+++ b/plat/nvidia/tegra/include/platform_def.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,12 +13,25 @@
#include <tegra_def.h>
+/*******************************************************************************
+ * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1
+ ******************************************************************************/
+#if !SEPARATE_CODE_AND_RODATA
+#error "SEPARATE_CODE_AND_RODATA should be set to 1"
+#endif
+
/*
* Platform binary types for linking
*/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
+/*
+ * Platform binary types for linking
+ */
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
/*******************************************************************************
* Generic platform constants
******************************************************************************/
@@ -33,7 +47,7 @@
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_MAX_CPUS_PER_CLUSTER)
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
- PLATFORM_CLUSTER_COUNT + 1)
+ PLATFORM_CLUSTER_COUNT + U(1))
/*******************************************************************************
* Platform console related constants
@@ -72,4 +86,5 @@
#define MAX_IO_DEVICES U(0)
#define MAX_IO_HANDLES U(0)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index dc06445..e39f9ca 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -10,6 +10,12 @@
#include <lib/utils_def.h>
/*******************************************************************************
+ * Chip specific cluster and cpu numbers
+ ******************************************************************************/
+#define PLATFORM_CLUSTER_COUNT U(4)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
+
+/*******************************************************************************
* Chip specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk
index 14b9913..8758820 100644
--- a/plat/nvidia/tegra/platform.mk
+++ b/plat/nvidia/tegra/platform.mk
@@ -40,7 +40,7 @@
# Flag to enable WDT FIQ interrupt handling for Tegra SoCs
# prior to Tegra186
-ENABLE_WDT_LEGACY_FIQ_HANDLING ?= 0
+ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING ?= 0
# Flag to allow relocation of BL32 image to TZDRAM during boot
RELOCATE_BL32_IMAGE ?= 0
@@ -48,7 +48,7 @@
include plat/nvidia/tegra/common/tegra_common.mk
include ${SOC_DIR}/platform_${TARGET_SOC}.mk
-$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING))
+$(eval $(call add_define,ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING))
$(eval $(call add_define,RELOCATE_BL32_IMAGE))
# modify BUILD_PLAT to point to SoC specific build directory
diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk
index 183e188..16bd0ea 100644
--- a/plat/nvidia/tegra/soc/t132/platform_t132.mk
+++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk
@@ -20,6 +20,9 @@
MAX_MMAP_REGIONS := 8
$(eval $(call add_define,MAX_MMAP_REGIONS))
+# platform files
+PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t132
+
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
index 9e42b2b..54d3b2c 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -386,14 +387,6 @@
}
/*******************************************************************************
- * Handler to update carveout values for TZ SysRAM aperture
- ******************************************************************************/
-int32_t mce_update_gsc_tzram(void)
-{
- return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZRAM);
-}
-
-/*******************************************************************************
* Handler to shutdown/reset the entire system
******************************************************************************/
__dead2 void mce_enter_ccplex_state(uint32_t state_idx)
diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
index 7ff7e77..4eb68e4 100644
--- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
@@ -21,29 +21,6 @@
* Array to hold stream_id override config register offsets
******************************************************************************/
const static uint32_t tegra186_streamid_override_regs[] = {
- MC_STREAMID_OVERRIDE_CFG_PTCR,
- MC_STREAMID_OVERRIDE_CFG_AFIR,
- MC_STREAMID_OVERRIDE_CFG_HDAR,
- MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
- MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
- MC_STREAMID_OVERRIDE_CFG_SATAR,
- MC_STREAMID_OVERRIDE_CFG_MPCORER,
- MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
- MC_STREAMID_OVERRIDE_CFG_AFIW,
- MC_STREAMID_OVERRIDE_CFG_HDAW,
- MC_STREAMID_OVERRIDE_CFG_MPCOREW,
- MC_STREAMID_OVERRIDE_CFG_SATAW,
- MC_STREAMID_OVERRIDE_CFG_ISPRA,
- MC_STREAMID_OVERRIDE_CFG_ISPWA,
- MC_STREAMID_OVERRIDE_CFG_ISPWB,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRD,
- MC_STREAMID_OVERRIDE_CFG_TSECSWR,
- MC_STREAMID_OVERRIDE_CFG_GPUSRD,
- MC_STREAMID_OVERRIDE_CFG_GPUSWR,
MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
MC_STREAMID_OVERRIDE_CFG_SDMMCR,
@@ -52,47 +29,6 @@
MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
MC_STREAMID_OVERRIDE_CFG_SDMMCW,
MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
- MC_STREAMID_OVERRIDE_CFG_VICSRD,
- MC_STREAMID_OVERRIDE_CFG_VICSWR,
- MC_STREAMID_OVERRIDE_CFG_VIW,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
- MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
- MC_STREAMID_OVERRIDE_CFG_APER,
- MC_STREAMID_OVERRIDE_CFG_APEW,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
- MC_STREAMID_OVERRIDE_CFG_SESRD,
- MC_STREAMID_OVERRIDE_CFG_SESWR,
- MC_STREAMID_OVERRIDE_CFG_ETRR,
- MC_STREAMID_OVERRIDE_CFG_ETRW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
- MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
- MC_STREAMID_OVERRIDE_CFG_GPUSRD2,
- MC_STREAMID_OVERRIDE_CFG_GPUSWR2,
- MC_STREAMID_OVERRIDE_CFG_AXISR,
- MC_STREAMID_OVERRIDE_CFG_AXISW,
- MC_STREAMID_OVERRIDE_CFG_EQOSR,
- MC_STREAMID_OVERRIDE_CFG_EQOSW,
- MC_STREAMID_OVERRIDE_CFG_UFSHCR,
- MC_STREAMID_OVERRIDE_CFG_UFSHCW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
- MC_STREAMID_OVERRIDE_CFG_BPMPR,
- MC_STREAMID_OVERRIDE_CFG_BPMPW,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
- MC_STREAMID_OVERRIDE_CFG_AONR,
- MC_STREAMID_OVERRIDE_CFG_AONW,
- MC_STREAMID_OVERRIDE_CFG_AONDMAR,
- MC_STREAMID_OVERRIDE_CFG_AONDMAW,
- MC_STREAMID_OVERRIDE_CFG_SCER,
- MC_STREAMID_OVERRIDE_CFG_SCEW,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
- MC_STREAMID_OVERRIDE_CFG_APEDMAR,
- MC_STREAMID_OVERRIDE_CFG_APEDMAW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
- MC_STREAMID_OVERRIDE_CFG_VICSRD1,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD1
};
/*******************************************************************************
diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk
index c17dab2..d320aac 100644
--- a/plat/nvidia/tegra/soc/t186/platform_t186.mk
+++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk
@@ -33,11 +33,12 @@
MAX_XLAT_TABLES := 25
$(eval $(call add_define,MAX_XLAT_TABLES))
-MAX_MMAP_REGIONS := 27
+MAX_MMAP_REGIONS := 30
$(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files
-PLAT_INCLUDES += -I${SOC_DIR}/drivers/include
+PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t186 \
+ -I${SOC_DIR}/drivers/include
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
index 00c671b..7edd7a0 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
@@ -116,25 +116,6 @@
}
/*******************************************************************************
- * Handler to update carveout values for TZ SysRAM aperture
- ******************************************************************************/
-int32_t mce_update_gsc_tzram(void)
-{
- int32_t ret;
-
- /*
- * MCE firmware is not running on simulation platforms.
- */
- if (mce_firmware_not_supported()) {
- ret = -EINVAL;
- } else {
- ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM);
- }
-
- return ret;
-}
-
-/*******************************************************************************
* Handler to issue the UPDATE_CSTATE_INFO request
******************************************************************************/
void mce_update_cstate_info(const mce_cstate_info_t *cstate)
diff --git a/plat/nvidia/tegra/soc/t194/drivers/se/se.c b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
index ccdc94d..31b0e26 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/se/se.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/se/se.c
@@ -23,12 +23,11 @@
/*******************************************************************************
* Constants and Macros
******************************************************************************/
-#define ERR_STATUS_SW_CLEAR U(0xFFFFFFFF)
-#define INT_STATUS_SW_CLEAR U(0xFFFFFFFF)
-#define MAX_TIMEOUT_MS U(100) /* Timeout in 100ms */
-#define NUM_SE_REGS_TO_SAVE U(4)
+#define ERR_STATUS_SW_CLEAR U(0xFFFFFFFF)
+#define INT_STATUS_SW_CLEAR U(0xFFFFFFFF)
+#define MAX_TIMEOUT_MS U(1000) /* Max. timeout of 1s */
+#define NUM_SE_REGS_TO_SAVE U(4)
-#define SE0_MAX_BUSY_TIMEOUT_MS U(100) /* 100ms Timeout Expired */
#define BYTES_IN_WORD U(4)
#define SHA256_MAX_HASH_RESULT U(7)
#define SHA256_DST_SIZE U(32)
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
index 2d5f8e3..9a4d22e 100644
--- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -12,150 +12,6 @@
#include <tegra_platform.h>
/*******************************************************************************
- * Array to hold stream_id override config register offsets
- ******************************************************************************/
-const static uint32_t tegra194_streamid_override_regs[] = {
- MC_STREAMID_OVERRIDE_CFG_PTCR,
- MC_STREAMID_OVERRIDE_CFG_HDAR,
- MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
- MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
- MC_STREAMID_OVERRIDE_CFG_SATAR,
- MC_STREAMID_OVERRIDE_CFG_MPCORER,
- MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
- MC_STREAMID_OVERRIDE_CFG_HDAW,
- MC_STREAMID_OVERRIDE_CFG_MPCOREW,
- MC_STREAMID_OVERRIDE_CFG_SATAW,
- MC_STREAMID_OVERRIDE_CFG_ISPRA,
- MC_STREAMID_OVERRIDE_CFG_ISPFALR,
- MC_STREAMID_OVERRIDE_CFG_ISPWA,
- MC_STREAMID_OVERRIDE_CFG_ISPWB,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRD,
- MC_STREAMID_OVERRIDE_CFG_TSECSWR,
- MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
- MC_STREAMID_OVERRIDE_CFG_SDMMCR,
- MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
- MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
- MC_STREAMID_OVERRIDE_CFG_SDMMCW,
- MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
- MC_STREAMID_OVERRIDE_CFG_VICSRD,
- MC_STREAMID_OVERRIDE_CFG_VICSWR,
- MC_STREAMID_OVERRIDE_CFG_VIW,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
- MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
- MC_STREAMID_OVERRIDE_CFG_APER,
- MC_STREAMID_OVERRIDE_CFG_APEW,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
- MC_STREAMID_OVERRIDE_CFG_SESRD,
- MC_STREAMID_OVERRIDE_CFG_SESWR,
- MC_STREAMID_OVERRIDE_CFG_AXIAPR,
- MC_STREAMID_OVERRIDE_CFG_AXIAPW,
- MC_STREAMID_OVERRIDE_CFG_ETRR,
- MC_STREAMID_OVERRIDE_CFG_ETRW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
- MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
- MC_STREAMID_OVERRIDE_CFG_AXISR,
- MC_STREAMID_OVERRIDE_CFG_AXISW,
- MC_STREAMID_OVERRIDE_CFG_EQOSR,
- MC_STREAMID_OVERRIDE_CFG_EQOSW,
- MC_STREAMID_OVERRIDE_CFG_UFSHCR,
- MC_STREAMID_OVERRIDE_CFG_UFSHCW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
- MC_STREAMID_OVERRIDE_CFG_BPMPR,
- MC_STREAMID_OVERRIDE_CFG_BPMPW,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
- MC_STREAMID_OVERRIDE_CFG_AONR,
- MC_STREAMID_OVERRIDE_CFG_AONW,
- MC_STREAMID_OVERRIDE_CFG_AONDMAR,
- MC_STREAMID_OVERRIDE_CFG_AONDMAW,
- MC_STREAMID_OVERRIDE_CFG_SCER,
- MC_STREAMID_OVERRIDE_CFG_SCEW,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
- MC_STREAMID_OVERRIDE_CFG_APEDMAR,
- MC_STREAMID_OVERRIDE_CFG_APEDMAW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
- MC_STREAMID_OVERRIDE_CFG_VICSRD1,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD1,
- MC_STREAMID_OVERRIDE_CFG_VIFALR,
- MC_STREAMID_OVERRIDE_CFG_VIFALW,
- MC_STREAMID_OVERRIDE_CFG_DLA0RDA,
- MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB,
- MC_STREAMID_OVERRIDE_CFG_DLA0WRA,
- MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB,
- MC_STREAMID_OVERRIDE_CFG_DLA1RDA,
- MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB,
- MC_STREAMID_OVERRIDE_CFG_DLA1WRA,
- MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDA,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDB,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDC,
- MC_STREAMID_OVERRIDE_CFG_PVA0WRA,
- MC_STREAMID_OVERRIDE_CFG_PVA0WRB,
- MC_STREAMID_OVERRIDE_CFG_PVA0WRC,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDA,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDB,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDC,
- MC_STREAMID_OVERRIDE_CFG_PVA1WRA,
- MC_STREAMID_OVERRIDE_CFG_PVA1WRB,
- MC_STREAMID_OVERRIDE_CFG_PVA1WRC,
- MC_STREAMID_OVERRIDE_CFG_RCER,
- MC_STREAMID_OVERRIDE_CFG_RCEW,
- MC_STREAMID_OVERRIDE_CFG_RCEDMAR,
- MC_STREAMID_OVERRIDE_CFG_RCEDMAW,
- MC_STREAMID_OVERRIDE_CFG_NVENC1SRD,
- MC_STREAMID_OVERRIDE_CFG_NVENC1SWR,
- MC_STREAMID_OVERRIDE_CFG_PCIE0R,
- MC_STREAMID_OVERRIDE_CFG_PCIE0W,
- MC_STREAMID_OVERRIDE_CFG_PCIE1R,
- MC_STREAMID_OVERRIDE_CFG_PCIE1W,
- MC_STREAMID_OVERRIDE_CFG_PCIE2AR,
- MC_STREAMID_OVERRIDE_CFG_PCIE2AW,
- MC_STREAMID_OVERRIDE_CFG_PCIE3R,
- MC_STREAMID_OVERRIDE_CFG_PCIE3W,
- MC_STREAMID_OVERRIDE_CFG_PCIE4R,
- MC_STREAMID_OVERRIDE_CFG_PCIE4W,
- MC_STREAMID_OVERRIDE_CFG_PCIE5R,
- MC_STREAMID_OVERRIDE_CFG_PCIE5W,
- MC_STREAMID_OVERRIDE_CFG_ISPFALW,
- MC_STREAMID_OVERRIDE_CFG_DLA0RDA1,
- MC_STREAMID_OVERRIDE_CFG_DLA1RDA1,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDA1,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDB1,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDA1,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDB1,
- MC_STREAMID_OVERRIDE_CFG_PCIE5R1,
- MC_STREAMID_OVERRIDE_CFG_NVENCSRD1,
- MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1,
- MC_STREAMID_OVERRIDE_CFG_ISPRA1,
- MC_STREAMID_OVERRIDE_CFG_PCIE0R1,
- MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD,
- MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1,
- MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR,
- MC_STREAMID_OVERRIDE_CFG_MIU0R,
- MC_STREAMID_OVERRIDE_CFG_MIU0W,
- MC_STREAMID_OVERRIDE_CFG_MIU1R,
- MC_STREAMID_OVERRIDE_CFG_MIU1W,
- MC_STREAMID_OVERRIDE_CFG_MIU2R,
- MC_STREAMID_OVERRIDE_CFG_MIU2W,
- MC_STREAMID_OVERRIDE_CFG_MIU3R,
- MC_STREAMID_OVERRIDE_CFG_MIU3W,
- MC_STREAMID_OVERRIDE_CFG_MIU4R,
- MC_STREAMID_OVERRIDE_CFG_MIU4W,
- MC_STREAMID_OVERRIDE_CFG_MIU5R,
- MC_STREAMID_OVERRIDE_CFG_MIU5W,
- MC_STREAMID_OVERRIDE_CFG_MIU6R,
- MC_STREAMID_OVERRIDE_CFG_MIU6W,
- MC_STREAMID_OVERRIDE_CFG_MIU7R,
- MC_STREAMID_OVERRIDE_CFG_MIU7W
-};
-
-/*******************************************************************************
* Array to hold the security configs for stream IDs
******************************************************************************/
const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
@@ -571,8 +427,6 @@
* Struct to hold the memory controller settings
******************************************************************************/
static tegra_mc_settings_t tegra194_mc_settings = {
- .streamid_override_cfg = tegra194_streamid_override_regs,
- .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs),
.streamid_security_cfg = tegra194_streamid_sec_cfgs,
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs),
.get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx
diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
index 33694a1..884762d 100644
--- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
@@ -16,11 +16,13 @@
#include <common/runtime_svc.h>
#include <tegra_private.h>
#include <tegra_platform.h>
+#include <smmu.h>
#include <stdbool.h>
/*******************************************************************************
* Tegra194 SiP SMCs
******************************************************************************/
+#define TEGRA_SIP_GET_SMMU_PER 0xC200FF00U
/*******************************************************************************
* This function is responsible for handling all T194 SiP calls
@@ -34,13 +36,43 @@
void *handle,
uint64_t flags)
{
- int32_t ret = -ENOTSUP;
+ int32_t ret = 0;
+ uint32_t i, smmu_per[6] = {0};
+ uint32_t num_smmu_devices = plat_get_num_smmu_devices();
+ uint64_t per[3] = {0ULL};
- (void)smc_fid;
(void)x1;
(void)x4;
(void)cookie;
(void)flags;
+ switch (smc_fid) {
+ case TEGRA_SIP_GET_SMMU_PER:
+
+ /* make sure we dont go past the array length */
+ assert(num_smmu_devices <= ARRAY_SIZE(smmu_per));
+
+ /* read all supported SMMU_PER records */
+ for (i = 0U; i < num_smmu_devices; i++) {
+ smmu_per[i] = tegra_smmu_read_32(i, SMMU_GSR0_PER);
+ }
+
+ /* pack results into 3 64bit variables. */
+ per[0] = smmu_per[0] | ((uint64_t)smmu_per[1] << 32U);
+ per[1] = smmu_per[2] | ((uint64_t)smmu_per[3] << 32U);
+ per[2] = smmu_per[4] | ((uint64_t)smmu_per[5] << 32U);
+
+ /* provide the results via X1-X3 CPU registers */
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]);
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]);
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]);
+
+ break;
+
+ default:
+ ret = -ENOTSUP;
+ break;
+ }
+
return ret;
}
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index 78766fc..c02128c 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -24,12 +24,6 @@
TZDRAM_BASE := 0x40000000
$(eval $(call add_define,TZDRAM_BASE))
-PLATFORM_CLUSTER_COUNT := 4
-$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
-
-PLATFORM_MAX_CPUS_PER_CLUSTER := 2
-$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
-
MAX_XLAT_TABLES := 25
$(eval $(call add_define,MAX_XLAT_TABLES))
@@ -37,7 +31,8 @@
$(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files
-PLAT_INCLUDES += -I${SOC_DIR}/drivers/include
+PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \
+ -I${SOC_DIR}/drivers/include
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index f29e624..7f73ea5 100644
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -534,6 +534,13 @@
}
/*
+ * Mark this CPU as ON in the cpu_powergate_mask[],
+ * so that we use Flow Controller for all subsequent
+ * power ups.
+ */
+ cpu_powergate_mask[plat_my_core_pos()] = 1;
+
+ /*
* T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's
* used for power management and boot purposes. Inform the BPMP that
* we have completed the cluster power up.
@@ -561,7 +568,6 @@
/* Turn on CPU using flow controller or PMC */
if (cpu_powergate_mask[cpu] == 0) {
tegra_pmc_cpu_on(cpu);
- cpu_powergate_mask[cpu] = 1;
} else {
tegra_fc_cpu_on(cpu);
}
diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index ba827a0..14e3324 100644
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -23,10 +23,10 @@
MAX_MMAP_REGIONS := 16
$(eval $(call add_define,MAX_MMAP_REGIONS))
-ENABLE_WDT_LEGACY_FIQ_HANDLING := 1
-$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING))
+ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING := 1
-PLAT_INCLUDES += -I${SOC_DIR}/drivers/se
+PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t210 \
+ -I${SOC_DIR}/drivers/se
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/cortex_a53.S \
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 6aa198c..1bf4e08 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -139,11 +139,10 @@
plat/common/plat_gicv2.c \
${PLAT_QEMU_COMMON_PATH}/qemu_gicv2.c
-QEMU_GICV3_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/common/gic_common.c \
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+QEMU_GICV3_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index 6ad3d8b..09856d6 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -62,11 +62,10 @@
common/desc_image_load.c
endif
-QEMU_GIC_SOURCES := drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/common/gic_common.c \
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+QEMU_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
${PLAT_QEMU_COMMON_PATH}/qemu_gicv3.c
diff --git a/plat/rockchip/rk3399/platform.mk b/plat/rockchip/rk3399/platform.mk
index 0dc1840..a658fb2 100644
--- a/plat/rockchip/rk3399/platform.mk
+++ b/plat/rockchip/rk3399/platform.mk
@@ -24,13 +24,10 @@
-I${RK_PLAT_SOC}/include/ \
-I${RK_PLAT_SOC}/include/shared/ \
-RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v3/arm_gicv3_common.c \
- drivers/arm/gic/v3/gic500.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+RK_GIC_SOURCES := ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
${RK_PLAT}/common/rockchip_gicv3.c
diff --git a/plat/socionext/synquacer/platform.mk b/plat/socionext/synquacer/platform.mk
index 0d9071b..dcd5d31 100644
--- a/plat/socionext/synquacer/platform.mk
+++ b/plat/socionext/synquacer/platform.mk
@@ -30,12 +30,11 @@
drivers/delay_timer/generic_delay_timer.c \
${XLAT_TABLES_LIB_SRCS}
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
BL31_SOURCES += drivers/arm/ccn/ccn.c \
- drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- drivers/arm/gic/v3/gicv3_main.c \
+ ${GICV3_SOURCES} \
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_gicv3.c \
plat/common/plat_psci_common.c \
diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index a014f52..0fcef1d 100644
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk
@@ -55,12 +55,11 @@
$(PLAT_PATH)/uniphier_scp.c \
$(PLAT_PATH)/uniphier_usb.c
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
BL31_SOURCES += drivers/arm/cci/cci.c \
- drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
- drivers/arm/gic/v3/gicv3_main.c \
+ ${GICV3_SOURCES} \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a72.S \
plat/common/plat_gicv3.c \
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index 4f85679..27ddab0 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -87,4 +87,8 @@
*/
int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer);
+/* Functions to map DDR in MMU with non-cacheable attribute, and unmap it */
+int stm32mp_map_ddr_non_cacheable(void);
+int stm32mp_unmap_ddr(void);
+
#endif /* STM32MP_COMMON_H */
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index afa87f4..9af1564 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,6 +12,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/st/stm32mp_clkfunc.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
uintptr_t plat_get_ns_image_entrypoint(void)
@@ -151,3 +152,16 @@
return 0;
}
+
+int stm32mp_map_ddr_non_cacheable(void)
+{
+ return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
+ STM32MP_DDR_MAX_SIZE,
+ MT_NON_CACHEABLE | MT_RW | MT_NS);
+}
+
+int stm32mp_unmap_ddr(void)
+{
+ return mmap_remove_dynamic_region(STM32MP_DDR_BASE,
+ STM32MP_DDR_MAX_SIZE);
+}
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index 4fa796f..acb323c 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,6 +92,7 @@
return status;
}
+#if ENABLE_ASSERTIONS
/*******************************************************************************
* This function returns the address cells from the node parent.
* Returns:
@@ -100,7 +101,7 @@
* - a default value if undefined #address-cells property as per libfdt
* implementation.
******************************************************************************/
-int fdt_get_node_parent_address_cells(int node)
+static int fdt_get_node_parent_address_cells(int node)
{
int parent;
@@ -120,7 +121,7 @@
* - a default value if undefined #size-cells property as per libfdt
* implementation.
******************************************************************************/
-int fdt_get_node_parent_size_cells(int node)
+static int fdt_get_node_parent_size_cells(int node)
{
int parent;
@@ -131,6 +132,7 @@
return fdt_size_cells(fdt, parent);
}
+#endif
/*******************************************************************************
* This function reads a value of a node property (generic use of fdt
@@ -467,7 +469,7 @@
}
pwr_regulators_node = fdt_subnode_offset(fdt, node, "pwr-regulators");
- if (node < 0) {
+ if (pwr_regulators_node < 0) {
INFO("%s: Cannot read pwr-regulators node in DT\n", __func__);
return 0;
}
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 024dbe0..652765c 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -130,6 +130,7 @@
void bl2_platform_setup(void)
{
int ret;
+ uint32_t ddr_ns_size;
if (dt_pmic_status() > 0) {
initialize_pmic();
@@ -141,8 +142,24 @@
panic();
}
+ ddr_ns_size = stm32mp_get_ddr_ns_size();
+ assert(ddr_ns_size > 0U);
+
+ /* Map non secure DDR for BL33 load, now with cacheable attribute */
+ ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
+ ddr_ns_size, MT_MEMORY | MT_RW | MT_NS);
+ assert(ret == 0);
+
#ifdef AARCH32_SP_OPTEE
INFO("BL2 runs OP-TEE setup\n");
+
+ /* Map secure DDR for OP-TEE paged area */
+ ret = mmap_add_dynamic_region(STM32MP_DDR_BASE + ddr_ns_size,
+ STM32MP_DDR_BASE + ddr_ns_size,
+ STM32MP_DDR_S_SIZE,
+ MT_MEMORY | MT_RW | MT_SECURE);
+ assert(ret == 0);
+
/* Initialize tzc400 after DDR initialization */
stm32mp1_security_setup();
#else
@@ -166,14 +183,6 @@
MT_CODE | MT_SECURE);
#ifdef AARCH32_SP_OPTEE
- /* OP-TEE image needs post load processing: keep RAM read/write */
- mmap_add_region(STM32MP_DDR_BASE + dt_get_ddr_size() -
- STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE,
- STM32MP_DDR_BASE + dt_get_ddr_size() -
- STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE,
- STM32MP_DDR_S_SIZE,
- MT_MEMORY | MT_RW | MT_SECURE);
-
mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
STM32MP_OPTEE_SIZE,
MT_MEMORY | MT_RW | MT_SECURE);
@@ -181,19 +190,12 @@
/* Prevent corruption of preloaded BL32 */
mmap_add_region(BL32_BASE, BL32_BASE,
BL32_LIMIT - BL32_BASE,
- MT_MEMORY | MT_RO | MT_SECURE);
-
+ MT_RO_DATA | MT_SECURE);
#endif
- /* Map non secure DDR for BL33 load and DDR training area restore */
- mmap_add_region(STM32MP_DDR_BASE,
- STM32MP_DDR_BASE,
- STM32MP_DDR_MAX_SIZE,
- MT_MEMORY | MT_RW | MT_NS);
-
/* Prevent corruption of preloaded Device Tree */
mmap_add_region(DTB_BASE, DTB_BASE,
DTB_LIMIT - DTB_BASE,
- MT_MEMORY | MT_RO | MT_SECURE);
+ MT_RO_DATA | MT_SECURE);
configure_mmu();
@@ -351,8 +353,7 @@
paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
assert(paged_mem_params != NULL);
paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
- (dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
- STM32MP_DDR_SHMEM_SIZE);
+ stm32mp_get_ddr_ns_size();
paged_mem_params->image_info.image_max_size =
STM32MP_DDR_S_SIZE;
diff --git a/plat/st/stm32mp1/include/stm32mp1_private.h b/plat/st/stm32mp1/include/stm32mp1_private.h
index e38fca0..2da64ac 100644
--- a/plat/st/stm32mp1/include/stm32mp1_private.h
+++ b/plat/st/stm32mp1/include/stm32mp1_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,4 +21,5 @@
void stm32mp1_syscfg_enable_io_compensation(void);
void stm32mp1_syscfg_disable_io_compensation(void);
+uint32_t stm32mp_get_ddr_ns_size(void);
#endif /* STM32MP1_PRIVATE_H */
diff --git a/plat/st/stm32mp1/plat_image_load.c b/plat/st/stm32mp1/plat_image_load.c
index a52db6c..6d7af74 100644
--- a/plat/st/stm32mp1/plat_image_load.c
+++ b/plat/st/stm32mp1/plat_image_load.c
@@ -1,9 +1,11 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <platform_def.h>
+
#include <common/desc_image_load.h>
#include <plat/common/platform.h>
@@ -21,6 +23,13 @@
******************************************************************************/
bl_load_info_t *plat_get_bl_image_load_info(void)
{
+ bl_mem_params_node_t *bl33 = get_bl_mem_params_node(BL33_IMAGE_ID);
+ uint32_t ddr_ns_size = stm32mp_get_ddr_ns_size();
+
+ /* Max size is non-secure DDR end address minus image_base */
+ bl33->image_info.image_max_size = STM32MP_DDR_BASE + ddr_ns_size -
+ bl33->image_info.image_base;
+
return get_bl_load_info_from_mem_params_desc();
}
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk
index bd1a16b..5ce7a9c 100644
--- a/plat/st/stm32mp1/platform.mk
+++ b/plat/st/stm32mp1/platform.mk
@@ -11,6 +11,11 @@
STM32_TF_VERSION ?= 0
+# Enable dynamic memory mapping
+PLAT_XLAT_TABLES_DYNAMIC := 1
+$(eval $(call assert_boolean,PLAT_XLAT_TABLES_DYNAMIC))
+$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+
# Not needed for Cortex-A7
WORKAROUND_CVE_2017_5715:= 0
@@ -152,8 +157,6 @@
STM32_TF_STM32 := $(addprefix ${BUILD_PLAT}/tf-a-, $(patsubst %.dtb,%.stm32,$(DTB_FILE_NAME)))
STM32_TF_LINKERFILE := ${BUILD_PLAT}/stm32mp1.ld
-BL2_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
-
# Variables for use with stm32image
STM32IMAGEPATH ?= tools/stm32image
STM32IMAGE ?= ${STM32IMAGEPATH}/stm32image${BIN_EXT}
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 5dc5206..fc776ae 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,6 +62,9 @@
#ifdef AARCH32_SP_OPTEE
#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
+#else
+#define STM32MP_DDR_S_SIZE U(0)
+#define STM32MP_DDR_SHMEM_SIZE U(0)
#endif
/* DDR power initializations */
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index e2dcd2a..ac45195 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -365,3 +365,24 @@
return BSEC_OK;
}
#endif
+
+/* Get the non-secure DDR size */
+uint32_t stm32mp_get_ddr_ns_size(void)
+{
+ static uint32_t ddr_ns_size;
+ uint32_t ddr_size;
+
+ if (ddr_ns_size != 0U) {
+ return ddr_ns_size;
+ }
+
+ ddr_size = dt_get_ddr_size();
+ if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) ||
+ (ddr_size > STM32MP_DDR_MAX_SIZE)) {
+ panic();
+ }
+
+ ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE);
+
+ return ddr_ns_size;
+}
diff --git a/plat/st/stm32mp1/stm32mp1_security.c b/plat/st/stm32mp1/stm32mp1_security.c
index 61db2e7..3a29ba9 100644
--- a/plat/st/stm32mp1/stm32mp1_security.c
+++ b/plat/st/stm32mp1/stm32mp1_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -35,29 +35,30 @@
{
unsigned long long region_base, region_top;
unsigned long long ddr_base = STM32MP_DDR_BASE;
- unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size();
- unsigned long long ddr_top = ddr_base + (ddr_size - 1U);
+ unsigned long long ddr_ns_size =
+ (unsigned long long)stm32mp_get_ddr_ns_size();
+ unsigned long long ddr_ns_top = ddr_base + (ddr_ns_size - 1U);
tzc400_init(STM32MP1_TZC_BASE);
tzc400_disable_filters();
-#ifdef AARCH32_SP_OPTEE
/*
* Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the
* same configuration to all filters in the TZC.
*/
region_base = ddr_base;
- region_top = ddr_top - STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE;
+ region_top = ddr_ns_top;
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
region_base,
region_top,
TZC_REGION_S_NONE,
TZC_REGION_NSEC_ALL_ACCESS_RDWR);
+#ifdef AARCH32_SP_OPTEE
/* Region 2 set to cover all secure DRAM. */
region_base = region_top + 1U;
- region_top = ddr_top - STM32MP_DDR_SHMEM_SIZE;
+ region_top += STM32MP_DDR_S_SIZE;
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 2,
region_base,
region_top,
@@ -66,24 +67,12 @@
/* Region 3 set to cover non-secure shared memory DRAM. */
region_base = region_top + 1U;
- region_top = ddr_top;
+ region_top += STM32MP_DDR_SHMEM_SIZE;
tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 3,
region_base,
region_top,
TZC_REGION_S_NONE,
TZC_REGION_NSEC_ALL_ACCESS_RDWR);
-#else
- /*
- * Region 1 set to cover all DRAM at 0xC000_0000. Apply the
- * same configuration to all filters in the TZC.
- */
- region_base = ddr_base;
- region_top = ddr_top;
- tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
- region_base,
- region_top,
- TZC_REGION_S_NONE,
- TZC_REGION_NSEC_ALL_ACCESS_RDWR);
#endif
/* Raise an exception if a NS device tries to access secure memory */
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 587b44b..03d39f1 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -53,12 +53,11 @@
drivers/ti/uart/aarch64/16550_console.S \
${PLAT_PATH}/common/k3_console.c \
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
K3_GIC_SOURCES += \
- drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
+ ${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
${PLAT_PATH}/common/k3_gicv3.c \
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index 9a9b7c0..810e5d8 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -7,6 +7,7 @@
#ifndef VERSAL_DEF_H
#define VERSAL_DEF_H
+#include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h>
/* List all consoles */
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 5d7fd69..16396dc 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -43,17 +43,14 @@
-Iplat/xilinx/versal/include/ \
-Iplat/xilinx/versal/pm_service/
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
- drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v3/arm_gicv3_common.c \
- drivers/arm/gic/v3/gic500.c \
- drivers/arm/gic/v3/gicv3_main.c \
- drivers/arm/gic/v3/gicv3_helpers.c \
- drivers/arm/gic/v3/gicdv3_helpers.c \
- drivers/arm/gic/v3/gicrv3_helpers.c \
+ ${GICV3_SOURCES} \
drivers/arm/pl011/aarch64/pl011_console.S \
plat/common/aarch64/crash_console_helpers.S \
plat/arm/common/arm_cci.c \
diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h
index 5d335d9..5e7254e 100644
--- a/plat/xilinx/zynqmp/include/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/include/zynqmp_def.h
@@ -7,6 +7,7 @@
#ifndef ZYNQMP_DEF_H
#define ZYNQMP_DEF_H
+#include <plat/arm/common/smccc_def.h>
#include <plat/common/common_def.h>
#define ZYNQMP_CONSOLE_ID_cadence 1
diff --git a/services/spd/tlkd/tlkd_main.c b/services/spd/tlkd/tlkd_main.c
index 481bb69..ecac435 100644
--- a/services/spd/tlkd/tlkd_main.c
+++ b/services/spd/tlkd/tlkd_main.c
@@ -272,6 +272,9 @@
case TLK_TA_LAUNCH_OP:
case TLK_TA_SEND_EVENT:
case TLK_RESUME_FID:
+ case TLK_SET_BL_VERSION:
+ case TLK_LOCK_BL_INTERFACE:
+ case TLK_BL_RPMB_SERVICE:
if (!ns)
SMC_RET1(handle, SMC_UNK);