diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
index 2cce653..c8e9ae8 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
@@ -45,30 +45,30 @@
 #ifndef RCAR_LSI
 #define RCAR_LSI	RCAR_AUTO
 #endif
-#if(RCAR_LSI==RCAR_AUTO)
+#if (RCAR_LSI == RCAR_AUTO)
 static uint32_t Prr_Product;
 static uint32_t Prr_Cut;
 #else
-#if(RCAR_LSI==RCAR_H3)
+#if (RCAR_LSI == RCAR_H3)
 static const uint32_t Prr_Product = PRR_PRODUCT_H3;
-#elif(RCAR_LSI==RCAR_M3)
+#elif(RCAR_LSI == RCAR_M3)
 static const uint32_t Prr_Product = PRR_PRODUCT_M3;
-#elif(RCAR_LSI==RCAR_M3N)
+#elif(RCAR_LSI == RCAR_M3N)
 static const uint32_t Prr_Product = PRR_PRODUCT_M3N;
-#elif(RCAR_LSI==RCAR_H3N)
+#elif(RCAR_LSI == RCAR_H3N)
 static const uint32_t Prr_Product = PRR_PRODUCT_H3;
 #endif /* RCAR_LSI */
 
 #ifndef RCAR_LSI_CUT
 static uint32_t Prr_Cut;
 #else /* RCAR_LSI_CUT */
-#if(RCAR_LSI_CUT==RCAR_CUT_10)
+#if (RCAR_LSI_CUT == RCAR_CUT_10)
 static const uint32_t Prr_Cut = PRR_PRODUCT_10;
-#elif(RCAR_LSI_CUT==RCAR_CUT_11)
+#elif(RCAR_LSI_CUT == RCAR_CUT_11)
 static const uint32_t Prr_Cut = PRR_PRODUCT_11;
-#elif(RCAR_LSI_CUT==RCAR_CUT_20)
+#elif(RCAR_LSI_CUT == RCAR_CUT_20)
 static const uint32_t Prr_Cut = PRR_PRODUCT_20;
-#elif(RCAR_LSI_CUT==RCAR_CUT_30)
+#elif(RCAR_LSI_CUT == RCAR_CUT_30)
 static const uint32_t Prr_Cut = PRR_PRODUCT_30;
 #endif /* RCAR_LSI_CUT */
 #endif /* RCAR_LSI_CUT */
@@ -130,7 +130,7 @@
 #define OPERATING_FREQ			(400U)	/* Mhz */
 #define BASE_SUB_SLOT_NUM		(0x6U)
 #define SUB_SLOT_CYCLE			(0x7EU)	/* 126 */
-#define QOSWT_WTSET0_CYCLE		((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ)	/* unit:ns */
+#define QOSWT_WTSET0_CYCLE		((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)	/* unit:ns */
 
 uint32_t get_refperiod(void)
 {
@@ -249,21 +249,21 @@
 static void ddr_setval_ach(uint32_t regdef, uint32_t val);
 static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
 static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p);
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p);
-static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size);
-static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val);
-static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef);
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p);
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p);
+static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size);
+static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val);
+static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef);
 static uint32_t ddrphy_regif_chk(void);
-static inline void ddrphy_regif_idle();
+static inline void ddrphy_regif_idle(void);
 static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps,
 			 uint16_t cyc);
 static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
-			 uint16_t * js2);
+			 uint16_t *js2);
 static int16_t _f_scale_adj(int16_t ps);
 static void ddrtbl_load(void);
 static void ddr_config_sub(void);
-static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz);
+static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz);
 static void ddr_config_sub_h3v1x(void);
 static void ddr_config(void);
 static void dbsc_regset(void);
@@ -297,6 +297,7 @@
 	uint32_t init_cal[4];	/*  Initial io-code (4 is for H3) */
 	uint32_t tcomp_cal[4];	/*  Temperature compensated io-code (4 is for H3) */
 };
+
 struct DdrtData tcal;
 
 static void pvtcode_update(void);
@@ -341,10 +342,10 @@
 }
 
 #define foreach_vch(ch) \
-for(ch=vch_nxt(0);ch<DRAM_CH_CNT;ch=vch_nxt(ch+1))
+for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1))
 
 #define foreach_ech(ch) \
-for(ch=0;ch<DRAM_CH_CNT;ch++)
+for (ch = 0; ch < DRAM_CH_CNT; ch++)
 
 /*******************************************************************************
  *	Printing functions
@@ -532,8 +533,8 @@
 	uint32_t loop;
 
 	val = 0;
-	if ((PRR_PRODUCT_M3N != Prr_Product)
-	    && (PRR_PRODUCT_V3H != Prr_Product)) {
+	if ((Prr_Product != PRR_PRODUCT_M3N)
+	    && (Prr_Product != PRR_PRODUCT_V3H)) {
 		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
 		dsb_sev();
 
@@ -579,8 +580,8 @@
 	uint32_t val;
 	uint32_t loop;
 
-	if ((PRR_PRODUCT_M3N != Prr_Product)
-	    && (PRR_PRODUCT_V3H != Prr_Product)) {
+	if ((Prr_Product != PRR_PRODUCT_M3N)
+	    && (Prr_Product != PRR_PRODUCT_V3H)) {
 		mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
 		dsb_sev();
 		for (loop = 0; loop < loop_max; loop++) {
@@ -628,8 +629,8 @@
 	uint32_t val;
 	uint32_t loop;
 
-	if ((PRR_PRODUCT_M3N != Prr_Product)
-	    && (PRR_PRODUCT_V3H != Prr_Product)) {
+	if ((Prr_Product != PRR_PRODUCT_M3N)
+	    && (Prr_Product != PRR_PRODUCT_V3H)) {
 		foreach_vch(ch) {
 			mmio_write_32(DBSC_DBPDRGA(ch), regadd);
 			dsb_sev();
@@ -653,7 +654,7 @@
 	}
 }
 
-static inline void ddrphy_regif_idle()
+static inline void ddrphy_regif_idle(void)
 {
 	uint32_t val;
 
@@ -759,7 +760,7 @@
 	return ddr_getval_s(ch, 0, regdef);
 }
 
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t * p)
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p)
 {
 	uint32_t ch;
 
@@ -768,14 +769,14 @@
 	return p[0];
 }
 
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t * p)
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p)
 {
 	uint32_t ch, slice;
 	uint32_t *pp;
 
 	pp = p;
 	foreach_vch(ch)
-	    for (slice = 0; slice < SLICE_CNT; slice++)
+	for (slice = 0; slice < SLICE_CNT; slice++)
 		*pp++ = ddr_getval_s(ch, slice, regdef);
 	return p[0];
 }
@@ -783,7 +784,7 @@
 /*******************************************************************************
  *	handling functions for setteing ddrphy value table
  ******************************************************************************/
-static void _tblcopy(uint32_t * to, const uint32_t * from, uint32_t size)
+static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size)
 {
 	uint32_t i;
 
@@ -792,7 +793,7 @@
 	}
 }
 
-static void ddrtbl_setval(uint32_t * tbl, uint32_t _regdef, uint32_t val)
+static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val)
 {
 	uint32_t adr;
 	uint32_t lsb;
@@ -822,7 +823,7 @@
 	tbl[adr & adrmsk] = tmp;
 }
 
-static uint32_t ddrtbl_getval(uint32_t * tbl, uint32_t _regdef)
+static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef)
 {
 	uint32_t adr;
 	uint32_t lsb;
@@ -870,10 +871,10 @@
 		PI_VERSION_CODE = 0x2040;	/* H3 Ver.2.0 or later/M3-N/V3H */
 	}
 
-	ddr_getval_ach(_reg_PI_VERSION, (uint32_t *) tmp_ach);
+	ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach);
 	err = 0;
 	foreach_vch(ch) {
-		if (PI_VERSION_CODE != tmp_ach[ch])
+		if (tmp_ach[ch] != PI_VERSION_CODE)
 			err = 1;
 	}
 	return err;
@@ -892,15 +893,16 @@
 	uint8_t MR1;
 	uint8_t MR2;
 };
+
 #define JS1_USABLEC_SPEC_LO 2
 #define JS1_USABLEC_SPEC_HI 5
 #define JS1_FREQ_TBL_NUM 8
-#define JS1_MR1(f) (0x04 | ((f)<<4))
-#define JS1_MR2(f) (0x00 | ((f)<<3) | (f))
+#define JS1_MR1(f) (0x04 | ((f) << 4))
+#define JS1_MR2(f) (0x00 | ((f) << 3) | (f))
 const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
-	{  800,  6,  6,  4,  6,  8, JS1_MR1(0), JS1_MR2(0)|0x40 }, /*  533.333Mbps */
-	{ 1600, 10, 12,  8, 10,  8, JS1_MR1(1), JS1_MR2(1)|0x40 }, /* 1066.666Mbps */
-	{ 2400, 14, 16, 12, 16,  8, JS1_MR1(2), JS1_MR2(2)|0x40 }, /* 1600.000Mbps */
+	{  800,  6,  6,  4,  6,  8, JS1_MR1(0), JS1_MR2(0) | 0x40 }, /*  533.333Mbps */
+	{ 1600, 10, 12,  8, 10,  8, JS1_MR1(1), JS1_MR2(1) | 0x40 }, /* 1066.666Mbps */
+	{ 2400, 14, 16, 12, 16,  8, JS1_MR1(2), JS1_MR2(2) | 0x40 }, /* 1600.000Mbps */
 	{ 3200, 20, 22, 10, 20,  8, JS1_MR1(3), JS1_MR2(3) },      /* 2133.333Mbps */
 	{ 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) },      /* 2666.666Mbps */
 	{ 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) },      /* 3200.000Mbps */
@@ -938,9 +940,9 @@
 #define JS2_TBLCNT 22
 
 #define JS2_tRCpb (JS2_TBLCNT)
-#define JS2_tRCab (JS2_TBLCNT+1)
-#define JS2_tRFCab (JS2_TBLCNT+2)
-#define JS2_CNT (JS2_TBLCNT+3)
+#define JS2_tRCab (JS2_TBLCNT + 1)
+#define JS2_tRFCab (JS2_TBLCNT + 2)
+#define JS2_CNT (JS2_TBLCNT + 3)
 
 #ifndef JS2_DERATE
 #define JS2_DERATE 0
@@ -992,7 +994,7 @@
 /*tZQCALns*/ {1000 * 10, 0},
 /*tZQLAT*/ {30000, 10},
 /*tIEdly*/ {12500, 0}
-	     }
+	}
 };
 
 const uint16_t jedec_spec2_tRFC_ab[7] = {
@@ -1011,18 +1013,18 @@
 	uint32_t tmp;
 	uint32_t div;
 
-	tmp = (((uint32_t) (ps) + 9) / 10) * ddr_mbps;
+	tmp = (((uint32_t)(ps) + 9) / 10) * ddr_mbps;
 	div = tmp / (200000 * ddr_mbpsdiv);
 	if (tmp != (div * 200000 * ddr_mbpsdiv))
 		div = div + 1;
 
 	if (div > cyc)
-		return (uint16_t) div;
+		return (uint16_t)div;
 	return cyc;
 }
 
 static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv,
-			 uint16_t * js2)
+			 uint16_t *js2)
 {
 	int i;
 
@@ -1046,11 +1048,11 @@
 	   = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
 	 */
 	tmp =
-	    (int32_t) 4 *(int32_t) ps *(int32_t) ddr_mbps /
-	    (int32_t) ddr_mbpsdiv;
-	tmp = (int32_t) tmp / (int32_t) 15625;
+	    (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps /
+	    (int32_t)ddr_mbpsdiv;
+	tmp = (int32_t)tmp / (int32_t)15625;
 
-	return (int16_t) tmp;
+	return (int16_t)tmp;
 }
 
 const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = {
@@ -1180,7 +1182,7 @@
 	}
 
 	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
-				_cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]);
+			   _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]);
 
 	/* protect register interface */
 	ddrphy_regif_idle();
@@ -1219,8 +1221,8 @@
 	dsb_sev();
 
 	foreach_ech(ch)
-	    if (((Boardcnf->phyvalid) & (1U << ch)))
-		while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) ;
+	if (((Boardcnf->phyvalid) & (1U << ch)))
+		while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f);
 	dsb_sev();
 }
 
@@ -1245,7 +1247,7 @@
 		if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U)
 			break;
 	}
-	if (JS1_USABLEC_SPEC_HI < i)
+	if (i > JS1_USABLEC_SPEC_HI)
 		js1_ind = JS1_USABLEC_SPEC_HI;
 	else
 		js1_ind = i;
@@ -1533,7 +1535,7 @@
 	FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety)
 	***********************************************************************/
 	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
-		(0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+			   (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
 	ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01);
 
 	/***********************************************************************
@@ -1624,6 +1626,7 @@
 	uint32_t tmp;
 	uint8_t high_byte[SLICE_CNT];
 	const uint32_t _par_CALVL_DEVICE_MAP = 1;
+
 	foreach_vch(ch) {
 	/***********************************************************************
 	BOARD SETTINGS (DQ,DM,VREF_DRIVING)
@@ -1747,11 +1750,12 @@
 	}
 }
 
-static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t * p_swz)
+static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz)
 {
 	uint32_t slice;
 	uint32_t tmp;
 	uint32_t tgt;
+
 	if (ddr_csn / 2) {
 		tgt = 3;
 	} else {
@@ -1920,7 +1924,7 @@
 				      _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
 				      dataL + adj);
 			reg_ddrphy_write(ch,
-					ddr_regdef_adr(
+					 ddr_regdef_adr(
 					_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
 					_cnf_DDR_PHY_ADR_V_REGSET[
 					ddr_regdef_adr(
@@ -1935,7 +1939,7 @@
 				      _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
 				      dataL + adj);
 			reg_ddrphy_write(ch,
-					ddr_regdef_adr(
+					 ddr_regdef_adr(
 					_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
 					_cnf_DDR_PHY_ADR_G_REGSET[
 					ddr_regdef_adr(
@@ -1952,7 +1956,7 @@
 					      _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
 					      dataL + adj);
 				reg_ddrphy_write(ch,
-					ddr_regdef_adr(
+						 ddr_regdef_adr(
 					_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) +
 					0x0100,
 					_cnf_DDR_PHY_ADR_V_REGSET[
@@ -1964,7 +1968,7 @@
 	}
 
 	reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
-		(0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+			   (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
 
 	/***********************************************************************
 	WDQDM DLY
@@ -2037,7 +2041,7 @@
 	 * set all ranks as density=0(4Gb) for PHY initialization
 	 */
 	foreach_vch(ch)
-	    for (csab = 0; csab < 4; csab++)
+	for (csab = 0; csab < 4; csab++)
 		mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0));
 
 	if (Prr_Product == PRR_PRODUCT_M3) {
@@ -2275,11 +2279,11 @@
 	if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
 		mmio_write_32(DBSC_DBSCHRW1, tmp[0]
 			+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
-			* 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps - 3);
+			* 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps - 3);
 	} else {
 		mmio_write_32(DBSC_DBSCHRW1, tmp[0]
 			+ ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
-			* 400 * 2 * ddr_mbpsdiv +(ddr_mbps-1))/ddr_mbps);
+			* 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps);
 	}
 
 	/***********************************************************************
@@ -2651,6 +2655,7 @@
 	uint32_t pvtr;
 	uint32_t pvtp;
 	uint32_t pvtn;
+
 	term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
 				  _reg_PHY_PAD_DATA_TERM);
 	override = 0;
@@ -2801,6 +2806,7 @@
 	uint32_t dataL;
 	uint32_t count;
 	uint32_t ch;
+
 	count = 100000;
 
 	/* H3 Ver.1.x cannot see frqchg_req */
@@ -2833,6 +2839,7 @@
 {
 	uint32_t ch;
 	uint32_t dataL;
+
 	if (assert)
 		dataL = 0x0CF20000;
 	else
@@ -2845,6 +2852,7 @@
 static inline void set_dfifrequency(uint32_t freq)
 {
 	uint32_t ch;
+
 	if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
 		foreach_vch(ch)
 		    mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq);
@@ -3404,7 +3412,7 @@
 					 _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
 			wdqdm_le[ch][cs][slice][i] = dataL;
 			win =
-			    (int32_t) wdqdm_te[ch][cs][slice][i] -
+			    (int32_t)wdqdm_te[ch][cs][slice][i] -
 			    wdqdm_le[ch][cs][slice][i];
 			if (min_win > win)
 				min_win = win;
@@ -3825,7 +3833,7 @@
 				    dataL;
 
 				win =
-				    (int32_t) rdqdm_te[ch][cs][slice +
+				    (int32_t)rdqdm_te[ch][cs][slice +
 							       SLICE_CNT *
 							       k][i] -
 				    rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
@@ -3881,7 +3889,7 @@
 			if (ch_have_this_cs[ddr_csn] & (1U << ch)) {
 				for (slice = 0; slice < SLICE_CNT; slice++) {
 					if (ddr_getval_s(ch, slice,
-					    _reg_PHY_RDLVL_STATUS_OBS) !=
+							 _reg_PHY_RDLVL_STATUS_OBS) !=
 					    0x0D00FFFF) {
 						err = (1U << ch) |
 							(0x10U << slice);
@@ -4043,7 +4051,7 @@
 			ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
 		}
 		dsb_sev();
-		ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *) tmp_ach_as);
+		ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as);
 
 		foreach_vch(ch) {
 			for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -4100,7 +4108,7 @@
 			ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
 		}
 		foreach_vch(ch)
-		    for (slice = 0; slice < SLICE_CNT; slice++)
+		for (slice = 0; slice < SLICE_CNT; slice++)
 			tmp_ach_as[ch][slice] =
 			    ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]);
 
@@ -4140,6 +4148,7 @@
 	uint32_t maxlatx2;
 	uint32_t tmp;
 	uint32_t rdlat_adjx2[SLICE_CNT];
+
 	foreach_vch(ch) {
 		maxlatx2 = 0;
 		for (slice = 0; slice < SLICE_CNT; slice++) {
@@ -4236,7 +4245,7 @@
 	Judge product and cut
 	***********************************************************************/
 #ifdef RCAR_DDR_FIXED_LSI_TYPE
-#if(RCAR_LSI==RCAR_AUTO)
+#if (RCAR_LSI == RCAR_AUTO)
 	Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
 	Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK;
 #else /* RCAR_LSI */
@@ -4304,7 +4313,7 @@
 	}
 
 	foreach_ech(ch)
-	    for (cs = 0; cs < CS_CNT; cs++)
+	for (cs = 0; cs < CS_CNT; cs++)
 		ddr_density[ch][cs] = 0xff;
 
 	foreach_vch(ch) {
@@ -4340,9 +4349,8 @@
 
 	ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1));
 
-	ddr_mul =
-	    CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
-		    brd_clkdiv * (brd_clkdiva + 1));
+	ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
+			  brd_clkdiv * (brd_clkdiva + 1));
 
 	/***********************************************************************
 	Adjust tccd
@@ -4487,6 +4495,7 @@
 void pvtcode_update2(void)
 {
 	uint32_t ch;
+
 	foreach_vch(ch) {
 		reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
 				 tcal.init_cal[ch] | 0x00020000);
@@ -4522,27 +4531,27 @@
 		dataL = mmio_read_32(THS1_TEMP);
 		if (dataL < 2800) {
 			tcal.init_temp =
-			    (143 * (int32_t) dataL - 359000) / 1000;
+			    (143 * (int32_t)dataL - 359000) / 1000;
 		} else {
 			tcal.init_temp =
-			    (121 * (int32_t) dataL - 296300) / 1000;
+			    (121 * (int32_t)dataL - 296300) / 1000;
 		}
 
 		foreach_vch(ch) {
 			pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F;
 			pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F;
-			if ((int32_t) pvtp >
+			if ((int32_t)pvtp >
 			    ((tcal.init_temp * 29 - 3625) / 1000))
 				pvtp =
-				    (int32_t) pvtp +
+				    (int32_t)pvtp +
 				    ((3625 - tcal.init_temp * 29) / 1000);
 			else
 				pvtp = 0;
 
-			if ((int32_t) pvtn >
+			if ((int32_t)pvtn >
 			    ((tcal.init_temp * 54 - 6750) / 1000))
 				pvtn =
-				    (int32_t) pvtn +
+				    (int32_t)pvtn +
 				    ((6750 - tcal.init_temp * 54) / 1000);
 			else
 				pvtn = 0;
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
index aaa5f00..58c9a7a 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
@@ -115,7 +115,7 @@
 		  0, 0, 0, 0, 0, 0, 0, 0,
 		  0, 0, 0, 0, 0, 0, 0, 0,
 		  0, 0, 0, 0, 0, 0, 0, 0}
-		 }
+		}
 		}
 	 },
 /* boardcnf[1] RENESAS KRIEK board with M3-W/SoC */
@@ -126,8 +126,8 @@
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00345201,
 	   0x3201,
@@ -147,7 +147,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00302154,
 	   0x2310,
@@ -166,8 +166,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[2] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 1rank) */
 	{
@@ -177,8 +177,8 @@
 	 -320,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x3210,
@@ -198,7 +198,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x3102,
@@ -218,7 +218,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x0213,
@@ -238,7 +238,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x0213,
@@ -257,8 +257,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[3] RENESAS Starter Kit board with M3-W/SIP(8Gbit 1rank) */
 	{
@@ -268,8 +268,8 @@
 	 0,
 	 0x0300,
 	 0x00a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xFF},
 	   0x00543210U,
 	   0x3201,
@@ -289,7 +289,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xFF},
 	   0x00543210,
 	   0x2310,
@@ -308,8 +308,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[4] RENESAS SALVATOR-M(1rank) board with H3 Ver.1.x/SoC */
 	{
@@ -319,8 +319,8 @@
 	 -320,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xff},
 	   0x00315024,
 	   0x3120,
@@ -340,7 +340,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00025143,
 	   0x3210,
@@ -360,7 +360,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00523104,
 	   0x2301,
@@ -380,7 +380,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00153402,
 	   0x2031,
@@ -399,8 +399,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[5] RENESAS KRIEK-1rank board with M3-W/SoC */
 	{
@@ -410,8 +410,8 @@
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xff},
 	   0x00345201,
 	   0x3201,
@@ -431,7 +431,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00302154,
 	   0x2310,
@@ -450,8 +450,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[6] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 2rank) */
 	{
@@ -461,8 +461,8 @@
 	 -320,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x3210,
@@ -482,7 +482,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x3102,
@@ -502,7 +502,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x0213,
@@ -522,7 +522,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x0213,
@@ -541,8 +541,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[7] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 1rank) */
 	{
@@ -552,8 +552,8 @@
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x2310,
@@ -573,7 +573,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00105432,
 	   0x3210,
@@ -593,7 +593,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -613,7 +613,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -632,8 +632,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[8] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 2rank) */
 	{
@@ -647,8 +647,8 @@
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x2310,
@@ -669,7 +669,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x2301,
@@ -690,7 +690,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #else
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00105432,
 	   0x3210,
@@ -711,7 +711,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #endif
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x2301,
@@ -731,7 +731,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00543210,
 	   0x2301,
@@ -750,8 +750,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[9] RENESAS SALVATOR-MS(1rank) board with H3 Ver.2.0 or later/SoC */
 	{
@@ -761,8 +761,8 @@
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x3210,
@@ -782,7 +782,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -802,7 +802,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00452103,
 	   0x3210,
@@ -822,7 +822,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0xff},
 	   0x00520413,
 	   0x2301,
@@ -841,8 +841,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[10] RENESAS Kriek(2rank) board with M3-N/SoC */
 	{
@@ -852,8 +852,8 @@
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00345201,
 	   0x3201,
@@ -872,8 +872,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[11] RENESAS SALVATOR-X board with M3-N/SIP(8Gbit 2rank) */
 	{
@@ -883,8 +883,8 @@
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 #if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
 	   {0x04, 0x04},
 #else
@@ -907,8 +907,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[12] RENESAS CONDOR board with V3H/SoC */
 	{
@@ -918,8 +918,8 @@
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00501342,
 	   0x3201,
@@ -938,8 +938,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[13] RENESAS KRIEK board with PM3/SoC */
 	{
@@ -949,8 +949,8 @@
 	 -320,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00345201,
 	   0x3201,
@@ -970,7 +970,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00302154,
 	   0x2310,
@@ -990,7 +990,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00302154,
 	   0x2310,
@@ -1010,7 +1010,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0xff, 0xff},
 	   0,
 	   0,
@@ -1029,8 +1029,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[14] SALVATOR-X board with H3 Ver.2.0 or later/SIP(16Gbit 1rank) */
 	{
@@ -1044,8 +1044,8 @@
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x04, 0xff},
 	   0x00543210,
 	   0x2310,
@@ -1066,7 +1066,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
-	  {
+	{
 	   {0x04, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -1087,7 +1087,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #else
-	  {
+	{
 	   {0x04, 0xff},
 	   0x00105432,
 	   0x3210,
@@ -1108,7 +1108,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
 #endif
-	  {
+	{
 	   {0x04, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -1128,7 +1128,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x04, 0xff},
 	   0x00543210,
 	   0x2301,
@@ -1147,8 +1147,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[15] RENESAS KRIEK board with H3N */
 	{
@@ -1158,8 +1158,8 @@
 	 0,
 	 0x300,
 	 0x0a0,
-	 {
-	  {
+	{
+	{
 	   {0x02, 0x02},
 	   0x00345201,
 	   0x3201,
@@ -1179,7 +1179,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00302154,
 	   0x2310,
@@ -1199,7 +1199,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x02, 0x02},
 	   0x00302154,
 	   0x2310,
@@ -1219,7 +1219,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0xff, 0xff},
 	   0,
 	   0,
@@ -1238,8 +1238,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */
 	{
@@ -1249,8 +1249,8 @@
 	 0,
 	 0x0300,
 	 0x00a0,
-	 {
-	  {
+	{
+	{
 	   {0x04, 0x04},
 	    0x520314FFFF523041,
 	    0x3201,
@@ -1270,7 +1270,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x04, 0x04},
 	    0x314250FFFF312405,
 	    0x2310,
@@ -1289,8 +1289,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	   }
-	  }
+	}
+	}
 	 },
 /* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */
 	{
@@ -1300,8 +1300,8 @@
 	 0,
 	 0x0300,
 	 0x00a0,
-	 {
-	  {
+	{
+	{
 	   {0x04, 0x04},
 	    0x520314FFFF523041,
 	    0x3201,
@@ -1320,8 +1320,8 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	  }
-	 }
+	}
+	}
 	},
 /* boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) */
 	{
@@ -1331,8 +1331,8 @@
 	 0,
 	 0x0300,
 	 0x00a0,
-	 {
-	  {
+	{
+	{
 	   {0x04, 0x04},
 	    0x00543210,
 	    0x3201,
@@ -1352,7 +1352,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x04, 0x04},
 	    0x00543210,
 	    0x2310,
@@ -1371,19 +1371,19 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	  }
-	 }
+	}
+	}
 	},
 /* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */
-        {
-         0x03,
-         0x01,
-         0x02c0,
-         0,
-         0x0300,
-         0x00a0,
-	 {
-          {
+	{
+	 0x03,
+	 0x01,
+	 0x02c0,
+	 0,
+	 0x0300,
+	 0x00a0,
+	{
+	{
 	   {0x04, 0xff},
 	    0x00543210,
 	    0x3201,
@@ -1403,7 +1403,7 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
 	   },
-	  {
+	{
 	   {0x04, 0xff},
 	    0x00543210,
 	    0x2310,
@@ -1422,114 +1422,114 @@
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0, 0, 0, 0, 0, 0, 0}
-	  }
-	 }
+	}
+	}
 	},
 /* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */
-        {
-         0x03,
-         0x01,
-         0x02c0,
-         0,
-         0x0300,
-         0x00a0,
-         {
-          {
-           {0x04, 0x04},
-            0x00345201,
-            0x3201,
-           {0x01672543, 0x45361207, 0x45632107, 0x60715234},
-           {0x08, 0x08, 0x08, 0x08},
-            WDQLVL_PAT,
-           {0, 0, 0, 0, 0, 0, 0, 0,
+	{
+	 0x03,
+	 0x01,
+	 0x02c0,
+	 0,
+	 0x0300,
+	 0x00a0,
+	{
+	{
+	   {0x04, 0x04},
+	    0x00345201,
+	    0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	    WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
 	    0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0}
-           },
-          {
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	{
 	   {0x04, 0x04},
-            0x00302154,
-            0x2310,
-           {0x01672543, 0x45361207, 0x45632107, 0x60715234},
-           {0x08, 0x08, 0x08, 0x08},
-           WDQLVL_PAT,
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0}
-          }
-         }
-        },
+	    0x00302154,
+	    0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	}
+	}
+	},
 /* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */
-        {
-         0x03,
-         0x01,
-         0x02c0,
-         0,
-         0x0300,
-         0x00a0,
-         {
-          {
-           {0x04, 0xff},
-            0x00345201,
-            0x3201,
-           {0x01672543, 0x45361207, 0x45632107, 0x60715234},
-           {0x08, 0x08, 0x08, 0x08},
-           WDQLVL_PAT,
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0}
-           },
-          {
-           {0x04, 0xff},
-            0x00302154,
-            0x2310,
-           {0x01672543, 0x45361207, 0x45632107, 0x60715234},
-           {0x08, 0x08, 0x08, 0x08},
-           WDQLVL_PAT,
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0},
-           {0, 0, 0, 0},
-           {0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0,
-            0, 0, 0, 0, 0, 0, 0, 0}
-           }
-          }
-         }
+	{
+	 0x03,
+	 0x01,
+	 0x02c0,
+	 0,
+	 0x0300,
+	 0x00a0,
+	{
+	{
+	   {0x04, 0xff},
+	    0x00345201,
+	    0x3201,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	   },
+	{
+	   {0x04, 0xff},
+	    0x00302154,
+	    0x2310,
+	   {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+	   {0x08, 0x08, 0x08, 0x08},
+	   WDQLVL_PAT,
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0},
+	   {0, 0, 0, 0},
+	   {0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0}
+	}
+	}
+	}
 };
 
-void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
+void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
 {
 	uint32_t md;
 
@@ -1560,7 +1560,7 @@
 	(void)brd;
 }
 
-void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
+void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
 {
 	uint32_t md;
 
@@ -1616,13 +1616,13 @@
 /*
  * SAMPLE board detect function
  */
-#define PFC_PMMR   	0xE6060000U
+#define PFC_PMMR	0xE6060000U
 #define PFC_PUEN5	0xE6060414U
 #define PFC_PUEN6	0xE6060418U
 #define PFC_PUD5	0xE6060454U
 #define PFC_PUD6	0xE6060458U
 #define GPIO_INDT5	0xE605500CU
-#define GPIO_GPSR6 	0xE6060118U
+#define GPIO_GPSR6	0xE6060118U
 
 #if (RCAR_GEN3_ULCB == 0)
 static void pfc_write_and_poll(uint32_t a, uint32_t v)
@@ -1630,7 +1630,7 @@
 	mmio_write_32(PFC_PMMR, ~v);
 	v = ~mmio_read_32(PFC_PMMR);
 	mmio_write_32(a, v);
-	while (v != mmio_read_32(a)) ;
+	while (v != mmio_read_32(a));
 	dsb_sev();
 }
 #endif
@@ -1699,7 +1699,7 @@
 static uint32_t _board_judge(void)
 {
 	uint32_t brd;
-#if (RCAR_GEN3_ULCB==1)
+#if (RCAR_GEN3_ULCB == 1)
 	/* Starter Kit */
 	if (Prr_Product == PRR_PRODUCT_H3) {
 		if (Prr_Cut <= PRR_PRODUCT_11) {
@@ -1725,7 +1725,7 @@
 
 	usb2_ovc_open = opencheck_SSI_WS6();
 
-	/* RENESAS Eva-borad */
+	/* RENESAS Eva-board */
 	brd = 99;
 	if (Prr_Product == PRR_PRODUCT_V3H) {
 		/* RENESAS Condor board */
@@ -1738,7 +1738,7 @@
 			/* RENESAS Kriek board with M3-W */
 			brd = 1;
 		} else if ((Prr_Product == PRR_PRODUCT_H3)
-			   && (Prr_Cut<=PRR_PRODUCT_11)) {
+			   && (Prr_Cut <= PRR_PRODUCT_11)) {
 			/* RENESAS Kriek board with PM3 */
 			brd = 13;
 		} else if ((Prr_Product == PRR_PRODUCT_H3)
diff --git a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
index bad1de9..7f27b39 100644
--- a/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
+++ b/drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
@@ -1178,9 +1178,9 @@
 #define _reg_PI_TSDO_F1                                    0x00000493U
 #define _reg_PI_TSDO_F2                                    0x00000494U
 
-#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff)
-#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff)
-#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff)
+#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffff)
+#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xff)
+#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xff)
 
 static const uint32_t DDR_REGDEF_TBL[4][1173] = {
 	{
@@ -5882,5 +5882,5 @@
 /*0492*/ 0x0808031dU,
 /*0493*/ 0x1008031dU,
 /*0494*/ 0x1808031dU,
-	 }
+	}
 };