refactor(versal-net): rename VERSAL_NET_IOU_SCNTRS register to generic
Refactor, the macro named VERSAL_NET_IOU_SCNTRS is being renamed to a more
generic macro name, which will be used in common code to enable reuse
across various platforms.
Change-Id: I548437e0fe2d73b196468bc92029f8099ea1f8d1
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_common.c b/plat/xilinx/versal_net/aarch64/versal_net_common.c
index f0cbec1..b4bc7d4 100644
--- a/plat/xilinx/versal_net/aarch64/versal_net_common.c
+++ b/plat/xilinx/versal_net/aarch64/versal_net_common.c
@@ -128,7 +128,7 @@
uintptr_t crl_base, iou_scntrs_base, psx_base;
crl_base = VERSAL_NET_CRL;
- iou_scntrs_base = VERSAL_NET_IOU_SCNTRS;
+ iou_scntrs_base = IOU_SCNTRS_BASE;
psx_base = PSX_CRF;
/* Reset for system timestamp generator in FPX */
@@ -143,10 +143,10 @@
mmio_write_32(crl_base + VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET, 0);
/* Program freq register in System counter and enable system counter. */
- mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET,
+ mmio_write_32(iou_scntrs_base + IOU_SCNTRS_BASE_FREQ_OFFSET,
cpu_clock);
- mmio_write_32(iou_scntrs_base + VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
- VERSAL_NET_IOU_SCNTRS_CONTROL_EN);
+ mmio_write_32(iou_scntrs_base + IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET,
+ IOU_SCNTRS_CONTROL_EN);
}
uint32_t plat_get_syscnt_freq2(void)
@@ -154,8 +154,8 @@
uint32_t counter_freq = 0;
uint32_t ret = 0;
- counter_freq = mmio_read_32(VERSAL_NET_IOU_SCNTRS +
- VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET);
+ counter_freq = mmio_read_32(IOU_SCNTRS_BASE +
+ IOU_SCNTRS_BASE_FREQ_OFFSET);
if (counter_freq != 0U) {
ret = counter_freq;
} else {
diff --git a/plat/xilinx/versal_net/include/versal_net_def.h b/plat/xilinx/versal_net/include/versal_net_def.h
index dd20faa..e7d234b 100644
--- a/plat/xilinx/versal_net/include/versal_net_def.h
+++ b/plat/xilinx/versal_net/include/versal_net_def.h
@@ -111,11 +111,11 @@
#define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U)
/* IOU SCNTRS */
-#define VERSAL_NET_IOU_SCNTRS U(0xEC920000)
-#define VERSAL_NET_IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0)
-#define VERSAL_NET_IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
+#define IOU_SCNTRS_BASE U(0xEC920000)
+#define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0)
+#define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20)
-#define VERSAL_NET_IOU_SCNTRS_CONTROL_EN U(1)
+#define IOU_SCNTRS_CONTROL_EN U(1)
#define APU_CLUSTER0 U(0xECC00000)
#define APU_RVBAR_L_0 U(0x40)