diff --git a/plat/imx/imx8ulp/imx8ulp_bl31_setup.c b/plat/imx/imx8ulp/imx8ulp_bl31_setup.c
index 32599f0..183e684 100644
--- a/plat/imx/imx8ulp/imx8ulp_bl31_setup.c
+++ b/plat/imx/imx8ulp/imx8ulp_bl31_setup.c
@@ -24,6 +24,7 @@
 #include <imx_plat_common.h>
 #include <plat_imx8.h>
 #include <upower_api.h>
+#include <xrdc.h>
 
 #define MAP_BL31_TOTAL										   \
 	MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE)
@@ -113,6 +114,11 @@
 
 	imx8ulp_init_scmi_server();
 	upower_init();
+
+	xrdc_apply_apd_config();
+	xrdc_apply_lpav_config();
+	xrdc_enable();
+
 	imx8ulp_caam_init();
 }
 
diff --git a/plat/imx/imx8ulp/include/xrdc.h b/plat/imx/imx8ulp/include/xrdc.h
new file mode 100644
index 0000000..15250f0
--- /dev/null
+++ b/plat/imx/imx8ulp/include/xrdc.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2021-2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX8ULP_XRDC_H
+#define IMX8ULP_XRDC_H
+
+#define DID_MAX 8
+#define PAC_SLOT_ALL 128
+#define MSC_SLOT_ALL 8
+
+enum xrdc_mda_sa {
+	MDA_SA_S,
+	MDA_SA_NS,
+	MDA_SA_PT, /* pass through master's secure/nonsecure attribute */
+};
+
+struct xrdc_mda_config {
+	uint16_t mda_id;
+	uint16_t did;
+	enum xrdc_mda_sa sa;
+};
+
+struct xrdc_pac_msc_config {
+	uint16_t pac_msc_id;
+	uint16_t slot_id;
+	uint8_t dsel[DID_MAX];
+};
+
+struct xrdc_mrc_config {
+	uint16_t mrc_id;
+	uint16_t region_id;
+	uint32_t region_start;
+	uint32_t region_size;
+	uint8_t dsel[DID_MAX];
+	uint16_t accset[2];
+};
+
+/* APIs to apply and enable XRDC */
+int xrdc_apply_lpav_config(void);
+int xrdc_apply_hifi_config(void);
+int xrdc_apply_apd_config(void);
+void xrdc_enable(void);
+
+#endif
diff --git a/plat/imx/imx8ulp/platform.mk b/plat/imx/imx8ulp/platform.mk
index e075bf4..510785a 100644
--- a/plat/imx/imx8ulp/platform.mk
+++ b/plat/imx/imx8ulp/platform.mk
@@ -31,6 +31,7 @@
 				lib/cpus/aarch64/cortex_a35.S		\
 				drivers/delay_timer/delay_timer.c	\
 				drivers/delay_timer/generic_delay_timer.c \
+				plat/imx/imx8ulp/xrdc/xrdc_core.c		\
 				plat/imx/imx8ulp/imx8ulp_caam.c         \
 				drivers/scmi-msg/base.c			\
 				drivers/scmi-msg/entry.c		\
diff --git a/plat/imx/imx8ulp/xrdc/xrdc_config.h b/plat/imx/imx8ulp/xrdc/xrdc_config.h
new file mode 100644
index 0000000..d23513e
--- /dev/null
+++ b/plat/imx/imx8ulp/xrdc/xrdc_config.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2020-2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <xrdc.h>
+
+#define SP(X)		((X) << 9)
+#define SU(X)		((X) << 6)
+#define NP(X)		((X) << 3)
+#define NU(X)		((X) << 0)
+
+#define RWX		7
+#define RW		6
+#define R		4
+#define X		1
+
+struct xrdc_mda_config imx8ulp_mda[] = {
+	{ 0, 7, MDA_SA_PT }, /* A core */
+	{ 1, 1, MDA_SA_NS }, /* DMA1 */
+	{ 2, 1, MDA_SA_NS }, /* USB */
+	{ 3, 1, MDA_SA_NS }, /* PXP-> .M10 */
+	{ 4, 1, MDA_SA_NS }, /* ENET */
+	{ 5, 1, MDA_SA_PT }, /* CAAM */
+	{ 6, 1, MDA_SA_NS }, /* USDHC0 */
+	{ 7, 1, MDA_SA_NS }, /* USDHC1 */
+	{ 8, 1, MDA_SA_NS }, /* USDHC2 */
+	{ 9, 2, MDA_SA_NS }, /* HIFI4 */
+	{ 10, 3, MDA_SA_NS }, /* GPU3D */
+	{ 11, 3, MDA_SA_NS }, /* GPU2D */
+	{ 12, 3, MDA_SA_NS }, /* EPDC */
+	{ 13, 3, MDA_SA_NS }, /* DCNano */
+	{ 14, 3, MDA_SA_NS }, /* ISI */
+	{ 15, 3, MDA_SA_NS }, /* PXP->NIC_LPAV.M0 */
+	{ 16, 3, MDA_SA_NS }, /* DMA2 */
+};
+
+struct xrdc_mrc_config imx8ulp_mrc[] = {
+	{ 0, 0, 0x0,         0x30000,    {0, 0, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* ROM1 */
+	{ 1, 0, 0x60000000,  0x10000000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* Flexspi2 */
+	{ 2, 0, 0x22020000,  0x40000,    {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM2 */
+	{ 3, 0, 0x22010000,  0x10000,    {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM0 */
+	{ 4, 0, 0x80000000,  0x80000000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* DRAM */
+	{ 5, 0, 0x80000000,  0x80000000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* DRAM */
+	{ 6, 0, 0x80000000,  0x80000000, {1, 1, 0, 1, 1, 0, 1, 0}, {0xfff, 0} }, /* DRAM for LPAV and RTD*/
+	{ 7, 0, 0x80000000,  0x10000000, {0, 0, 1, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for HIFI4 */
+	{ 7, 1, 0x90000000,  0x10000000, {0, 0, 1, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for HIFI4 */
+	{ 8, 0, 0x21000000,  0x10000,    {1, 1, 1, 1, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM1 */
+	{ 9, 0, 0x1ffc0000,  0xc0000,    {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0} }, /* SSRAM for HIFI4 */
+	{ 10, 0, 0x1ffc0000, 0xc0000,    {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0} }, /* SSRAM for LPAV */
+	{ 11, 0, 0x21170000, 0x10000,    {0, 0, 1, 0, 0, 0, 0, 2}, {0xfff, SP(RW) | SU(RW) | NP(RW)} }, /* HIFI4 TCM */
+	{ 11, 1, 0x21180000, 0x10000,    {0, 0, 1, 0, 0, 0, 0, 2}, {SP(RW) | SU(RW) | NP(RW) | NU(RW), SP(RW) | SU(RW) | NP(RW)} }, /* HIFI4 TCM */
+	{ 12, 0, 0x2d400000, 0x100000,   {0, 0, 0, 0, 0, 0, 0, 1}, {SP(RW) | SU(RW) | NP(RW) | NU(RW), 0} }, /* GIC500 */
+};
+
+struct xrdc_pac_msc_config imx8ulp_pdac[] = {
+	{ 0, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC0 */
+	{ 0, 36, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 36 for CMC1 */
+	{ 0, 41, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 41 for SIM_AD */
+	{ 1, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC1 */
+	{ 1, 0, {0, 7, 0, 0, 0, 0, 7, 7} }, /* PAC1 slot 0 for PCC4 */
+	{ 1, 6, {0, 7, 7, 0, 0, 0, 0, 7} }, /* PAC1 slot 6 for LPUART6 */
+	{ 1, 9,  {0, 7, 7, 7, 0, 0, 0, 7} }, /* SAI5 for HIFI4 and eDMA2 */
+	{ 1, 12, {0, 7, 0, 0, 0, 0, 7, 7} }, /* PAC1 slot 12 for IOMUXC1 */
+	{ 2, PAC_SLOT_ALL, {7, 7, 7, 7, 0, 0, 7, 7} }, /* PAC2 */
+};
+
+struct xrdc_pac_msc_config imx8ulp_msc[] = {
+	{ 0, 0, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC0 GPIOE */
+	{ 0, 1, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC0 GPIOF */
+	{ 1, MSC_SLOT_ALL, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC1 GPIOD */
+	{ 2, MSC_SLOT_ALL, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC2 GPU3D/2D/DCNANO/DDR registers */
+};
diff --git a/plat/imx/imx8ulp/xrdc/xrdc_core.c b/plat/imx/imx8ulp/xrdc/xrdc_core.c
new file mode 100644
index 0000000..2e6d31c
--- /dev/null
+++ b/plat/imx/imx8ulp/xrdc/xrdc_core.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright 2020-2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+#include "xrdc_config.h"
+
+#define XRDC_ADDR	0x292f0000
+#define MRC_OFFSET	0x2000
+#define MRC_STEP	0x200
+
+#define XRDC_MGR_PAC_ID	  U(0)
+#define XRDC_MGR_PAC_SLOT U(47)
+
+enum xrdc_comp_type {
+	MDA_TYPE = (1 << 16),
+	MRC_TYPE = (2 << 16),
+	PAC_TYPE = (3 << 16),
+	MSC_TYPE = (4 << 16),
+};
+
+enum xrdc_pd_type {
+	XRDC_AD_PD,
+	XRDC_HIFI_PD,
+	XRDC_AV_PD,
+};
+
+#define XRDC_TYPE_MASK (0x7 << 16)
+#define XRDC_ID_MASK 0xFFFF
+#define XRDC_ID(id) ((id) & XRDC_ID_MASK)
+
+typedef bool (*xrdc_check_func)(enum xrdc_comp_type type, uint16_t id);
+
+/* Access below XRDC needs enable PS 8
+ * and HIFI clocks and release HIFI firstly
+ */
+uint32_t hifi_xrdc_list[] = {
+	(MDA_TYPE | XRDC_ID(9)),
+	(MRC_TYPE | XRDC_ID(7)),
+	(MRC_TYPE | XRDC_ID(9)),
+	(MRC_TYPE | XRDC_ID(11)),
+};
+
+/* Access below XRDC needs enable PS 16 firstly */
+uint32_t av_periph_xrdc_list[] = {
+	(MDA_TYPE | XRDC_ID(10)),
+	(MDA_TYPE | XRDC_ID(11)),
+	(MDA_TYPE | XRDC_ID(12)),
+	(MDA_TYPE | XRDC_ID(13)),
+	(MDA_TYPE | XRDC_ID(14)),
+	(MDA_TYPE | XRDC_ID(15)),
+	(MDA_TYPE | XRDC_ID(16)),
+
+	(PAC_TYPE | XRDC_ID(2)),
+
+	(MRC_TYPE | XRDC_ID(6)),
+	(MRC_TYPE | XRDC_ID(8)),
+	(MRC_TYPE | XRDC_ID(10)),
+
+	(MSC_TYPE | XRDC_ID(1)),
+	(MSC_TYPE | XRDC_ID(2)),
+};
+
+uint32_t imx8ulp_pac_slots[] = {
+	61, 23, 53
+};
+
+uint32_t imx8ulp_msc_slots[] = {
+	2, 1, 7
+};
+
+static int xrdc_config_mrc_w0_w1(uint32_t mrc_con, uint32_t region, uint32_t w0, uint32_t size)
+{
+
+	uint32_t w0_addr, w1_addr;
+
+	w0_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20;
+	w1_addr = w0_addr + 4;
+
+	if ((size % 32) != 0) {
+		return -EINVAL;
+	}
+
+	mmio_write_32(w0_addr, w0 & ~0x1f);
+	mmio_write_32(w1_addr, w0 + size - 1);
+
+	return 0;
+}
+
+static int xrdc_config_mrc_w2(uint32_t mrc_con, uint32_t region, uint32_t dxsel_all)
+{
+	uint32_t w2_addr;
+
+	w2_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0x8;
+
+	mmio_write_32(w2_addr, dxsel_all);
+
+	return 0;
+}
+
+static int xrdc_config_mrc_w3_w4(uint32_t mrc_con, uint32_t region, uint32_t w3, uint32_t w4)
+{
+	uint32_t w3_addr = XRDC_ADDR + MRC_OFFSET + mrc_con * 0x200 + region * 0x20 + 0xC;
+	uint32_t w4_addr = w3_addr + 4;
+
+	mmio_write_32(w3_addr, w3);
+	mmio_write_32(w4_addr, w4);
+
+	return 0;
+}
+
+static int xrdc_config_pac(uint32_t pac, uint32_t index, uint32_t dxacp)
+{
+	uint32_t w0_addr;
+	uint32_t val;
+
+	if (pac > 2U) {
+		return -EINVAL;
+	}
+
+	/* Skip the PAC slot for XRDC MGR, use Sentinel configuration */
+	if (pac == XRDC_MGR_PAC_ID && index == XRDC_MGR_PAC_SLOT) {
+		return 0;
+	}
+
+	w0_addr = XRDC_ADDR + 0x1000 + 0x400 * pac + 0x8 * index;
+
+	mmio_write_32(w0_addr, dxacp);
+
+	val = mmio_read_32(w0_addr + 4);
+	mmio_write_32(w0_addr + 4, val | BIT_32(31));
+
+	return 0;
+}
+
+static int xrdc_config_msc(uint32_t msc, uint32_t index, uint32_t dxacp)
+{
+	uint32_t w0_addr;
+	uint32_t val;
+
+	if (msc > 2) {
+		return -EINVAL;
+	}
+
+	w0_addr = XRDC_ADDR + 0x4000 + 0x400 * msc + 0x8 * index;
+
+	mmio_write_32(w0_addr, dxacp);
+
+	val = mmio_read_32(w0_addr + 4);
+	mmio_write_32(w0_addr + 4, val | BIT_32(31));
+
+	return 0;
+}
+
+static int xrdc_config_mda(uint32_t mda_con, uint32_t dom, enum xrdc_mda_sa sa)
+{
+	uint32_t w0_addr;
+	uint32_t val;
+
+	w0_addr = XRDC_ADDR + 0x800 + mda_con * 0x20;
+
+	val = mmio_read_32(w0_addr);
+
+	if (val & BIT_32(29)) {
+		mmio_write_32(w0_addr, (val & (~0xFF)) | dom |
+			      BIT_32(31) | 0x20 | ((sa & 0x3) << 6));
+	} else {
+		mmio_write_32(w0_addr, dom | BIT_32(31));
+		mmio_write_32(w0_addr + 0x4, dom | BIT_32(31));
+	}
+
+	return 0;
+}
+
+static bool xrdc_check_pd(enum xrdc_comp_type type,
+			  uint16_t id, enum xrdc_pd_type pd)
+{
+	unsigned int i, size;
+	uint32_t item = type | XRDC_ID(id);
+	uint32_t *list;
+
+	if (pd == XRDC_HIFI_PD) {
+		size = ARRAY_SIZE(hifi_xrdc_list);
+		list = hifi_xrdc_list;
+	} else if (pd == XRDC_AV_PD) {
+		size = ARRAY_SIZE(av_periph_xrdc_list);
+		list = av_periph_xrdc_list;
+	} else {
+		return false;
+	}
+
+	for (i = 0U; i < size; i++) {
+		if (item == list[i]) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static bool xrdc_check_lpav(enum xrdc_comp_type type, uint16_t id)
+{
+	return xrdc_check_pd(type, id, XRDC_AV_PD);
+}
+
+static bool xrdc_check_hifi(enum xrdc_comp_type type, uint16_t id)
+{
+	return xrdc_check_pd(type, id, XRDC_HIFI_PD);
+}
+
+static bool xrdc_check_ad(enum xrdc_comp_type type, uint16_t id)
+{
+	return (!xrdc_check_pd(type, id, XRDC_HIFI_PD) &&
+			!xrdc_check_pd(type, id, XRDC_AV_PD));
+}
+
+static int xrdc_apply_config(xrdc_check_func check_func)
+{
+	unsigned int i, j;
+	uint32_t val;
+
+	for (i = 0U; i < ARRAY_SIZE(imx8ulp_mda); i++) {
+		if (check_func(MDA_TYPE, imx8ulp_mda[i].mda_id)) {
+			xrdc_config_mda(imx8ulp_mda[i].mda_id,
+					imx8ulp_mda[i].did, imx8ulp_mda[i].sa);
+		}
+	}
+
+	for (i = 0U; i < ARRAY_SIZE(imx8ulp_mrc); i++) {
+		if (check_func(MRC_TYPE, imx8ulp_mrc[i].mrc_id)) {
+			xrdc_config_mrc_w0_w1(imx8ulp_mrc[i].mrc_id,
+					      imx8ulp_mrc[i].region_id,
+					      imx8ulp_mrc[i].region_start,
+					      imx8ulp_mrc[i].region_size);
+
+			val = 0;
+			for (j = 0U; j < DID_MAX; j++) {
+				val |= imx8ulp_mrc[i].dsel[j] << (3 * j);
+			}
+
+			xrdc_config_mrc_w2(imx8ulp_mrc[i].mrc_id, imx8ulp_mrc[i].region_id, val);
+			xrdc_config_mrc_w3_w4(imx8ulp_mrc[i].mrc_id, imx8ulp_mrc[i].region_id,
+				0, imx8ulp_mrc[i].accset[0] | (imx8ulp_mrc[i].accset[1] << 16) | BIT_32(31));
+		}
+	}
+
+	for (i = 0U; i < ARRAY_SIZE(imx8ulp_pdac); i++) {
+		if (check_func(PAC_TYPE, imx8ulp_pdac[i].pac_msc_id)) {
+			val = 0;
+			for (j = 0U; j < DID_MAX; j++) {
+				val |= imx8ulp_pdac[i].dsel[j] << (3 * j);
+			}
+
+			if (imx8ulp_pdac[i].slot_id == PAC_SLOT_ALL) {
+				/* Apply to all slots*/
+				for (j = 0U; j < imx8ulp_pac_slots[imx8ulp_pdac[i].pac_msc_id]; j++) {
+					xrdc_config_pac(imx8ulp_pdac[i].pac_msc_id, j, val);
+				}
+			} else {
+				if (imx8ulp_pdac[i].slot_id >= imx8ulp_pac_slots[imx8ulp_pdac[i].pac_msc_id]) {
+					return -EINVAL;
+				}
+
+				xrdc_config_pac(imx8ulp_pdac[i].pac_msc_id, imx8ulp_pdac[i].slot_id, val);
+			}
+		}
+	}
+
+	for (i = 0U; i < ARRAY_SIZE(imx8ulp_msc); i++) {
+		if (check_func(MSC_TYPE, imx8ulp_msc[i].pac_msc_id)) {
+			val = 0;
+			for (j = 0U; j < DID_MAX; j++) {
+				val |= imx8ulp_msc[i].dsel[j] << (3 * j);
+			}
+
+			if (imx8ulp_msc[i].slot_id == MSC_SLOT_ALL) {
+				/* Apply to all slots*/
+				for (j = 0U; j < imx8ulp_msc_slots[imx8ulp_msc[i].pac_msc_id]; j++) {
+					xrdc_config_msc(imx8ulp_msc[i].pac_msc_id, j, val);
+				}
+			} else {
+				if (imx8ulp_msc[i].slot_id >= imx8ulp_msc_slots[imx8ulp_msc[i].pac_msc_id]) {
+					return -EINVAL;
+				}
+
+				xrdc_config_msc(imx8ulp_msc[i].pac_msc_id, imx8ulp_msc[i].slot_id, val);
+			}
+		}
+	}
+
+	return 0;
+}
+
+int xrdc_apply_lpav_config(void)
+{
+	/* Enable the eDMA2 MP clock for MDA16 access */
+	mmio_write_32(IMX_PCC5_BASE + 0x0, 0xc0000000);
+	return xrdc_apply_config(xrdc_check_lpav);
+}
+
+int xrdc_apply_hifi_config(void)
+{
+	return xrdc_apply_config(xrdc_check_hifi);
+}
+
+int xrdc_apply_apd_config(void)
+{
+	return xrdc_apply_config(xrdc_check_ad);
+}
+
+void xrdc_enable(void)
+{
+	mmio_write_32(XRDC_ADDR, BIT(14) | BIT(15) | BIT(0));
+}