| commit | fda03c9ebea3f57ba28857bf898f795b0eac79e6 | [log] [tgz] |
|---|---|---|
| author | Ang Tien Sung <tien.sung.ang@intel.com> | Mon Mar 13 09:32:40 2023 +0800 |
| committer | Sieu Mun Tang <sieu.mun.tang@intel.com> | Tue Apr 11 00:17:00 2023 +0800 |
| tree | 11527690b64f5bc69481f339c30114a8dec64041 | |
| parent | 84f8ae8808aa6c06c3d9242244ff421e6045ff21 [diff] |
feat(intel): fix bridge disable and reset Fix bridge sideband manager register clear and set incorrect implementation. To support non-graceful full bridge disable and enable. Signed-off-by: Ang Tien Sung <tien.sung.ang@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com> Change-Id: I651f3ec163d954e8efb0542ec33bce96e51992db