Merge "spm: Add spci manifest binding document" into integration
diff --git a/Makefile b/Makefile
index 47a544d..8049a18 100644
--- a/Makefile
+++ b/Makefile
@@ -364,7 +364,8 @@
endif
DTC_FLAGS += -I dts -O dtb
-DTC_CPPFLAGS += -P -nostdinc -Iinclude -Ifdts -undef -x assembler-with-cpp
+DTC_CPPFLAGS += -P -nostdinc -Iinclude -Ifdts -undef \
+ -x assembler-with-cpp $(DEFINES)
################################################################################
# Common sources and include directories
@@ -826,7 +827,7 @@
$(eval $(call assert_boolean,TRUSTED_BOARD_BOOT))
$(eval $(call assert_boolean,USE_COHERENT_MEM))
$(eval $(call assert_boolean,USE_DEBUGFS))
-$(eval $(call assert_boolean,USE_FCONF_BASED_IO))
+$(eval $(call assert_boolean,ARM_IO_IN_DTB))
$(eval $(call assert_boolean,USE_ROMLIB))
$(eval $(call assert_boolean,USE_TBBR_DEFS))
$(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY))
@@ -904,7 +905,7 @@
$(eval $(call add_define,TRUSTED_BOARD_BOOT))
$(eval $(call add_define,USE_COHERENT_MEM))
$(eval $(call add_define,USE_DEBUGFS))
-$(eval $(call add_define,USE_FCONF_BASED_IO))
+$(eval $(call add_define,ARM_IO_IN_DTB))
$(eval $(call add_define,USE_ROMLIB))
$(eval $(call add_define,USE_TBBR_DEFS))
$(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY))
@@ -938,13 +939,18 @@
endif
# Generate and include sp_gen.mk if SPD is spmd and SP_LAYOUT_FILE is defined
-ifdef SP_LAYOUT_FILE
ifeq (${SPD},spmd)
+ifdef SP_LAYOUT_FILE
+ ifeq (${SPMD_SPM_AT_SEL2},0)
+ $(error "SPMD with SPM at S-EL1 does not require SP_LAYOUT_FILE")
+ endif
-include $(BUILD_PLAT)/sp_gen.mk
FIP_DEPS += sp
NEED_SP_PKG := yes
else
- $(error "SP_LAYOUT_FILE will be used only if SPD=spmd")
+ ifeq (${SPMD_SPM_AT_SEL2},1)
+ $(error "SPMD with SPM at S-EL2 require SP_LAYOUT_FILE")
+ endif
endif
endif
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index 9da2f9a..e947838 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -371,12 +371,16 @@
tsp_stats[linear_id].smc_count++;
tsp_stats[linear_id].eret_count++;
+#if LOG_LEVEL >= LOG_LEVEL_INFO
+ spin_lock(&console_lock);
INFO("TSP: cpu 0x%lx received %s smc 0x%llx\n", read_mpidr(),
((func >> 31) & 1) == 1 ? "fast" : "yielding",
func);
INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count);
+ spin_unlock(&console_lock);
+#endif
/* Render secure services and obtain results here */
results[0] = arg1;
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 2bf5eb7..9e55e60 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -217,6 +217,17 @@
:G: `grandpaul`_
:F: docs/plat/rpi3.rst
:F: plat/rpi/rpi3/
+:F: plat/rpi/common/
+:F: drivers/rpi3/
+:F: include/drivers/rpi3/
+
+Raspberry Pi 4 platform port
+----------------------------
+:M: Andre Przywara <andre.przywara@arm.com>
+:G: `Andre-ARM`_
+:F: docs/plat/rpi4.rst
+:F: plat/rpi/rpi4/
+:F: plat/rpi/common/
:F: drivers/rpi3/
:F: include/drivers/rpi3/
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index f138feb..e53f714 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -622,8 +622,8 @@
exposing a virtual filesystem interface through BL31 as a SiP SMC function.
Default is 0.
-- ``USE_FCONF_BASED_IO``: This flag determines whether to use IO based on the
- firmware configuration framework. This allows moving the io_policies into a
+- ``ARM_IO_IN_DTB``: This flag determines whether to use IO based on the
+ firmware configuration framework. This will move the io_policies into a
configuration device tree, instead of static structure in the code base.
diff --git a/docs/plat/hikey.rst b/docs/plat/hikey.rst
index 372d388..6c488b8 100644
--- a/docs/plat/hikey.rst
+++ b/docs/plat/hikey.rst
@@ -26,9 +26,6 @@
- l-loader:
`link <https://github.com/96boards-hikey/l-loader/tree/testing/hikey960_v1.2>`__
-- uefi-tools:
- `link <https://git.linaro.org/uefi/uefi-tools.git>`__
-
- atf-fastboot:
`link <https://github.com/96boards-hikey/atf-fastboot/tree/master>`__
@@ -45,7 +42,6 @@
git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
- git clone https://git.linaro.org/uefi/uefi-tools
git clone https://github.com/96boards-hikey/atf-fastboot
- Create the symbol link to OpenPlatformPkg in edk2.
@@ -57,13 +53,12 @@
- Prepare AARCH64 && AARCH32 toolchain. Prepare python.
-- If your hikey hardware is built by CircuitCo, update *uefi-tools/platform.config* first. *(optional)*
- **Uncomment the below sentence. Otherwise, UEFI can't output messages on serial
+- If your hikey hardware is built by CircuitCo, update *OpenPlatformPkg/Platforms/Hisilicon/HiKey/HiKey.dsc* first. *(optional)*
console on hikey.**
.. code:: shell
- BUILDFLAGS=-DSERIAL_BASE=0xF8015000
+ DEFINE SERIAL_BASE=0xF8015000
If your hikey hardware is built by LeMaker, nothing to do.
@@ -71,19 +66,8 @@
.. code:: shell
- BUILD_OPTION=DEBUG
- export AARCH64_TOOLCHAIN=GCC5
- export UEFI_TOOLS_DIR=${BUILD_PATH}/uefi-tools
- export EDK2_DIR=${BUILD_PATH}/edk2
- EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey/${BUILD_OPTION}_${AARCH64_TOOLCHAIN}
- # Build fastboot for Trusted Firmware-A. It's used for recovery mode.
- cd ${BUILD_PATH}/atf-fastboot
- CROSS_COMPILE=aarch64-linux-gnu- make PLAT=hikey DEBUG=1
- # Convert DEBUG/RELEASE to debug/release
- FASTBOOT_BUILD_OPTION=$(echo ${BUILD_OPTION} | tr '[A-Z]' '[a-z]')
- cd ${EDK2_DIR}
- # Build UEFI & Trusted Firmware-A
- ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey
+ cd {BUILD_PATH}/arm-trusted-firmware
+ sh ../l-loader/build_uefi.sh hikey
- Generate l-loader.bin and partition table for aosp. The eMMC capacity is either 8GB or 4GB. Just change "aosp-8g" to "linux-8g" for debian.
diff --git a/docs/plat/hikey960.rst b/docs/plat/hikey960.rst
index 3d42a77..982c2c8 100644
--- a/docs/plat/hikey960.rst
+++ b/docs/plat/hikey960.rst
@@ -26,9 +26,6 @@
- l-loader:
`link <https://github.com/96boards-hikey/l-loader/tree/testing/hikey960_v1.2>`__
-- uefi-tools:
- `link <https://git.linaro.org/uefi/uefi-tools.git>`__
-
Build Procedure
~~~~~~~~~~~~~~~
@@ -42,7 +39,6 @@
git clone https://github.com/96boards-hikey/edk2 -b testing/hikey960_v2.5
git clone https://github.com/96boards-hikey/OpenPlatformPkg -b testing/hikey960_v1.3.4
git clone https://github.com/96boards-hikey/l-loader -b testing/hikey960_v1.2
- git clone https://git.linaro.org/uefi/uefi-tools
- Create the symbol link to OpenPlatformPkg in edk2.
@@ -53,13 +49,11 @@
- Prepare AARCH64 toolchain.
-- If your hikey960 hardware is v1, update *uefi-tools/platform.config* first. *(optional)*
- **Uncomment the below sentence. Otherwise, UEFI can't output messages on serial
- console on hikey960 v1.**
+- If your hikey960 hardware is v1, update *OpenPlatformPkg/Platforms/Hisilicon/HiKey960/HiKey960.dsc* first. *(optional)*
.. code:: shell
- BUILDFLAGS=-DSERIAL_BASE=0xFDF05000
+ DEFINE SERIAL_BASE=0xFDF05000
If your hikey960 hardware is v2 or newer, nothing to do.
@@ -67,14 +61,8 @@
.. code:: shell
- BUILD_OPTION=DEBUG
- export AARCH64_TOOLCHAIN=GCC5
- export UEFI_TOOLS_DIR=${BUILD_PATH}/uefi-tools
- export EDK2_DIR=${BUILD_PATH}/edk2
- EDK2_OUTPUT_DIR=${EDK2_DIR}/Build/HiKey960/${BUILD_OPTION}_${AARCH64_TOOLCHAIN}
- cd ${EDK2_DIR}
- # Build UEFI & Trusted Firmware-A
- ${UEFI_TOOLS_DIR}/uefi-build.sh -b ${BUILD_OPTION} -a ../arm-trusted-firmware -s ../optee_os hikey960
+ cd {BUILD_PATH}/arm-trusted-firmware
+ sh ../l-loader/build_uefi.sh hikey960
- Generate l-loader.bin and partition table.
*Make sure that you're using the sgdisk in the l-loader directory.*
diff --git a/drivers/rpi3/gpio/rpi3_gpio.c b/drivers/rpi3/gpio/rpi3_gpio.c
index b39808f..f938f56 100644
--- a/drivers/rpi3/gpio/rpi3_gpio.c
+++ b/drivers/rpi3/gpio/rpi3_gpio.c
@@ -11,7 +11,7 @@
#include <drivers/delay_timer.h>
#include <drivers/rpi3/gpio/rpi3_gpio.h>
-static struct rpi3_gpio_params rpi3_gpio_params;
+static uintptr_t reg_base;
static int rpi3_gpio_get_direction(int gpio);
static void rpi3_gpio_set_direction(int gpio, int direction);
@@ -43,7 +43,6 @@
int rpi3_gpio_get_select(int gpio)
{
int ret;
- uintptr_t reg_base = rpi3_gpio_params.reg_base;
int regN = gpio / 10;
int shift = 3 * (gpio % 10);
uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN);
@@ -69,7 +68,6 @@
*/
void rpi3_gpio_set_select(int gpio, int fsel)
{
- uintptr_t reg_base = rpi3_gpio_params.reg_base;
int regN = gpio / 10;
int shift = 3 * (gpio % 10);
uintptr_t reg_sel = reg_base + RPI3_GPIO_GPFSEL(regN);
@@ -106,7 +104,6 @@
static int rpi3_gpio_get_value(int gpio)
{
- uintptr_t reg_base = rpi3_gpio_params.reg_base;
int regN = gpio / 32;
int shift = gpio % 32;
uintptr_t reg_lev = reg_base + RPI3_GPIO_GPLEV(regN);
@@ -119,7 +116,6 @@
static void rpi3_gpio_set_value(int gpio, int value)
{
- uintptr_t reg_base = rpi3_gpio_params.reg_base;
int regN = gpio / 32;
int shift = gpio % 32;
uintptr_t reg_set = reg_base + RPI3_GPIO_GPSET(regN);
@@ -137,7 +133,6 @@
static void rpi3_gpio_set_pull(int gpio, int pull)
{
- uintptr_t reg_base = rpi3_gpio_params.reg_base;
int regN = gpio / 32;
int shift = gpio % 32;
uintptr_t reg_pud = reg_base + RPI3_GPIO_GPPUD;
@@ -161,9 +156,8 @@
mmio_write_32(reg_pud, 0x0);
}
-void rpi3_gpio_init(struct rpi3_gpio_params *params)
+void rpi3_gpio_init(void)
{
- assert(params != 0);
- memcpy(&rpi3_gpio_params, params, sizeof(struct rpi3_gpio_params));
+ reg_base = RPI3_GPIO_BASE;
gpio_init(&rpi3_gpio_ops);
}
diff --git a/drivers/st/fmc/stm32_fmc2_nand.c b/drivers/st/fmc/stm32_fmc2_nand.c
index b694fff..d2d7e06 100644
--- a/drivers/st/fmc/stm32_fmc2_nand.c
+++ b/drivers/st/fmc/stm32_fmc2_nand.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -365,7 +365,7 @@
xor_ecc_2b = ecc[1] ^ eccbuffer[1];
xor_ecc_3b = ecc[2] ^ eccbuffer[2];
- xor_ecc.val = 0L;
+ xor_ecc.val = 0U;
xor_ecc.bytes[2] = xor_ecc_3b;
xor_ecc.bytes[1] = xor_ecc_2b;
xor_ecc.bytes[0] = xor_ecc_1b;
diff --git a/drivers/st/io/io_stm32image.c b/drivers/st/io/io_stm32image.c
index 413521b..3e377cd 100644
--- a/drivers/st/io/io_stm32image.c
+++ b/drivers/st/io/io_stm32image.c
@@ -247,7 +247,7 @@
size_t length, size_t *length_read)
{
int result;
- uint8_t *local_buffer = (uint8_t *)buffer;
+ uint8_t *local_buffer;
boot_api_image_header_t *header =
(boot_api_image_header_t *)first_lba_buffer;
@@ -255,6 +255,7 @@
assert(buffer != 0U);
assert(length_read != NULL);
+ local_buffer = (uint8_t *)buffer;
*length_read = 0U;
while (*length_read == 0U) {
diff --git a/drivers/st/spi/stm32_qspi.c b/drivers/st/spi/stm32_qspi.c
index 188d2ff..c5e4ea8 100644
--- a/drivers/st/spi/stm32_qspi.c
+++ b/drivers/st/spi/stm32_qspi.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -12,6 +12,7 @@
#include <drivers/delay_timer.h>
#include <drivers/spi_mem.h>
#include <drivers/st/stm32_gpio.h>
+#include <drivers/st/stm32_qspi.h>
#include <drivers/st/stm32mp_reset.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
@@ -172,9 +173,8 @@
static int stm32_qspi_poll(const struct spi_mem_op *op)
{
void (*fifo)(uint8_t *val, uintptr_t addr);
- uint32_t len = op->data.nbytes;
+ uint32_t len;
uint8_t *buf;
- uint64_t timeout;
if (op->data.dir == SPI_MEM_DATA_IN) {
fifo = stm32_qspi_read_fifo;
@@ -185,7 +185,8 @@
buf = (uint8_t *)op->data.buf;
for (len = op->data.nbytes; len != 0U; len--) {
- timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US);
+ uint64_t timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US);
+
while ((mmio_read_32(qspi_base() + QSPI_SR) &
QSPI_SR_FTF) == 0U) {
if (timeout_elapsed(timeout)) {
diff --git a/fdts/corstone700.dts b/fdts/corstone700.dts
index c13d3b2..851f5e6 100644
--- a/fdts/corstone700.dts
+++ b/fdts/corstone700.dts
@@ -15,8 +15,6 @@
chosen {
bootargs = "console=ttyAMA0 \
- root=mtd:physmap-flash.0 \
- ro \
loglevel=9";
};
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S
index 7559de4..4fd746d 100644
--- a/include/arch/aarch32/el3_common_macros.S
+++ b/include/arch/aarch32/el3_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -329,6 +329,11 @@
bl inv_dcache_range
#endif
+ /*
+ * zeromem uses r12 whereas it is used to save previous BL arg3,
+ * save it in r7
+ */
+ mov r7, r12
ldr r0, =__BSS_START__
ldr r1, =__BSS_SIZE__
bl zeromem
@@ -339,6 +344,9 @@
bl zeromem
#endif
+ /* Restore r12 */
+ mov r12, r7
+
#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM)
/* -----------------------------------------------------
* Copy data from ROM to RAM.
diff --git a/include/bl32/payloads/tlk.h b/include/bl32/payloads/tlk.h
index fe6f352..290f329 100644
--- a/include/bl32/payloads/tlk.h
+++ b/include/bl32/payloads/tlk.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,10 +24,12 @@
#define TLK_SS_REGISTER_HANDLER TLK_TOS_YIELD_FID(0x3)
#define TLK_REGISTER_NS_DRAM_RANGES TLK_TOS_YIELD_FID(0x4)
#define TLK_SET_ROOT_OF_TRUST TLK_TOS_YIELD_FID(0x5)
+#define TLK_SET_BL_VERSION TLK_TOS_YIELD_FID(0x6)
+#define TLK_LOCK_BL_INTERFACE TLK_TOS_YIELD_FID(0x7)
+#define TLK_BL_RPMB_SERVICE TLK_TOS_YIELD_FID(0x8)
#define TLK_RESUME_FID TLK_TOS_YIELD_FID(0x100)
#define TLK_SYSTEM_SUSPEND TLK_TOS_YIELD_FID(0xE001)
#define TLK_SYSTEM_RESUME TLK_TOS_YIELD_FID(0xE002)
-#define TLK_SYSTEM_OFF TLK_TOS_YIELD_FID(0xE003)
#define TLK_IRQ_FIRED TLK_TOS_YIELD_FID(0xE004)
/*
@@ -39,7 +42,6 @@
#define TLK_VA_TRANSLATE (0x32000004 | (ULL(1) << 31))
#define TLK_SUSPEND_DONE (0x32000005 | (ULL(1) << 31))
#define TLK_RESUME_DONE (0x32000006 | (ULL(1) << 31))
-#define TLK_SYSTEM_OFF_DONE (0x32000007 | (ULL(1) << 31))
#define TLK_IRQ_DONE (0x32000008 | (ULL(1) << 31))
/*
diff --git a/include/drivers/raw_nand.h b/include/drivers/raw_nand.h
index 18e4b73..9018f02 100644
--- a/include/drivers/raw_nand.h
+++ b/include/drivers/raw_nand.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,7 @@
#ifndef DRIVERS_RAW_NAND_H
#define DRIVERS_RAW_NAND_H
+#include <cdefs.h>
#include <stdint.h>
#include <drivers/nand.h>
diff --git a/include/drivers/rpi3/gpio/rpi3_gpio.h b/include/drivers/rpi3/gpio/rpi3_gpio.h
index 159a2e0..7bb3ee2 100644
--- a/include/drivers/rpi3/gpio/rpi3_gpio.h
+++ b/include/drivers/rpi3/gpio/rpi3_gpio.h
@@ -11,11 +11,7 @@
#include <stdint.h>
#include <drivers/gpio.h>
-struct rpi3_gpio_params {
- uintptr_t reg_base;
-};
-
-void rpi3_gpio_init(struct rpi3_gpio_params *params);
+void rpi3_gpio_init(void);
int rpi3_gpio_get_select(int gpio);
void rpi3_gpio_set_select(int gpio, int fsel);
diff --git a/include/lib/cpus/aarch64/denver.h b/include/lib/cpus/aarch64/denver.h
index 02657a0..b98abdf 100644
--- a/include/lib/cpus/aarch64/denver.h
+++ b/include/lib/cpus/aarch64/denver.h
@@ -34,6 +34,11 @@
#define DENVER_CPU_PMSTATE_C7 U(0x7)
#define DENVER_CPU_PMSTATE_MASK U(0xF)
+/* ACTRL_ELx bits to enable dual execution*/
+#define DENVER_CPU_ENABLE_DUAL_EXEC_EL2 (ULL(1) << 9)
+#define DENVER_CPU_ENABLE_DUAL_EXEC_EL3 (ULL(1) << 9)
+#define DENVER_CPU_ENABLE_DUAL_EXEC_EL1 (U(1) << 4)
+
#ifndef __ASSEMBLER__
/* Disable Dynamic Code Optimisation */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index e061950..0029658 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -183,7 +183,7 @@
#define CTX_SPSR_EL2 U(0xd0)
#define CTX_SP_EL2 U(0xd8)
#define CTX_TCR_EL2 U(0xe0)
-#define CTX_TRFCR_EL2 U(0xe8)
+#define CTX_TPIDR_EL2 U(0xe8)
#define CTX_TTBR0_EL2 U(0xf0)
#define CTX_VBAR_EL2 U(0xf8)
#define CTX_VMPIDR_EL2 U(0x100)
@@ -234,11 +234,13 @@
#define CTX_VSESR_EL2 U(0x228)
#define CTX_VSTCR_EL2 U(0x230)
#define CTX_VSTTBR_EL2 U(0x238)
+#define CTX_TRFCR_EL2 U(0x240)
// Starting with Armv8.5
-#define CTX_SCXTNUM_EL2 U(0x240)
+#define CTX_SCXTNUM_EL2 U(0x248)
/* Align to the next 16 byte boundary */
#define CTX_EL2_SYSREGS_END U(0x250)
+
#endif /* CTX_INCLUDE_EL2_REGS */
/*******************************************************************************
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 30ad7b7..221f33e 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -100,7 +100,7 @@
stp x10, x11, [x0, #CTX_SPSR_EL2]
mrs x12, tcr_el2
- mrs x13, TRFCR_EL2
+ mrs x13, tpidr_el2
stp x12, x13, [x0, #CTX_TCR_EL2]
mrs x14, ttbr0_el2
@@ -204,11 +204,14 @@
mrs x16, vsttbr_el2
str x16, [x0, #CTX_VSTTBR_EL2]
+
+ mrs x17, TRFCR_EL2
+ str x17, [x0, #CTX_TRFCR_EL2]
#endif
#if ARM_ARCH_AT_LEAST(8, 5)
- mrs x17, scxtnum_el2
- str x17, [x0, #CTX_SCXTNUM_EL2]
+ mrs x9, scxtnum_el2
+ str x9, [x0, #CTX_SCXTNUM_EL2]
#endif
ret
@@ -289,7 +292,7 @@
ldp x12, x13, [x0, #CTX_TCR_EL2]
msr tcr_el2, x12
- msr TRFCR_EL2, x13
+ msr tpidr_el2, x13
ldp x14, x15, [x0, #CTX_TTBR0_EL2]
msr ttbr0_el2, x14
@@ -391,11 +394,14 @@
ldr x16, [x0, #CTX_VSTTBR_EL2]
msr vsttbr_el2, x16
+
+ ldr x17, [x0, #CTX_TRFCR_EL2]
+ msr TRFCR_EL2, x17
#endif
#if ARM_ARCH_AT_LEAST(8, 5)
- ldr x17, [x0, #CTX_SCXTNUM_EL2]
- msr scxtnum_el2, x17
+ ldr x9, [x0, #CTX_SCXTNUM_EL2]
+ msr scxtnum_el2, x9
#endif
ret
diff --git a/lib/fconf/fconf.c b/lib/fconf/fconf.c
index 9ce4635..3007273 100644
--- a/lib/fconf/fconf.c
+++ b/lib/fconf/fconf.c
@@ -33,7 +33,7 @@
err = load_auth_image(TB_FW_CONFIG_ID, &arm_tb_fw_info);
if (err != 0) {
/* Return if FW_CONFIG is not loaded */
- VERBOSE("Failed to load FW_CONFIG\n");
+ WARN("Failed to load FW_CONFIG\n");
return;
}
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 03322db..4e968e2 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -223,7 +223,7 @@
USE_DEBUGFS := 0
# Build option to fconf based io
-USE_FCONF_BASED_IO := 0
+ARM_IO_IN_DTB := 0
# Build option to choose whether Trusted Firmware uses library at ROM
USE_ROMLIB := 0
diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
index 0e204d0..702db77 100644
--- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
+++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
@@ -29,9 +29,9 @@
#define SUNXI_SID_BASE 0x03006000
#define SUNXI_DMA_BASE 0x03002000
#define SUNXI_MSGBOX_BASE 0x03003000
-#define SUNXI_CCU_BASE 0x03010000
+#define SUNXI_CCU_BASE 0x03001000
#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0xf00)
-#define SUNXI_PIO_BASE 0x030b0000
+#define SUNXI_PIO_BASE 0x0300b000
#define SUNXI_TIMER_BASE 0x03009000
#define SUNXI_WDOG_BASE 0x030090a0
#define SUNXI_THS_BASE 0x05070400
diff --git a/plat/arm/board/a5ds/platform.mk b/plat/arm/board/a5ds/platform.mk
index 7198842..3a4d5e5 100644
--- a/plat/arm/board/a5ds/platform.mk
+++ b/plat/arm/board/a5ds/platform.mk
@@ -41,6 +41,7 @@
plat/arm/common/arm_err.c \
plat/arm/board/a5ds/a5ds_err.c \
plat/arm/common/arm_io_storage.c \
+ plat/arm/common/fconf/arm_fconf_io.c \
plat/arm/board/a5ds/${ARCH}/a5ds_helpers.S \
plat/arm/board/a5ds/a5ds_bl1_setup.c \
lib/aarch32/arm32_aeabi_divmod.c \
@@ -61,6 +62,7 @@
plat/arm/common/arm_err.c \
plat/arm/board/a5ds/a5ds_err.c \
plat/arm/common/arm_io_storage.c \
+ plat/arm/common/fconf/arm_fconf_io.c \
plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c \
plat/arm/common/arm_image_load.c \
common/desc_image_load.c \
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index 9a4a057..704bf29 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -39,7 +39,7 @@
tos_fw-config {
load-address = <0x0 0x04001200>;
- max-size = <0x200>;
+ max-size = <0x1000>;
id = <TOS_FW_CONFIG_ID>;
};
@@ -75,6 +75,7 @@
* stored in machine order (little endian).
* This will be fixed in future.
*/
+#if ARM_IO_IN_DTB
arm-io_policies {
fip-handles {
compatible = "arm,io-fip-handle";
@@ -99,15 +100,16 @@
nt_fw_content_cert_uuid = <0xf3c1c48e 0x11e4635d 0xee87a9a7 0xa73fb240>;
};
};
+#endif /* ARM_IO_IN_DTB */
secure-partitions {
compatible = "arm,sp";
- cactus {
+ cactus-primary {
uuid = <0x1e67b5b4 0xe14f904a 0x13fb1fb8 0xcbdae1da>;
load-address = <0x7000000>;
};
- ivy {
+ cactus-secondary {
uuid = <0x092358d1 0xb94723f0 0x64447c82 0xc88f57f5>;
load-address = <0x7100000>;
};
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index db3fb55..79c4c07 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -6,7 +6,7 @@
/dts-v1/;
/ {
- compatible = "spci-core-manifest-1.0";
+ compatible = "arm,spci-core-manifest-1.0";
attribute {
spmc_id = <0x8000>;
@@ -16,4 +16,52 @@
load_address = <0x0 0x6000000>;
entrypoint = <0x0 0x6000000>;
};
+
+ chosen {
+ linux,initrd-start = <0>;
+ linux,initrd-end = <0>;
+ };
+
+ hypervisor {
+ compatible = "hafnium,hafnium";
+ vm1 {
+ is_spci_partition;
+ debug_name = "cactus-primary";
+ load-addr = <0x7000000>;
+ };
+ vm2 {
+ is_spci_partition;
+ debug_name = "cactus-secondary";
+ load-addr = <0x7100000>;
+ vcpu_count = <2>;
+ mem_size = <1048576>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <0x2>;
+ };
+ };
+ };
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <0xc>;
+ phandle = <0x2>;
+ };
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x6000000 0x2000000>; /* Trusted DRAM */
+ };
};
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 4e20632..e64c4d4 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -10,11 +10,6 @@
# Use the SP804 timer instead of the generic one
FVP_USE_SP804_TIMER := 0
-# Use fconf based io for FVP
-ifeq ($(BL2_AT_EL3), 0)
-USE_FCONF_BASED_IO := 1
-endif
-
# Default cluster count for FVP
FVP_CLUSTER_COUNT := 2
diff --git a/plat/arm/board/fvp_ve/platform.mk b/plat/arm/board/fvp_ve/platform.mk
index 7883719..9ada86b 100644
--- a/plat/arm/board/fvp_ve/platform.mk
+++ b/plat/arm/board/fvp_ve/platform.mk
@@ -42,6 +42,7 @@
plat/arm/common/arm_err.c \
plat/arm/board/fvp_ve/fvp_ve_err.c \
plat/arm/common/arm_io_storage.c \
+ plat/arm/common/fconf/arm_fconf_io.c \
drivers/cfi/v2m/v2m_flash.c \
plat/arm/board/fvp_ve/${ARCH}/fvp_ve_helpers.S \
plat/arm/board/fvp_ve/fvp_ve_bl1_setup.c \
@@ -63,6 +64,7 @@
plat/arm/common/arm_err.c \
plat/arm/board/fvp_ve/fvp_ve_err.c \
plat/arm/common/arm_io_storage.c \
+ plat/arm/common/fconf/arm_fconf_io.c \
plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c \
plat/arm/common/arm_image_load.c \
common/desc_image_load.c \
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index d9fc84e..6c3f64f 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -205,7 +205,7 @@
******************************************************************************/
int arm_bl2_plat_handle_post_image_load(unsigned int image_id)
{
-#if defined(SPD_spmd)
+#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
/* For Secure Partitions we don't need post processing */
if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) &&
(image_id < MAX_NUMBER_IDS)) {
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 65f6bf3..3b0c39d 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -177,14 +177,12 @@
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
endif
-ifeq (${USE_FCONF_BASED_IO}, 0)
-ARM_IO_SOURCES += plat/arm/common/arm_io_storage.c
-else
-ARM_IO_SOURCES += plat/arm/common/arm_fconf_io_storage.c \
+ARM_IO_SOURCES += plat/arm/common/arm_io_storage.c \
plat/arm/common/fconf/arm_fconf_io.c
ifeq (${SPD},spmd)
-ARM_IO_SOURCES += plat/arm/common/fconf/arm_fconf_sp.c
-endif
+ ifeq (${SPMD_SPM_AT_SEL2},1)
+ ARM_IO_SOURCES += plat/arm/common/fconf/arm_fconf_sp.c
+ endif
endif
BL1_SOURCES += drivers/io/io_fip.c \
diff --git a/plat/arm/common/arm_fconf_io_storage.c b/plat/arm/common/arm_fconf_io_storage.c
deleted file mode 100644
index 6fcfbd6..0000000
--- a/plat/arm/common/arm_fconf_io_storage.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2015-2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <common/debug.h>
-#include <drivers/io/io_driver.h>
-#include <drivers/io/io_fip.h>
-#include <drivers/io/io_memmap.h>
-#include <drivers/io/io_storage.h>
-#include <lib/utils.h>
-
-#include <plat/arm/common/arm_fconf_getter.h>
-#include <plat/arm/common/arm_fconf_io_storage.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-#include <platform_def.h>
-
-/* IO devices */
-static const io_dev_connector_t *fip_dev_con;
-uintptr_t fip_dev_handle;
-static const io_dev_connector_t *memmap_dev_con;
-uintptr_t memmap_dev_handle;
-
-/* Weak definitions may be overridden in specific ARM standard platform */
-#pragma weak plat_arm_io_setup
-#pragma weak plat_arm_get_alt_image_source
-
-int open_fip(const uintptr_t spec)
-{
- int result;
- uintptr_t local_image_handle;
-
- /* See if a Firmware Image Package is available */
- result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
- if (result == 0) {
- result = io_open(fip_dev_handle, spec, &local_image_handle);
- if (result == 0) {
- VERBOSE("Using FIP\n");
- io_close(local_image_handle);
- }
- }
- return result;
-}
-
-int open_memmap(const uintptr_t spec)
-{
- int result;
- uintptr_t local_image_handle;
-
- result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
- if (result == 0) {
- result = io_open(memmap_dev_handle, spec, &local_image_handle);
- if (result == 0) {
- VERBOSE("Using Memmap\n");
- io_close(local_image_handle);
- }
- }
- return result;
-}
-
-int arm_io_setup(void)
-{
- int io_result;
-
- io_result = register_io_dev_fip(&fip_dev_con);
- if (io_result < 0) {
- return io_result;
- }
-
- io_result = register_io_dev_memmap(&memmap_dev_con);
- if (io_result < 0) {
- return io_result;
- }
-
- /* Open connections to devices and cache the handles */
- io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
- &fip_dev_handle);
- if (io_result < 0) {
- return io_result;
- }
-
- io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
- &memmap_dev_handle);
-
- return io_result;
-}
-
-void plat_arm_io_setup(void)
-{
- int err;
-
- err = arm_io_setup();
- if (err < 0) {
- panic();
- }
-}
-
-int plat_arm_get_alt_image_source(
- unsigned int image_id __unused,
- uintptr_t *dev_handle __unused,
- uintptr_t *image_spec __unused)
-{
- /* By default do not try an alternative */
- return -ENOENT;
-}
-
-/* Return an IO device handle and specification which can be used to access
- * an image. Use this to enforce platform load policy */
-int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
- uintptr_t *image_spec)
-{
- int result;
- const struct plat_io_policy *policy;
-
- assert(image_id < MAX_NUMBER_IDS);
-
- policy = FCONF_GET_PROPERTY(arm, io_policies, image_id);
- result = policy->check(policy->image_spec);
- if (result == 0) {
- *image_spec = policy->image_spec;
- *dev_handle = *(policy->dev_handle);
- } else {
- VERBOSE("Trying alternative IO\n");
- result = plat_arm_get_alt_image_source(image_id, dev_handle,
- image_spec);
- }
-
- return result;
-}
-
-/*
- * See if a Firmware Image Package is available,
- * by checking if TOC is valid or not.
- */
-bool arm_io_is_toc_valid(void)
-{
- return (io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID) == 0);
-}
diff --git a/plat/arm/common/arm_image_load.c b/plat/arm/common/arm_image_load.c
index 593199d..ed7f1f5 100644
--- a/plat/arm/common/arm_image_load.c
+++ b/plat/arm/common/arm_image_load.c
@@ -32,11 +32,11 @@
next_bl_params_cpy_ptr);
}
-#if defined(SPD_spmd)
+#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
/*******************************************************************************
* This function appends Secure Partitions to list of loadable images.
******************************************************************************/
-void plat_add_sp_images_load_info(struct bl_load_info *load_info)
+static void plat_add_sp_images_load_info(struct bl_load_info *load_info)
{
bl_load_info_node_t *node_info = load_info->head;
unsigned int index = 0;
@@ -78,7 +78,7 @@
******************************************************************************/
struct bl_load_info *plat_get_bl_image_load_info(void)
{
-#if defined(SPD_spmd)
+#if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
bl_load_info_t *bl_load_info;
bl_load_info = get_bl_load_info_from_mem_params_desc();
diff --git a/plat/arm/common/arm_io_storage.c b/plat/arm/common/arm_io_storage.c
index f5d8a41..6fcfbd6 100644
--- a/plat/arm/common/arm_io_storage.c
+++ b/plat/arm/common/arm_io_storage.c
@@ -1,13 +1,10 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
-#include <string.h>
-
-#include <platform_def.h>
#include <common/debug.h>
#include <drivers/io/io_driver.h>
@@ -15,249 +12,24 @@
#include <drivers/io/io_memmap.h>
#include <drivers/io/io_storage.h>
#include <lib/utils.h>
+
+#include <plat/arm/common/arm_fconf_getter.h>
+#include <plat/arm/common/arm_fconf_io_storage.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
-#include <tools_share/firmware_image_package.h>
+#include <platform_def.h>
/* IO devices */
static const io_dev_connector_t *fip_dev_con;
-static uintptr_t fip_dev_handle;
+uintptr_t fip_dev_handle;
static const io_dev_connector_t *memmap_dev_con;
-static uintptr_t memmap_dev_handle;
-
-static const io_block_spec_t fip_block_spec = {
- .offset = PLAT_ARM_FIP_BASE,
- .length = PLAT_ARM_FIP_MAX_SIZE
-};
-
-static const io_uuid_spec_t bl2_uuid_spec = {
- .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
-};
-
-static const io_uuid_spec_t scp_bl2_uuid_spec = {
- .uuid = UUID_SCP_FIRMWARE_SCP_BL2,
-};
-
-static const io_uuid_spec_t bl31_uuid_spec = {
- .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
-};
-
-static const io_uuid_spec_t bl32_uuid_spec = {
- .uuid = UUID_SECURE_PAYLOAD_BL32,
-};
-
-static const io_uuid_spec_t bl32_extra1_uuid_spec = {
- .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
-};
-
-static const io_uuid_spec_t bl32_extra2_uuid_spec = {
- .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
-};
-
-static const io_uuid_spec_t bl33_uuid_spec = {
- .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
-};
-
-static const io_uuid_spec_t tb_fw_config_uuid_spec = {
- .uuid = UUID_TB_FW_CONFIG,
-};
-
-static const io_uuid_spec_t hw_config_uuid_spec = {
- .uuid = UUID_HW_CONFIG,
-};
-
-static const io_uuid_spec_t soc_fw_config_uuid_spec = {
- .uuid = UUID_SOC_FW_CONFIG,
-};
-
-static const io_uuid_spec_t tos_fw_config_uuid_spec = {
- .uuid = UUID_TOS_FW_CONFIG,
-};
-
-static const io_uuid_spec_t nt_fw_config_uuid_spec = {
- .uuid = UUID_NT_FW_CONFIG,
-};
-
-#if TRUSTED_BOARD_BOOT
-static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
- .uuid = UUID_TRUSTED_BOOT_FW_CERT,
-};
-
-static const io_uuid_spec_t trusted_key_cert_uuid_spec = {
- .uuid = UUID_TRUSTED_KEY_CERT,
-};
-
-static const io_uuid_spec_t scp_fw_key_cert_uuid_spec = {
- .uuid = UUID_SCP_FW_KEY_CERT,
-};
-
-static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = {
- .uuid = UUID_SOC_FW_KEY_CERT,
-};
-
-static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = {
- .uuid = UUID_TRUSTED_OS_FW_KEY_CERT,
-};
-
-static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = {
- .uuid = UUID_NON_TRUSTED_FW_KEY_CERT,
-};
-
-static const io_uuid_spec_t scp_fw_cert_uuid_spec = {
- .uuid = UUID_SCP_FW_CONTENT_CERT,
-};
-
-static const io_uuid_spec_t soc_fw_cert_uuid_spec = {
- .uuid = UUID_SOC_FW_CONTENT_CERT,
-};
-
-static const io_uuid_spec_t tos_fw_cert_uuid_spec = {
- .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT,
-};
-
-static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
- .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT,
-};
-#endif /* TRUSTED_BOARD_BOOT */
-
-
-static int open_fip(const uintptr_t spec);
-static int open_memmap(const uintptr_t spec);
-
-struct plat_io_policy {
- uintptr_t *dev_handle;
- uintptr_t image_spec;
- int (*check)(const uintptr_t spec);
-};
-
-/* By default, ARM platforms load images from the FIP */
-static const struct plat_io_policy policies[] = {
- [FIP_IMAGE_ID] = {
- &memmap_dev_handle,
- (uintptr_t)&fip_block_spec,
- open_memmap
- },
- [BL2_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl2_uuid_spec,
- open_fip
- },
- [SCP_BL2_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&scp_bl2_uuid_spec,
- open_fip
- },
- [BL31_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl31_uuid_spec,
- open_fip
- },
- [BL32_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl32_uuid_spec,
- open_fip
- },
- [BL32_EXTRA1_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl32_extra1_uuid_spec,
- open_fip
- },
- [BL32_EXTRA2_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl32_extra2_uuid_spec,
- open_fip
- },
- [BL33_IMAGE_ID] = {
- &fip_dev_handle,
- (uintptr_t)&bl33_uuid_spec,
- open_fip
- },
- [TB_FW_CONFIG_ID] = {
- &fip_dev_handle,
- (uintptr_t)&tb_fw_config_uuid_spec,
- open_fip
- },
- [HW_CONFIG_ID] = {
- &fip_dev_handle,
- (uintptr_t)&hw_config_uuid_spec,
- open_fip
- },
- [SOC_FW_CONFIG_ID] = {
- &fip_dev_handle,
- (uintptr_t)&soc_fw_config_uuid_spec,
- open_fip
- },
- [TOS_FW_CONFIG_ID] = {
- &fip_dev_handle,
- (uintptr_t)&tos_fw_config_uuid_spec,
- open_fip
- },
- [NT_FW_CONFIG_ID] = {
- &fip_dev_handle,
- (uintptr_t)&nt_fw_config_uuid_spec,
- open_fip
- },
-#if TRUSTED_BOARD_BOOT
- [TRUSTED_BOOT_FW_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&tb_fw_cert_uuid_spec,
- open_fip
- },
- [TRUSTED_KEY_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&trusted_key_cert_uuid_spec,
- open_fip
- },
- [SCP_FW_KEY_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&scp_fw_key_cert_uuid_spec,
- open_fip
- },
- [SOC_FW_KEY_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&soc_fw_key_cert_uuid_spec,
- open_fip
- },
- [TRUSTED_OS_FW_KEY_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&tos_fw_key_cert_uuid_spec,
- open_fip
- },
- [NON_TRUSTED_FW_KEY_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&nt_fw_key_cert_uuid_spec,
- open_fip
- },
- [SCP_FW_CONTENT_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&scp_fw_cert_uuid_spec,
- open_fip
- },
- [SOC_FW_CONTENT_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&soc_fw_cert_uuid_spec,
- open_fip
- },
- [TRUSTED_OS_FW_CONTENT_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&tos_fw_cert_uuid_spec,
- open_fip
- },
- [NON_TRUSTED_FW_CONTENT_CERT_ID] = {
- &fip_dev_handle,
- (uintptr_t)&nt_fw_cert_uuid_spec,
- open_fip
- },
-#endif /* TRUSTED_BOARD_BOOT */
-};
-
+uintptr_t memmap_dev_handle;
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak plat_arm_io_setup
#pragma weak plat_arm_get_alt_image_source
-
-static int open_fip(const uintptr_t spec)
+int open_fip(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
@@ -274,8 +46,7 @@
return result;
}
-
-static int open_memmap(const uintptr_t spec)
+int open_memmap(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
@@ -291,7 +62,6 @@
return result;
}
-
int arm_io_setup(void)
{
int io_result;
@@ -346,9 +116,9 @@
int result;
const struct plat_io_policy *policy;
- assert(image_id < ARRAY_SIZE(policies));
+ assert(image_id < MAX_NUMBER_IDS);
- policy = &policies[image_id];
+ policy = FCONF_GET_PROPERTY(arm, io_policies, image_id);
result = policy->check(policy->image_spec);
if (result == 0) {
*image_spec = policy->image_spec;
@@ -370,4 +140,3 @@
{
return (io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID) == 0);
}
-
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c
index 017af79..6ebc467 100644
--- a/plat/arm/common/fconf/arm_fconf_io.c
+++ b/plat/arm/common/fconf/arm_fconf_io.c
@@ -25,8 +25,31 @@
const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = {
[BL2_IMAGE_ID] = {UUID_TRUSTED_BOOT_FIRMWARE_BL2},
[TB_FW_CONFIG_ID] = {UUID_TB_FW_CONFIG},
+#if !ARM_IO_IN_DTB
+ [SCP_BL2_IMAGE_ID] = {UUID_SCP_FIRMWARE_SCP_BL2},
+ [BL31_IMAGE_ID] = {UUID_EL3_RUNTIME_FIRMWARE_BL31},
+ [BL32_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32},
+ [BL32_EXTRA1_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32_EXTRA1},
+ [BL32_EXTRA2_IMAGE_ID] = {UUID_SECURE_PAYLOAD_BL32_EXTRA2},
+ [BL33_IMAGE_ID] = {UUID_NON_TRUSTED_FIRMWARE_BL33},
+ [HW_CONFIG_ID] = {UUID_HW_CONFIG},
+ [SOC_FW_CONFIG_ID] = {UUID_SOC_FW_CONFIG},
+ [TOS_FW_CONFIG_ID] = {UUID_TOS_FW_CONFIG},
+ [NT_FW_CONFIG_ID] = {UUID_NT_FW_CONFIG},
+#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {UUID_TRUSTED_BOOT_FW_CERT},
+#if !ARM_IO_IN_DTB
+ [TRUSTED_KEY_CERT_ID] = {UUID_TRUSTED_KEY_CERT},
+ [SCP_FW_KEY_CERT_ID] = {UUID_SCP_FW_KEY_CERT},
+ [SOC_FW_KEY_CERT_ID] = {UUID_SOC_FW_KEY_CERT},
+ [TRUSTED_OS_FW_KEY_CERT_ID] = {UUID_TRUSTED_OS_FW_KEY_CERT},
+ [NON_TRUSTED_FW_KEY_CERT_ID] = {UUID_NON_TRUSTED_FW_KEY_CERT},
+ [SCP_FW_CONTENT_CERT_ID] = {UUID_SCP_FW_CONTENT_CERT},
+ [SOC_FW_CONTENT_CERT_ID] = {UUID_SOC_FW_CONTENT_CERT},
+ [TRUSTED_OS_FW_CONTENT_CERT_ID] = {UUID_TRUSTED_OS_FW_CONTENT_CERT},
+ [NON_TRUSTED_FW_CONTENT_CERT_ID] = {UUID_NON_TRUSTED_FW_CONTENT_CERT},
+#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@@ -47,12 +70,111 @@
(uintptr_t)&arm_uuid_spec[TB_FW_CONFIG_ID],
open_fip
},
+#if !ARM_IO_IN_DTB
+ [SCP_BL2_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SCP_BL2_IMAGE_ID],
+ open_fip
+ },
+ [BL31_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[BL31_IMAGE_ID],
+ open_fip
+ },
+ [BL32_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[BL32_IMAGE_ID],
+ open_fip
+ },
+ [BL32_EXTRA1_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[BL32_EXTRA1_IMAGE_ID],
+ open_fip
+ },
+ [BL32_EXTRA2_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[BL32_EXTRA2_IMAGE_ID],
+ open_fip
+ },
+ [BL33_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[BL33_IMAGE_ID],
+ open_fip
+ },
+ [HW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[HW_CONFIG_ID],
+ open_fip
+ },
+ [SOC_FW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SOC_FW_CONFIG_ID],
+ open_fip
+ },
+ [TOS_FW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[TOS_FW_CONFIG_ID],
+ open_fip
+ },
+ [NT_FW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[NT_FW_CONFIG_ID],
+ open_fip
+ },
+#endif /* ARM_IO_IN_DTB */
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
&fip_dev_handle,
(uintptr_t)&arm_uuid_spec[TRUSTED_BOOT_FW_CERT_ID],
open_fip
},
+#if !ARM_IO_IN_DTB
+ [TRUSTED_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[TRUSTED_KEY_CERT_ID],
+ open_fip
+ },
+ [SCP_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SCP_FW_KEY_CERT_ID],
+ open_fip
+ },
+ [SOC_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SOC_FW_KEY_CERT_ID],
+ open_fip
+ },
+ [TRUSTED_OS_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[TRUSTED_OS_FW_KEY_CERT_ID],
+ open_fip
+ },
+ [NON_TRUSTED_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[NON_TRUSTED_FW_KEY_CERT_ID],
+ open_fip
+ },
+ [SCP_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SCP_FW_CONTENT_CERT_ID],
+ open_fip
+ },
+ [SOC_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[SOC_FW_CONTENT_CERT_ID],
+ open_fip
+ },
+ [TRUSTED_OS_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[TRUSTED_OS_FW_CONTENT_CERT_ID],
+ open_fip
+ },
+ [NON_TRUSTED_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&arm_uuid_spec[NON_TRUSTED_FW_CONTENT_CERT_ID],
+ open_fip
+ },
+#endif /* ARM_IO_IN_DTB */
#endif /* TRUSTED_BOARD_BOOT */
};
@@ -138,6 +260,8 @@
return 0;
}
+#if ARM_IO_IN_DTB
FCONF_REGISTER_POPULATOR(TB_FW, arm_io, fconf_populate_arm_io_policies);
+#endif /* ARM_IO_IN_DTB */
#endif /* IMAGE_BL2 */
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index 9a482d0..8c8b231 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -56,7 +56,7 @@
* PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
* plus a little space for growth.
*/
-#define PLAT_ARM_MAX_BL1_RW_SIZE 0xB000
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000
/*
* PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
@@ -141,7 +141,7 @@
CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + \
ARM_SHARED_RAM_BASE, \
ARM_SHARED_RAM_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE \
+ MT_NON_CACHEABLE | MT_RW | MT_SECURE \
)
#define CSS_SGI_MAP_DEVICE_REMOTE_CHIP(n) \
diff --git a/plat/imx/common/include/imx8_iomux.h b/plat/imx/common/include/imx8_iomux.h
index 0e93d98..264c295 100644
--- a/plat/imx/common/include/imx8_iomux.h
+++ b/plat/imx/common/include/imx8_iomux.h
@@ -7,19 +7,19 @@
#ifndef IMX8_IOMUX_H
#define IMX8_IOMUX_H
-#define PADRING_IFMUX_EN_SHIFT 31
-#define PADRING_IFMUX_EN_MASK (1 << PADRING_IFMUX_EN_SHIFT)
-#define PADRING_GP_EN_SHIFT 30
-#define PADRING_GP_EN_MASK (1 << PADRING_GP_EN_SHIFT)
-#define PADRING_IFMUX_SHIFT 27
-#define PADRING_IFMUX_MASK (0x7 << PADRING_IFMUX_SHIFT)
-#define PADRING_CONFIG_SHIFT 25
-#define PADRING_CONFIG_MASK (0x3 << PADRING_CONFIG_SHIFT)
-#define PADRING_LPCONFIG_SHIFT 23
-#define PADRING_LPCONFIG_MASK (0x3 << PADRING_LPCONFIG_SHIFT)
-#define PADRING_PULL_SHIFT 5
-#define PADRING_PULL_MASK (0x3 << PADRING_PULL_SHIFT)
-#define PADRING_DSE_SHIFT 0
-#define PADRING_DSE_MASK (0x7 << PADRING_DSE_SHIFT)
+#define PADRING_IFMUX_EN_SHIFT U(31)
+#define PADRING_IFMUX_EN_MASK (U(0x1) << PADRING_IFMUX_EN_SHIFT)
+#define PADRING_GP_EN_SHIFT U(30)
+#define PADRING_GP_EN_MASK (U(0x1) << PADRING_GP_EN_SHIFT)
+#define PADRING_IFMUX_SHIFT U(27)
+#define PADRING_IFMUX_MASK (U(0x7) << PADRING_IFMUX_SHIFT)
+#define PADRING_CONFIG_SHIFT U(25)
+#define PADRING_CONFIG_MASK (U(0x3) << PADRING_CONFIG_SHIFT)
+#define PADRING_LPCONFIG_SHIFT U(23)
+#define PADRING_LPCONFIG_MASK (U(0x3) << PADRING_LPCONFIG_SHIFT)
+#define PADRING_PULL_SHIFT U(5)
+#define PADRING_PULL_MASK (U(0x3) << PADRING_PULL_SHIFT)
+#define PADRING_DSE_SHIFT U(0)
+#define PADRING_DSE_MASK (U(0x7) << PADRING_DSE_SHIFT)
#endif /* IMX8_IOMUX_H */
diff --git a/plat/imx/imx8qm/imx8qm_bl31_setup.c b/plat/imx/imx8qm/imx8qm_bl31_setup.c
index cffb140..4ca6a5d 100644
--- a/plat/imx/imx8qm/imx8qm_bl31_setup.c
+++ b/plat/imx/imx8qm/imx8qm_bl31_setup.c
@@ -44,6 +44,22 @@
(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT))
+#if defined(IMX_USE_UART0)
+#define IMX_RES_UART SC_R_UART_0
+#define IMX_PAD_UART_RX SC_P_UART0_RX
+#define IMX_PAD_UART_TX SC_P_UART0_TX
+#define IMX_PAD_UART_RTS_B SC_P_UART0_RTS_B
+#define IMX_PAD_UART_CTS_B SC_P_UART0_CTS_B
+#elif defined(IMX_USE_UART1)
+#define IMX_RES_UART SC_R_UART_1
+#define IMX_PAD_UART_RX SC_P_UART1_RX
+#define IMX_PAD_UART_TX SC_P_UART1_TX
+#define IMX_PAD_UART_RTS_B SC_P_UART1_RTS_B
+#define IMX_PAD_UART_CTS_B SC_P_UART1_CTS_B
+#else
+#error "Provide proper UART number in IMX_DEBUG_UART"
+#endif
+
const static int imx8qm_cci_map[] = {
CLUSTER0_CCI_SLVAE_IFACE,
CLUSTER1_CCI_SLVAE_IFACE
@@ -79,7 +95,7 @@
if (baudrate == 0)
panic();
- sc_pm_get_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate);
+ sc_pm_get_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate);
baud_diff = baudrate;
osr = 0;
@@ -301,16 +317,17 @@
panic();
#if DEBUG_CONSOLE_A53
- sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON);
+ sc_pm_set_resource_power_mode(ipc_handle, IMX_RES_UART,
+ SC_PM_PW_MODE_ON);
sc_pm_clock_rate_t rate = 80000000;
- sc_pm_set_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate);
- sc_pm_clock_enable(ipc_handle, SC_R_UART_0, 2, true, false);
+ sc_pm_set_clock_rate(ipc_handle, IMX_RES_UART, 2, &rate);
+ sc_pm_clock_enable(ipc_handle, IMX_RES_UART, 2, true, false);
/* configure UART pads */
- sc_pad_set(ipc_handle, SC_P_UART0_RX, UART_PAD_CTRL);
- sc_pad_set(ipc_handle, SC_P_UART0_TX, UART_PAD_CTRL);
- sc_pad_set(ipc_handle, SC_P_UART0_RTS_B, UART_PAD_CTRL);
- sc_pad_set(ipc_handle, SC_P_UART0_CTS_B, UART_PAD_CTRL);
+ sc_pad_set(ipc_handle, IMX_PAD_UART_RX, UART_PAD_CTRL);
+ sc_pad_set(ipc_handle, IMX_PAD_UART_TX, UART_PAD_CTRL);
+ sc_pad_set(ipc_handle, IMX_PAD_UART_RTS_B, UART_PAD_CTRL);
+ sc_pad_set(ipc_handle, IMX_PAD_UART_CTS_B, UART_PAD_CTRL);
lpuart32_serial_init(IMX_BOOT_UART_BASE);
#endif
diff --git a/plat/imx/imx8qm/include/platform_def.h b/plat/imx/imx8qm/include/platform_def.h
index b54943d..671c77f 100644
--- a/plat/imx/imx8qm/include/platform_def.h
+++ b/plat/imx/imx8qm/include/platform_def.h
@@ -40,12 +40,22 @@
#define PLAT_CCI_BASE 0x52090000
#define CLUSTER0_CCI_SLVAE_IFACE 3
#define CLUSTER1_CCI_SLVAE_IFACE 4
+
+/* UART */
+#if defined(IMX_USE_UART0)
#define IMX_BOOT_UART_BASE 0x5a060000
+#elif defined(IMX_USE_UART1)
+#define IMX_BOOT_UART_BASE 0x5a070000
+#else
+#error "Provide proper UART number in IMX_DEBUG_UART"
+#endif
+
#define IMX_BOOT_UART_BAUDRATE 115200
#define IMX_BOOT_UART_CLK_IN_HZ 24000000
#define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE
#define PLAT__CRASH_UART_CLK_IN_HZ 24000000
#define IMX_CONSOLE_BAUDRATE 115200
+
#define SC_IPC_BASE 0x5d1b0000
#define IMX_GPT_LPCG_BASE 0x5d540000
#define IMX_GPT_BASE 0x5d140000
@@ -64,7 +74,6 @@
#define MAX_XLAT_TABLES 8
#define MAX_MMAP_REGIONS 12
-#define DEBUG_CONSOLE 0
-#define DEBUG_CONSOLE_A53 0
+#define DEBUG_CONSOLE_A53 DEBUG_CONSOLE
#endif /* PLATFORM_DEF_H */
diff --git a/plat/imx/imx8qm/platform.mk b/plat/imx/imx8qm/platform.mk
index 5ba9c3f..20ee05b 100644
--- a/plat/imx/imx8qm/platform.mk
+++ b/plat/imx/imx8qm/platform.mk
@@ -43,3 +43,9 @@
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
+
+IMX_DEBUG_UART ?= 0
+$(eval $(call add_define,IMX_USE_UART${IMX_DEBUG_UART}))
+
+DEBUG_CONSOLE ?= 0
+$(eval $(call add_define,DEBUG_CONSOLE))
diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
index 7cba3a4..5f01416 100644
--- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
+++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S
@@ -39,6 +39,7 @@
.globl plat_crash_console_init
.globl plat_crash_console_putc
.globl plat_crash_console_flush
+ .weak plat_core_pos_by_mpidr
.globl tegra_secure_entrypoint
.globl plat_reset_handler
@@ -140,17 +141,14 @@
* unsigned int plat_my_core_pos(void);
*
* result: CorePos = CoreId + (ClusterId * cpus per cluster)
+ * Registers clobbered: x0, x8
* ----------------------------------------------------------
*/
func plat_my_core_pos
+ mov x8, x30
mrs x0, mpidr_el1
- and x1, x0, #MPIDR_CPU_MASK
- and x0, x0, #MPIDR_CLUSTER_MASK
- lsr x0, x0, #MPIDR_AFFINITY_BITS
- mov x2, #PLATFORM_MAX_CPUS_PER_CLUSTER
- mul x0, x0, x2
- add x0, x1, x0
- ret
+ bl plat_core_pos_by_mpidr
+ ret x8
endfunc plat_my_core_pos
/* -----------------------------------------------------
@@ -273,6 +271,42 @@
ret
endfunc plat_reset_handler
+ /* ------------------------------------------------------
+ * int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
+ *
+ * This function implements a part of the critical
+ * interface between the psci generic layer and the
+ * platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error
+ * code (-1) is returned in case the MPIDR is invalid.
+ *
+ * Clobbers: x0-x3
+ * ------------------------------------------------------
+ */
+func plat_core_pos_by_mpidr
+ lsr x1, x0, #MPIDR_AFF0_SHIFT
+ and x1, x1, #MPIDR_AFFLVL_MASK /* core id */
+ lsr x2, x0, #MPIDR_AFF1_SHIFT
+ and x2, x2, #MPIDR_AFFLVL_MASK /* cluster id */
+
+ /* core_id >= PLATFORM_MAX_CPUS_PER_CLUSTER */
+ mov x0, #-1
+ cmp x1, #(PLATFORM_MAX_CPUS_PER_CLUSTER - 1)
+ b.gt 1f
+
+ /* cluster_id >= PLATFORM_CLUSTER_COUNT */
+ cmp x2, #(PLATFORM_CLUSTER_COUNT - 1)
+ b.gt 1f
+
+ /* CorePos = CoreId + (ClusterId * cpus per cluster) */
+ mov x3, #PLATFORM_MAX_CPUS_PER_CLUSTER
+ mul x3, x3, x2
+ add x0, x1, x3
+
+1:
+ ret
+endfunc plat_core_pos_by_mpidr
+
/* ----------------------------------------
* Secure entrypoint function for CPU boot
* ----------------------------------------
diff --git a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c
index 57daf6a..d964fc0 100644
--- a/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c
+++ b/plat/nvidia/tegra/common/drivers/bpmp_ipc/ivc.c
@@ -8,6 +8,7 @@
#include <assert.h>
#include <common/debug.h>
#include <errno.h>
+#include <stdbool.h>
#include <stddef.h>
#include <string.h>
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
index 92fa273..c3f95db 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -117,7 +117,8 @@
ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
non_overlap_area_start, /* VA */
non_overlap_area_size, /* size */
- MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
+ MT_NS | MT_RW | MT_EXECUTE_NEVER |
+ MT_NON_CACHEABLE); /* attrs */
assert(ret == 0);
zeromem((void *)non_overlap_area_start, non_overlap_area_size);
diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index a53f660..5555f5d 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -159,69 +159,7 @@
*/
void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
{
- uint32_t index;
- uint32_t total_128kb_blocks = size_in_bytes >> 17;
- uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12;
- uint32_t val;
-
- INFO("Configuring TrustZone SRAM Memory Carveout\n");
-
- /*
- * Reset the access configuration registers to restrict access
- * to the TZRAM aperture
- */
- for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0;
- index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE);
- index += 4U) {
- tegra_mc_write_32(index, 0);
- }
-
- /*
- * Enable CPU access configuration registers to access the TZRAM aperture
- */
- if (!tegra_chipid_is_t186()) {
- val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0);
- val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW;
- tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val);
- }
-
- /*
- * Set the TZRAM base. TZRAM base must be 4k aligned, at least.
- */
- assert((phys_base & (uint64_t)0xFFF) == 0U);
- tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base);
- tegra_mc_write_32(MC_TZRAM_BASE_HI,
- (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK);
-
- /*
- * Set the TZRAM size
- *
- * total size = (number of 128KB blocks) + (number of remaining 4KB
- * blocks)
- *
- */
- val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) |
- total_128kb_blocks;
- tegra_mc_write_32(MC_TZRAM_SIZE, val);
-
- /*
- * Lock the configuration settings by disabling TZ-only lock
- * and locking the configuration against any future changes
- * at all.
- */
- val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG);
- val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT;
- val |= MC_GSC_LOCK_CFG_SETTINGS_BIT;
- if (!tegra_chipid_is_t186()) {
- val |= MC_GSC_ENABLE_CPU_SECURE_BIT;
- }
- tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val);
-
- /*
- * MCE propagates the security configuration values across the
- * CCPLEX.
- */
- mce_update_gsc_tzram();
+ ; /* do nothing */
}
/*
@@ -348,7 +286,8 @@
ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */
non_overlap_area_start, /* VA */
non_overlap_area_size, /* size */
- MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
+ MT_NS | MT_RW | MT_EXECUTE_NEVER |
+ MT_NON_CACHEABLE); /* attrs */
assert(ret == 0);
zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size);
diff --git a/plat/nvidia/tegra/common/tegra_bl31_setup.c b/plat/nvidia/tegra/common/tegra_bl31_setup.c
index 46686c3..269afb1 100644
--- a/plat/nvidia/tegra/common/tegra_bl31_setup.c
+++ b/plat/nvidia/tegra/common/tegra_bl31_setup.c
@@ -39,15 +39,8 @@
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
-
IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
-static const uint64_t BL31_RW_END = BL_END;
-static const uint64_t BL31_RODATA_BASE = BL_RO_DATA_BASE;
-static const uint64_t BL31_RODATA_END = BL_RO_DATA_END;
-static const uint64_t TEXT_START = BL_CODE_BASE;
-static const uint64_t TEXT_END = BL_CODE_END;
-
extern uint64_t tegra_bl31_phys_base;
static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
@@ -314,15 +307,12 @@
void bl31_plat_arch_setup(void)
{
uint64_t rw_start = BL31_RW_START;
- uint64_t rw_size = BL31_RW_END - BL31_RW_START;
- uint64_t rodata_start = BL31_RODATA_BASE;
- uint64_t rodata_size = BL31_RODATA_END - BL31_RODATA_BASE;
- uint64_t code_base = TEXT_START;
- uint64_t code_size = TEXT_END - TEXT_START;
+ uint64_t rw_size = BL_END - BL31_RW_START;
+ uint64_t rodata_start = BL_RO_DATA_BASE;
+ uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE;
+ uint64_t code_base = BL_CODE_BASE;
+ uint64_t code_size = BL_CODE_END - BL_CODE_BASE;
const mmap_region_t *plat_mmio_map = NULL;
-#if USE_COHERENT_MEM
- uint32_t coh_start, coh_size;
-#endif
const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
/*
@@ -349,15 +339,6 @@
code_size,
MT_CODE | MT_SECURE);
-#if USE_COHERENT_MEM
- coh_start = total_base + (BL_COHERENT_RAM_BASE - BL31_RO_BASE);
- coh_size = BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE;
-
- mmap_add_region(coh_start, coh_start,
- coh_size,
- (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE);
-#endif
-
/* map TZDRAM used by BL31 as coherent memory */
if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
mmap_add_region(params_from_bl2->tzdram_base,
diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk
index 50c9592..c946a75 100644
--- a/plat/nvidia/tegra/common/tegra_common.mk
+++ b/plat/nvidia/tegra/common/tegra_common.mk
@@ -6,8 +6,7 @@
PLAT_INCLUDES := -Iplat/nvidia/tegra/include/drivers \
-Iplat/nvidia/tegra/include/lib \
- -Iplat/nvidia/tegra/include \
- -Iplat/nvidia/tegra/include/${TARGET_SOC}
+ -Iplat/nvidia/tegra/include
include lib/xlat_tables_v2/xlat_tables.mk
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
@@ -32,5 +31,4 @@
${COMMON_DIR}/tegra_io_storage.c \
${COMMON_DIR}/tegra_platform.c \
${COMMON_DIR}/tegra_pm.c \
- ${COMMON_DIR}/tegra_sip_calls.c \
- ${COMMON_DIR}/tegra_topology.c
+ ${COMMON_DIR}/tegra_sip_calls.c
diff --git a/plat/nvidia/tegra/common/tegra_gicv2.c b/plat/nvidia/tegra/common/tegra_gicv2.c
index 293df8d..012107e 100644
--- a/plat/nvidia/tegra/common/tegra_gicv2.c
+++ b/plat/nvidia/tegra/common/tegra_gicv2.c
@@ -1,20 +1,23 @@
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
-
#include <platform_def.h>
#include <common/bl_common.h>
#include <drivers/arm/gicv2.h>
#include <lib/utils.h>
+#include <plat/common/platform.h>
#include <tegra_private.h>
#include <tegra_def.h>
+static unsigned int tegra_target_masks[PLATFORM_CORE_COUNT];
+
/******************************************************************************
* Tegra common helper to setup the GICv2 driver data.
*****************************************************************************/
@@ -33,6 +36,8 @@
tegra_gic_data.gicc_base = TEGRA_GICC_BASE;
tegra_gic_data.interrupt_props = interrupt_props;
tegra_gic_data.interrupt_props_num = interrupt_props_num;
+ tegra_gic_data.target_masks = tegra_target_masks;
+ tegra_gic_data.target_masks_num = ARRAY_SIZE(tegra_target_masks);
gicv2_driver_init(&tegra_gic_data);
}
@@ -43,6 +48,7 @@
{
gicv2_distif_init();
gicv2_pcpu_distif_init();
+ gicv2_set_pe_target_mask(plat_my_core_pos());
gicv2_cpuif_enable();
}
@@ -61,5 +67,6 @@
void tegra_gic_pcpu_init(void)
{
gicv2_pcpu_distif_init();
+ gicv2_set_pe_target_mask(plat_my_core_pos());
gicv2_cpuif_enable();
}
diff --git a/plat/nvidia/tegra/common/tegra_topology.c b/plat/nvidia/tegra/common/tegra_topology.c
deleted file mode 100644
index 205b051..0000000
--- a/plat/nvidia/tegra/common/tegra_topology.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <arch.h>
-#include <lib/psci/psci.h>
-#include <plat/common/platform.h>
-
-#pragma weak plat_core_pos_by_mpidr
-
-/*******************************************************************************
- * This function implements a part of the critical interface between the psci
- * generic layer and the platform that allows the former to query the platform
- * to convert an MPIDR to a unique linear index. An error code (-1) is returned
- * in case the MPIDR is invalid.
- ******************************************************************************/
-int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
-{
- u_register_t cluster_id, cpu_id;
- int32_t result;
-
- cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) &
- (u_register_t)MPIDR_AFFLVL_MASK;
- cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) &
- (u_register_t)MPIDR_AFFLVL_MASK;
-
- /* CorePos = CoreId + (ClusterId * cpus per cluster) */
- result = (int32_t)cpu_id + ((int32_t)cluster_id *
- PLATFORM_MAX_CPUS_PER_CLUSTER);
-
- if (cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) {
- result = PSCI_E_NOT_PRESENT;
- }
-
- /*
- * Validate cpu_id by checking whether it represents a CPU in
- * one of the two clusters present on the platform.
- */
- if (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER) {
- result = PSCI_E_NOT_PRESENT;
- }
-
- return result;
-}
diff --git a/plat/nvidia/tegra/include/drivers/flowctrl.h b/plat/nvidia/tegra/include/drivers/flowctrl.h
index 54336b0..e5ab600 100644
--- a/plat/nvidia/tegra/include/drivers/flowctrl.h
+++ b/plat/nvidia/tegra/include/drivers/flowctrl.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +10,8 @@
#include <lib/mmio.h>
+#include <stdbool.h>
+
#include <tegra_def.h>
#define FLOWCTRL_HALT_CPU0_EVENTS (0x0U)
diff --git a/plat/nvidia/tegra/include/drivers/mce.h b/plat/nvidia/tegra/include/drivers/mce.h
index 4470b6b..5f1bb4f 100644
--- a/plat/nvidia/tegra/include/drivers/mce.h
+++ b/plat/nvidia/tegra/include/drivers/mce.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,7 +69,6 @@
int mce_update_reset_vector(void);
int mce_update_gsc_videomem(void);
int mce_update_gsc_tzdram(void);
-int mce_update_gsc_tzram(void);
__dead2 void mce_enter_ccplex_state(uint32_t state_idx);
void mce_update_cstate_info(const mce_cstate_info_t *cstate);
void mce_verify_firmware_version(void);
diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h
index eb55def..91a24ca 100644
--- a/plat/nvidia/tegra/include/platform_def.h
+++ b/plat/nvidia/tegra/include/platform_def.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,12 +13,25 @@
#include <tegra_def.h>
+/*******************************************************************************
+ * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1
+ ******************************************************************************/
+#if !SEPARATE_CODE_AND_RODATA
+#error "SEPARATE_CODE_AND_RODATA should be set to 1"
+#endif
+
/*
* Platform binary types for linking
*/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
+/*
+ * Platform binary types for linking
+ */
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
/*******************************************************************************
* Generic platform constants
******************************************************************************/
@@ -33,7 +47,7 @@
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_MAX_CPUS_PER_CLUSTER)
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
- PLATFORM_CLUSTER_COUNT + 1)
+ PLATFORM_CLUSTER_COUNT + U(1))
/*******************************************************************************
* Platform console related constants
@@ -72,4 +86,5 @@
#define MAX_IO_DEVICES U(0)
#define MAX_IO_HANDLES U(0)
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/nvidia/tegra/include/t186/tegra186_private.h b/plat/nvidia/tegra/include/t186/tegra186_private.h
index 60174ab..4514e14 100644
--- a/plat/nvidia/tegra/include/t186/tegra186_private.h
+++ b/plat/nvidia/tegra/include/t186/tegra186_private.h
@@ -7,10 +7,6 @@
#ifndef TEGRA186_PRIVATE_H
#define TEGRA186_PRIVATE_H
-void tegra186_cpu_reset_handler(void);
-uint64_t tegra186_get_cpu_reset_handler_base(void);
-uint64_t tegra186_get_cpu_reset_handler_size(void);
-uint64_t tegra186_get_mc_ctx_offset(void);
-void tegra186_set_system_suspend_entry(void);
+uint64_t tegra186_get_mc_ctx_size(void);
#endif /* TEGRA186_PRIVATE_H */
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index dc06445..e39f9ca 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -10,6 +10,12 @@
#include <lib/utils_def.h>
/*******************************************************************************
+ * Chip specific cluster and cpu numbers
+ ******************************************************************************/
+#define PLATFORM_CLUSTER_COUNT U(4)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
+
+/*******************************************************************************
* Chip specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index ad3cee4..f72c9cf 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -47,6 +47,8 @@
uint64_t sc7entry_fw_size;
/* System Suspend Entry Firmware base address */
uint64_t sc7entry_fw_base;
+ /* Enable dual execution */
+ uint8_t enable_ccplex_lock_step;
} plat_params_from_bl2_t;
/*******************************************************************************
diff --git a/plat/nvidia/tegra/platform.mk b/plat/nvidia/tegra/platform.mk
index d0ed5d5..8758820 100644
--- a/plat/nvidia/tegra/platform.mk
+++ b/plat/nvidia/tegra/platform.mk
@@ -13,7 +13,7 @@
# enable assert() for release/debug builds
ENABLE_ASSERTIONS := 1
-PLAT_LOG_LEVEL_ASSERT := 40
+PLAT_LOG_LEVEL_ASSERT := 50
$(eval $(call add_define,PLAT_LOG_LEVEL_ASSERT))
# enable dynamic memory mapping
@@ -40,7 +40,7 @@
# Flag to enable WDT FIQ interrupt handling for Tegra SoCs
# prior to Tegra186
-ENABLE_WDT_LEGACY_FIQ_HANDLING ?= 0
+ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING ?= 0
# Flag to allow relocation of BL32 image to TZDRAM during boot
RELOCATE_BL32_IMAGE ?= 0
@@ -48,7 +48,7 @@
include plat/nvidia/tegra/common/tegra_common.mk
include ${SOC_DIR}/platform_${TARGET_SOC}.mk
-$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING))
+$(eval $(call add_define,ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING))
$(eval $(call add_define,RELOCATE_BL32_IMAGE))
# modify BUILD_PLAT to point to SoC specific build directory
diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk
index 183e188..16bd0ea 100644
--- a/plat/nvidia/tegra/soc/t132/platform_t132.mk
+++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk
@@ -20,6 +20,9 @@
MAX_MMAP_REGIONS := 8
$(eval $(call add_define,MAX_MMAP_REGIONS))
+# platform files
+PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t132
+
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
${COMMON_DIR}/drivers/flowctrl/flowctrl.c \
diff --git a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
index 9e42b2b..54d3b2c 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/mce/mce.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -386,14 +387,6 @@
}
/*******************************************************************************
- * Handler to update carveout values for TZ SysRAM aperture
- ******************************************************************************/
-int32_t mce_update_gsc_tzram(void)
-{
- return mce_update_ccplex_gsc(TEGRA_ARI_GSC_TZRAM);
-}
-
-/*******************************************************************************
* Handler to shutdown/reset the entire system
******************************************************************************/
__dead2 void mce_enter_ccplex_state(uint32_t state_idx)
diff --git a/plat/nvidia/tegra/soc/t186/drivers/se/se.c b/plat/nvidia/tegra/soc/t186/drivers/se/se.c
index dfb9de8..25f8cd0 100644
--- a/plat/nvidia/tegra/soc/t186/drivers/se/se.c
+++ b/plat/nvidia/tegra/soc/t186/drivers/se/se.c
@@ -12,7 +12,6 @@
#include <bpmp_ipc.h>
#include <pmc.h>
#include <security_engine.h>
-#include <tegra186_private.h>
#include <tegra_private.h>
#include "se_private.h"
diff --git a/plat/nvidia/tegra/soc/t186/plat_memctrl.c b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
index 09377bb..4eb68e4 100644
--- a/plat/nvidia/tegra/soc/t186/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t186/plat_memctrl.c
@@ -10,8 +10,8 @@
#include <mce.h>
#include <memctrl_v2.h>
-#include <tegra_mc_def.h>
#include <tegra186_private.h>
+#include <tegra_mc_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
@@ -21,29 +21,6 @@
* Array to hold stream_id override config register offsets
******************************************************************************/
const static uint32_t tegra186_streamid_override_regs[] = {
- MC_STREAMID_OVERRIDE_CFG_PTCR,
- MC_STREAMID_OVERRIDE_CFG_AFIR,
- MC_STREAMID_OVERRIDE_CFG_HDAR,
- MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
- MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
- MC_STREAMID_OVERRIDE_CFG_SATAR,
- MC_STREAMID_OVERRIDE_CFG_MPCORER,
- MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
- MC_STREAMID_OVERRIDE_CFG_AFIW,
- MC_STREAMID_OVERRIDE_CFG_HDAW,
- MC_STREAMID_OVERRIDE_CFG_MPCOREW,
- MC_STREAMID_OVERRIDE_CFG_SATAW,
- MC_STREAMID_OVERRIDE_CFG_ISPRA,
- MC_STREAMID_OVERRIDE_CFG_ISPWA,
- MC_STREAMID_OVERRIDE_CFG_ISPWB,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRD,
- MC_STREAMID_OVERRIDE_CFG_TSECSWR,
- MC_STREAMID_OVERRIDE_CFG_GPUSRD,
- MC_STREAMID_OVERRIDE_CFG_GPUSWR,
MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
MC_STREAMID_OVERRIDE_CFG_SDMMCR,
@@ -52,47 +29,6 @@
MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
MC_STREAMID_OVERRIDE_CFG_SDMMCW,
MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
- MC_STREAMID_OVERRIDE_CFG_VICSRD,
- MC_STREAMID_OVERRIDE_CFG_VICSWR,
- MC_STREAMID_OVERRIDE_CFG_VIW,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
- MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
- MC_STREAMID_OVERRIDE_CFG_APER,
- MC_STREAMID_OVERRIDE_CFG_APEW,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
- MC_STREAMID_OVERRIDE_CFG_SESRD,
- MC_STREAMID_OVERRIDE_CFG_SESWR,
- MC_STREAMID_OVERRIDE_CFG_ETRR,
- MC_STREAMID_OVERRIDE_CFG_ETRW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
- MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
- MC_STREAMID_OVERRIDE_CFG_GPUSRD2,
- MC_STREAMID_OVERRIDE_CFG_GPUSWR2,
- MC_STREAMID_OVERRIDE_CFG_AXISR,
- MC_STREAMID_OVERRIDE_CFG_AXISW,
- MC_STREAMID_OVERRIDE_CFG_EQOSR,
- MC_STREAMID_OVERRIDE_CFG_EQOSW,
- MC_STREAMID_OVERRIDE_CFG_UFSHCR,
- MC_STREAMID_OVERRIDE_CFG_UFSHCW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
- MC_STREAMID_OVERRIDE_CFG_BPMPR,
- MC_STREAMID_OVERRIDE_CFG_BPMPW,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
- MC_STREAMID_OVERRIDE_CFG_AONR,
- MC_STREAMID_OVERRIDE_CFG_AONW,
- MC_STREAMID_OVERRIDE_CFG_AONDMAR,
- MC_STREAMID_OVERRIDE_CFG_AONDMAW,
- MC_STREAMID_OVERRIDE_CFG_SCER,
- MC_STREAMID_OVERRIDE_CFG_SCEW,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
- MC_STREAMID_OVERRIDE_CFG_APEDMAR,
- MC_STREAMID_OVERRIDE_CFG_APEDMAW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
- MC_STREAMID_OVERRIDE_CFG_VICSRD1,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD1
};
/*******************************************************************************
@@ -711,13 +647,6 @@
void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
{
uint32_t val;
- uint64_t src_base_tzdram;
- const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
- uint64_t src_len_in_bytes = BL31_END - BL31_START;
-
- /* base address of BL3-1 source in TZDRAM */
- src_base_tzdram = params_from_bl2->tzdram_base +
- tegra186_get_cpu_reset_handler_size();
/*
* Setup the Memory controller to allow only secure accesses to
@@ -747,15 +676,6 @@
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val);
/*
- * save tzdram_addr_lo and ATF-size, this would be used in SC7-RF to
- * generate SHA256.
- */
- mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO,
- (uint32_t)src_base_tzdram);
- mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI,
- (uint32_t)src_len_in_bytes);
-
- /*
* MCE propagates the security configuration values across the
* CCPLEX.
*/
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 179dd96..6f58427 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -134,8 +134,7 @@
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
/* save MC context to TZDRAM */
- mc_ctx_base = params_from_bl2->tzdram_base +
- tegra186_get_mc_ctx_offset();
+ mc_ctx_base = params_from_bl2->tzdram_base;
tegra_mc_save_context((uintptr_t)mc_ctx_base);
/* Prepare for system suspend */
@@ -158,9 +157,6 @@
(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
(uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
- /* set system suspend state for house-keeping */
- tegra186_set_system_suspend_entry();
-
} else {
; /* do nothing */
}
@@ -289,7 +285,7 @@
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
val = params_from_bl2->tzdram_base +
- tegra186_get_cpu_reset_handler_size();
+ tegra186_get_mc_ctx_size();
/* Initialise communication channel with BPMP */
assert(tegra_bpmp_ipc_init() == 0);
@@ -316,10 +312,19 @@
* BL3-1 over to TZDRAM.
*/
val = params_from_bl2->tzdram_base +
- tegra186_get_cpu_reset_handler_size();
+ tegra186_get_mc_ctx_size();
memcpy16((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
(uintptr_t)BL31_END - (uintptr_t)BL31_BASE);
+ /*
+ * Save code base and size; this would be used by SC7-RF to
+ * verify binary
+ */
+ mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV68_LO,
+ (uint32_t)val);
+ mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV0_HI,
+ (uint32_t)src_len_in_bytes);
+
ret = tegra_bpmp_ipc_disable_clock(TEGRA186_CLK_SE);
if (ret != 0) {
ERROR("Failed to disable clock\n");
diff --git a/plat/nvidia/tegra/soc/t186/plat_secondary.c b/plat/nvidia/tegra/soc/t186/plat_secondary.c
index 1650809..fbb550a 100644
--- a/plat/nvidia/tegra/soc/t186/plat_secondary.c
+++ b/plat/nvidia/tegra/soc/t186/plat_secondary.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,56 +12,30 @@
#include <lib/mmio.h>
#include <mce.h>
-#include <tegra186_private.h>
#include <tegra_def.h>
#include <tegra_private.h>
-#define MISCREG_AA64_RST_LOW 0x2004U
-#define MISCREG_AA64_RST_HIGH 0x2008U
-
#define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U
#define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU
#define CPU_RESET_MODE_AA64 1U
-extern void memcpy16(void *dest, const void *src, unsigned int length);
-
/*******************************************************************************
* Setup secondary CPU vectors
******************************************************************************/
void plat_secondary_setup(void)
{
uint32_t addr_low, addr_high;
- const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
- uint64_t cpu_reset_handler_base, cpu_reset_handler_size;
INFO("Setting up secondary CPU boot\n");
- /*
- * The BL31 code resides in the TZSRAM which loses state
- * when we enter System Suspend. Copy the wakeup trampoline
- * code to TZDRAM to help us exit from System Suspend.
- */
- cpu_reset_handler_base = tegra186_get_cpu_reset_handler_base();
- cpu_reset_handler_size = tegra186_get_cpu_reset_handler_size();
- (void)memcpy16((void *)(uintptr_t)params_from_bl2->tzdram_base,
- (const void *)(uintptr_t)cpu_reset_handler_base,
- cpu_reset_handler_size);
-
/* TZDRAM base will be used as the "resume" address */
- addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
- addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
-
- /* write lower 32 bits first, then the upper 11 bits */
- mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
- mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
+ addr_low = (uintptr_t)&tegra_secure_entrypoint | CPU_RESET_MODE_AA64;
+ addr_high = (uintptr_t)(((uintptr_t)&tegra_secure_entrypoint >> 32U) & 0x7ffU);
/* save reset vector to be used during SYSTEM_SUSPEND exit */
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
addr_low);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
addr_high);
-
- /* update reset vector address to the CCPLEX */
- (void)mce_update_reset_vector();
}
diff --git a/plat/nvidia/tegra/soc/t186/plat_trampoline.S b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
index 818c24b..2fc2046 100644
--- a/plat/nvidia/tegra/soc/t186/plat_trampoline.S
+++ b/plat/nvidia/tegra/soc/t186/plat_trampoline.S
@@ -12,135 +12,30 @@
#include <plat/common/common_def.h>
#include <tegra_def.h>
-#define TEGRA186_STATE_SYSTEM_SUSPEND 0x5C7
-#define TEGRA186_STATE_SYSTEM_RESUME 0x600D
#define TEGRA186_MC_CTX_SIZE 0x93
- .globl tegra186_cpu_reset_handler
-
-/* CPU reset handler routine */
-func tegra186_cpu_reset_handler _align=4
- /* check if we are exiting system suspend state */
- adr x0, __tegra186_system_suspend_state
- ldr x1, [x0]
- mov x2, #TEGRA186_STATE_SYSTEM_SUSPEND
- lsl x2, x2, #16
- add x2, x2, #TEGRA186_STATE_SYSTEM_SUSPEND
- cmp x1, x2
- bne boot_cpu
-
- /* set system resume state */
- mov x1, #TEGRA186_STATE_SYSTEM_RESUME
- lsl x1, x1, #16
- mov x2, #TEGRA186_STATE_SYSTEM_RESUME
- add x1, x1, x2
- str x1, [x0]
- dsb sy
-
- /* prepare to relocate to TZSRAM */
- mov x0, #BL31_BASE
- adr x1, __tegra186_cpu_reset_handler_end
- adr x2, __tegra186_cpu_reset_handler_data
- ldr x2, [x2, #8]
-
- /* memcpy16 */
-m_loop16:
- cmp x2, #16
- b.lt m_loop1
- ldp x3, x4, [x1], #16
- stp x3, x4, [x0], #16
- sub x2, x2, #16
- b m_loop16
- /* copy byte per byte */
-m_loop1:
- cbz x2, boot_cpu
- ldrb w3, [x1], #1
- strb w3, [x0], #1
- subs x2, x2, #1
- b.ne m_loop1
-
-boot_cpu:
- adr x0, __tegra186_cpu_reset_handler_data
- ldr x0, [x0]
- br x0
-endfunc tegra186_cpu_reset_handler
+ .globl tegra186_get_mc_ctx_size
/*
- * Tegra186 reset data (offset 0x0 - 0x430)
+ * Tegra186 reset data (offset 0x0 - 0x420)
*
- * 0x000: secure world's entrypoint
- * 0x008: BL31 size (RO + RW)
- * 0x00C: MC context start
- * 0x42C: MC context end
+ * 0x000: MC context start
+ * 0x420: MC context end
*/
.align 4
- .type __tegra186_cpu_reset_handler_data, %object
- .globl __tegra186_cpu_reset_handler_data
-__tegra186_cpu_reset_handler_data:
- .quad tegra_secure_entrypoint
- .quad __BL31_END__ - BL31_BASE
-
- .globl __tegra186_system_suspend_state
-__tegra186_system_suspend_state:
- .quad 0
-
- .align 4
- .globl __tegra186_mc_context
__tegra186_mc_context:
.rept TEGRA186_MC_CTX_SIZE
.quad 0
.endr
- .size __tegra186_cpu_reset_handler_data, \
- . - __tegra186_cpu_reset_handler_data
.align 4
- .globl __tegra186_cpu_reset_handler_end
-__tegra186_cpu_reset_handler_end:
-
- .globl tegra186_get_cpu_reset_handler_size
- .globl tegra186_get_cpu_reset_handler_base
- .globl tegra186_get_mc_ctx_offset
- .globl tegra186_set_system_suspend_entry
-
-/* return size of the CPU reset handler */
-func tegra186_get_cpu_reset_handler_size
- adr x0, __tegra186_cpu_reset_handler_end
- adr x1, tegra186_cpu_reset_handler
- sub x0, x0, x1
- ret
-endfunc tegra186_get_cpu_reset_handler_size
-
-/* return the start address of the CPU reset handler */
-func tegra186_get_cpu_reset_handler_base
- adr x0, tegra186_cpu_reset_handler
- ret
-endfunc tegra186_get_cpu_reset_handler_base
+__tegra186_mc_context_end:
/* return the size of the MC context */
-func tegra186_get_mc_ctx_offset
- adr x0, __tegra186_mc_context
- adr x1, tegra186_cpu_reset_handler
+func tegra186_get_mc_ctx_size
+ adr x0, __tegra186_mc_context_end
+ adr x1, __tegra186_mc_context
sub x0, x0, x1
ret
-endfunc tegra186_get_mc_ctx_offset
-
-/* set system suspend state before SC7 entry */
-func tegra186_set_system_suspend_entry
- mov x0, #TEGRA_MC_BASE
- mov x3, #MC_SECURITY_CFG3_0
- ldr w1, [x0, x3]
- lsl x1, x1, #32
- mov x3, #MC_SECURITY_CFG0_0
- ldr w2, [x0, x3]
- orr x3, x1, x2 /* TZDRAM base */
- adr x0, __tegra186_system_suspend_state
- adr x1, tegra186_cpu_reset_handler
- sub x2, x0, x1 /* offset in TZDRAM */
- mov x0, #TEGRA186_STATE_SYSTEM_SUSPEND
- lsl x0, x0, #16
- add x0, x0, #TEGRA186_STATE_SYSTEM_SUSPEND
- str x0, [x3, x2] /* set value in TZDRAM */
- dsb sy
- ret
-endfunc tegra186_set_system_suspend_entry
+endfunc tegra186_get_mc_ctx_size
diff --git a/plat/nvidia/tegra/soc/t186/platform_t186.mk b/plat/nvidia/tegra/soc/t186/platform_t186.mk
index d79155f..a534123 100644
--- a/plat/nvidia/tegra/soc/t186/platform_t186.mk
+++ b/plat/nvidia/tegra/soc/t186/platform_t186.mk
@@ -14,7 +14,7 @@
RESET_TO_BL31 := 1
-PROGRAMMABLE_RESET_ADDRESS := 1
+PROGRAMMABLE_RESET_ADDRESS := 0
COLD_BOOT_SINGLE_CPU := 1
@@ -37,7 +37,8 @@
$(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files
-PLAT_INCLUDES += -I${SOC_DIR}/drivers/include
+PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t186 \
+ -I${SOC_DIR}/drivers/include
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
diff --git a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
index 9ccb823..7a68a43 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
+++ b/plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
@@ -7,6 +7,8 @@
#ifndef T194_NVG_H
#define T194_NVG_H
+#include <lib/utils_def.h>
+
/**
* t194_nvg.h - Header for the NVIDIA Generic interface (NVG).
* Official documentation for this interface is included as part
@@ -20,7 +22,7 @@
*/
enum {
TEGRA_NVG_VERSION_MAJOR = U(6),
- TEGRA_NVG_VERSION_MINOR = U(6)
+ TEGRA_NVG_VERSION_MINOR = U(7)
};
typedef enum {
@@ -71,6 +73,9 @@
TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = U(77),
TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = U(78),
TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = U(79),
+ TEGRA_NVG_CHANNEL_RT_SAFE_MASK = U(80),
+ TEGRA_NVG_CHANNEL_RT_WINDOW_US = U(81),
+ TEGRA_NVG_CHANNEL_RT_FWD_PROGRESS_US = U(82),
TEGRA_NVG_CHANNEL_LAST_INDEX
} tegra_nvg_channel_id_t;
@@ -153,7 +158,7 @@
typedef union {
uint64_t flat;
- struct nvg_power_perf_channel_t {
+ struct {
uint32_t perf_per_watt : U(1);
uint32_t reserved_31_1 : U(31);
uint32_t reserved_63_32 : U(32);
@@ -162,7 +167,7 @@
typedef union {
uint64_t flat;
- struct nvg_power_modes_channel_t {
+ struct {
uint32_t low_battery : U(1);
uint32_t reserved_1_1 : U(1);
uint32_t battery_save : U(1);
@@ -182,7 +187,7 @@
typedef union {
uint64_t flat;
- struct nvg_ccplex_cache_control_channel_t {
+ struct {
uint32_t gpu_ways : U(5);
uint32_t reserved_7_5 : U(3);
uint32_t gpu_only_ways : U(5);
@@ -203,7 +208,7 @@
typedef union {
uint64_t flat;
- struct nvg_wake_time_channel_t {
+ struct {
uint32_t wake_time : U(32);
uint32_t reserved_63_32 : U(32);
} bits;
@@ -211,7 +216,7 @@
typedef union {
uint64_t flat;
- struct nvg_cstate_info_channel_t {
+ struct {
uint32_t cluster_state : U(3);
uint32_t reserved_6_3 : U(4);
uint32_t update_cluster : U(1);
@@ -242,7 +247,7 @@
typedef union {
uint64_t flat;
- struct nvg_lower_bound_channel_t {
+ struct {
uint32_t crossover_value : U(32);
uint32_t reserved_63_32 : U(32);
} bits;
@@ -250,7 +255,7 @@
typedef union {
uint64_t flat;
- struct nvg_cstate_stat_query_channel_t {
+ struct {
uint32_t unit_id : U(4);
uint32_t reserved_15_4 : U(12);
uint32_t stat_id : U(16);
@@ -260,7 +265,7 @@
typedef union {
uint64_t flat;
- struct nvg_num_cores_channel_t {
+ struct {
uint32_t num_cores : U(4);
uint32_t reserved_31_4 : U(28);
uint32_t reserved_63_32 : U(32);
@@ -269,7 +274,7 @@
typedef union {
uint64_t flat;
- struct nvg_unique_logical_id_channel_t {
+ struct {
uint32_t unique_core_id : U(3);
uint32_t reserved_31_3 : U(29);
uint32_t reserved_63_32 : U(32);
@@ -278,7 +283,7 @@
typedef union {
uint64_t flat;
- struct nvg_logical_to_physical_mappings_channel_t {
+ struct {
uint32_t lcore0_pcore_id : U(4);
uint32_t lcore1_pcore_id : U(4);
uint32_t lcore2_pcore_id : U(4);
@@ -306,7 +311,7 @@
typedef union {
uint64_t flat;
- struct nvg_is_sc7_allowed_channel_t {
+ struct {
uint32_t is_sc7_allowed : U(1);
uint32_t reserved_31_1 : U(31);
uint32_t reserved_63_32 : U(32);
@@ -315,7 +320,7 @@
typedef union {
uint64_t flat;
- struct nvg_core_online_channel_t {
+ struct {
uint32_t core_id : U(4);
uint32_t reserved_31_4 : U(28);
uint32_t reserved_63_32 : U(32);
@@ -324,7 +329,7 @@
typedef union {
uint64_t flat;
- struct nvg_cc3_control_channel_t {
+ struct {
uint32_t freq_req : U(9);
uint32_t reserved_30_9 : U(22);
uint32_t enable : U(1);
@@ -374,7 +379,7 @@
typedef union {
uint64_t flat;
- struct nvg_update_ccplex_gsc_channel_t {
+ struct {
uint32_t gsc_enum : U(16);
uint32_t reserved_31_16 : U(16);
uint32_t reserved_63_32 : U(32);
@@ -411,7 +416,7 @@
typedef union {
uint64_t flat;
- struct nvg_hsm_error_ctrl_channel_t {
+ struct {
uint32_t uncorr : U(1);
uint32_t corr : U(1);
uint32_t reserved_31_2 : U(30);
diff --git a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
index 00c671b..7edd7a0 100644
--- a/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
+++ b/plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
@@ -116,25 +116,6 @@
}
/*******************************************************************************
- * Handler to update carveout values for TZ SysRAM aperture
- ******************************************************************************/
-int32_t mce_update_gsc_tzram(void)
-{
- int32_t ret;
-
- /*
- * MCE firmware is not running on simulation platforms.
- */
- if (mce_firmware_not_supported()) {
- ret = -EINVAL;
- } else {
- ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM);
- }
-
- return ret;
-}
-
-/*******************************************************************************
* Handler to issue the UPDATE_CSTATE_INFO request
******************************************************************************/
void mce_update_cstate_info(const mce_cstate_info_t *cstate)
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
index 2d5f8e3..9a4d22e 100644
--- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -12,150 +12,6 @@
#include <tegra_platform.h>
/*******************************************************************************
- * Array to hold stream_id override config register offsets
- ******************************************************************************/
-const static uint32_t tegra194_streamid_override_regs[] = {
- MC_STREAMID_OVERRIDE_CFG_PTCR,
- MC_STREAMID_OVERRIDE_CFG_HDAR,
- MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
- MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
- MC_STREAMID_OVERRIDE_CFG_SATAR,
- MC_STREAMID_OVERRIDE_CFG_MPCORER,
- MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
- MC_STREAMID_OVERRIDE_CFG_HDAW,
- MC_STREAMID_OVERRIDE_CFG_MPCOREW,
- MC_STREAMID_OVERRIDE_CFG_SATAW,
- MC_STREAMID_OVERRIDE_CFG_ISPRA,
- MC_STREAMID_OVERRIDE_CFG_ISPFALR,
- MC_STREAMID_OVERRIDE_CFG_ISPWA,
- MC_STREAMID_OVERRIDE_CFG_ISPWB,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
- MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRD,
- MC_STREAMID_OVERRIDE_CFG_TSECSWR,
- MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
- MC_STREAMID_OVERRIDE_CFG_SDMMCR,
- MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
- MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
- MC_STREAMID_OVERRIDE_CFG_SDMMCW,
- MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
- MC_STREAMID_OVERRIDE_CFG_VICSRD,
- MC_STREAMID_OVERRIDE_CFG_VICSWR,
- MC_STREAMID_OVERRIDE_CFG_VIW,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
- MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
- MC_STREAMID_OVERRIDE_CFG_APER,
- MC_STREAMID_OVERRIDE_CFG_APEW,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
- MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
- MC_STREAMID_OVERRIDE_CFG_SESRD,
- MC_STREAMID_OVERRIDE_CFG_SESWR,
- MC_STREAMID_OVERRIDE_CFG_AXIAPR,
- MC_STREAMID_OVERRIDE_CFG_AXIAPW,
- MC_STREAMID_OVERRIDE_CFG_ETRR,
- MC_STREAMID_OVERRIDE_CFG_ETRW,
- MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
- MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
- MC_STREAMID_OVERRIDE_CFG_AXISR,
- MC_STREAMID_OVERRIDE_CFG_AXISW,
- MC_STREAMID_OVERRIDE_CFG_EQOSR,
- MC_STREAMID_OVERRIDE_CFG_EQOSW,
- MC_STREAMID_OVERRIDE_CFG_UFSHCR,
- MC_STREAMID_OVERRIDE_CFG_UFSHCW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
- MC_STREAMID_OVERRIDE_CFG_BPMPR,
- MC_STREAMID_OVERRIDE_CFG_BPMPW,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
- MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
- MC_STREAMID_OVERRIDE_CFG_AONR,
- MC_STREAMID_OVERRIDE_CFG_AONW,
- MC_STREAMID_OVERRIDE_CFG_AONDMAR,
- MC_STREAMID_OVERRIDE_CFG_AONDMAW,
- MC_STREAMID_OVERRIDE_CFG_SCER,
- MC_STREAMID_OVERRIDE_CFG_SCEW,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
- MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
- MC_STREAMID_OVERRIDE_CFG_APEDMAR,
- MC_STREAMID_OVERRIDE_CFG_APEDMAW,
- MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
- MC_STREAMID_OVERRIDE_CFG_VICSRD1,
- MC_STREAMID_OVERRIDE_CFG_NVDECSRD1,
- MC_STREAMID_OVERRIDE_CFG_VIFALR,
- MC_STREAMID_OVERRIDE_CFG_VIFALW,
- MC_STREAMID_OVERRIDE_CFG_DLA0RDA,
- MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB,
- MC_STREAMID_OVERRIDE_CFG_DLA0WRA,
- MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB,
- MC_STREAMID_OVERRIDE_CFG_DLA1RDA,
- MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB,
- MC_STREAMID_OVERRIDE_CFG_DLA1WRA,
- MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDA,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDB,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDC,
- MC_STREAMID_OVERRIDE_CFG_PVA0WRA,
- MC_STREAMID_OVERRIDE_CFG_PVA0WRB,
- MC_STREAMID_OVERRIDE_CFG_PVA0WRC,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDA,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDB,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDC,
- MC_STREAMID_OVERRIDE_CFG_PVA1WRA,
- MC_STREAMID_OVERRIDE_CFG_PVA1WRB,
- MC_STREAMID_OVERRIDE_CFG_PVA1WRC,
- MC_STREAMID_OVERRIDE_CFG_RCER,
- MC_STREAMID_OVERRIDE_CFG_RCEW,
- MC_STREAMID_OVERRIDE_CFG_RCEDMAR,
- MC_STREAMID_OVERRIDE_CFG_RCEDMAW,
- MC_STREAMID_OVERRIDE_CFG_NVENC1SRD,
- MC_STREAMID_OVERRIDE_CFG_NVENC1SWR,
- MC_STREAMID_OVERRIDE_CFG_PCIE0R,
- MC_STREAMID_OVERRIDE_CFG_PCIE0W,
- MC_STREAMID_OVERRIDE_CFG_PCIE1R,
- MC_STREAMID_OVERRIDE_CFG_PCIE1W,
- MC_STREAMID_OVERRIDE_CFG_PCIE2AR,
- MC_STREAMID_OVERRIDE_CFG_PCIE2AW,
- MC_STREAMID_OVERRIDE_CFG_PCIE3R,
- MC_STREAMID_OVERRIDE_CFG_PCIE3W,
- MC_STREAMID_OVERRIDE_CFG_PCIE4R,
- MC_STREAMID_OVERRIDE_CFG_PCIE4W,
- MC_STREAMID_OVERRIDE_CFG_PCIE5R,
- MC_STREAMID_OVERRIDE_CFG_PCIE5W,
- MC_STREAMID_OVERRIDE_CFG_ISPFALW,
- MC_STREAMID_OVERRIDE_CFG_DLA0RDA1,
- MC_STREAMID_OVERRIDE_CFG_DLA1RDA1,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDA1,
- MC_STREAMID_OVERRIDE_CFG_PVA0RDB1,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDA1,
- MC_STREAMID_OVERRIDE_CFG_PVA1RDB1,
- MC_STREAMID_OVERRIDE_CFG_PCIE5R1,
- MC_STREAMID_OVERRIDE_CFG_NVENCSRD1,
- MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1,
- MC_STREAMID_OVERRIDE_CFG_ISPRA1,
- MC_STREAMID_OVERRIDE_CFG_PCIE0R1,
- MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD,
- MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1,
- MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR,
- MC_STREAMID_OVERRIDE_CFG_MIU0R,
- MC_STREAMID_OVERRIDE_CFG_MIU0W,
- MC_STREAMID_OVERRIDE_CFG_MIU1R,
- MC_STREAMID_OVERRIDE_CFG_MIU1W,
- MC_STREAMID_OVERRIDE_CFG_MIU2R,
- MC_STREAMID_OVERRIDE_CFG_MIU2W,
- MC_STREAMID_OVERRIDE_CFG_MIU3R,
- MC_STREAMID_OVERRIDE_CFG_MIU3W,
- MC_STREAMID_OVERRIDE_CFG_MIU4R,
- MC_STREAMID_OVERRIDE_CFG_MIU4W,
- MC_STREAMID_OVERRIDE_CFG_MIU5R,
- MC_STREAMID_OVERRIDE_CFG_MIU5W,
- MC_STREAMID_OVERRIDE_CFG_MIU6R,
- MC_STREAMID_OVERRIDE_CFG_MIU6W,
- MC_STREAMID_OVERRIDE_CFG_MIU7R,
- MC_STREAMID_OVERRIDE_CFG_MIU7W
-};
-
-/*******************************************************************************
* Array to hold the security configs for stream IDs
******************************************************************************/
const static mc_streamid_security_cfg_t tegra194_streamid_sec_cfgs[] = {
@@ -571,8 +427,6 @@
* Struct to hold the memory controller settings
******************************************************************************/
static tegra_mc_settings_t tegra194_mc_settings = {
- .streamid_override_cfg = tegra194_streamid_override_regs,
- .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_override_regs),
.streamid_security_cfg = tegra194_streamid_sec_cfgs,
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra194_streamid_sec_cfgs),
.get_mc_system_suspend_ctx = tegra194_get_mc_system_suspend_ctx
diff --git a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
index d92025b..ce5815b 100644
--- a/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
@@ -368,7 +368,11 @@
int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
+ const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
+ uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step;
uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
+ cpu_context_t *ctx = cm_get_context(NON_SECURE);
+ uint64_t actlr_elx;
/*
* Reset power state info for CPUs when onlining, we set
@@ -377,6 +381,10 @@
* will re-init this info from non-secure software when the
* core come online.
*/
+ actlr_elx = read_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1));
+ actlr_elx &= ~DENVER_CPU_PMSTATE_MASK;
+ actlr_elx |= DENVER_CPU_PMSTATE_C1;
+ write_ctx_reg((get_el1_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
/*
* Check if we are exiting from deep sleep and restore SE
@@ -446,13 +454,23 @@
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
}
+ }
- /*
- * Reset power state info for the last core doing SC7
- * entry and exit, we set deepest power state as CC7
- * and SC7 for SC7 entry which may not be requested by
- * non-secure SW which controls idle states.
- */
+ /*
+ * Enable dual execution optimized translations for all ELx.
+ */
+ if (enable_ccplex_lock_step != 0U) {
+ actlr_elx = read_actlr_el3();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3;
+ write_actlr_el3(actlr_elx);
+
+ actlr_elx = read_actlr_el2();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2;
+ write_actlr_el2(actlr_elx);
+
+ actlr_elx = read_actlr_el1();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1;
+ write_actlr_el1(actlr_elx);
}
return PSCI_E_SUCCESS;
diff --git a/plat/nvidia/tegra/soc/t194/plat_setup.c b/plat/nvidia/tegra/soc/t194/plat_setup.c
index 235fba4..8255540 100644
--- a/plat/nvidia/tegra/soc/t194/plat_setup.c
+++ b/plat/nvidia/tegra/soc/t194/plat_setup.c
@@ -201,6 +201,10 @@
******************************************************************************/
void plat_early_platform_setup(void)
{
+ const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
+ uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step;
+ uint64_t actlr_elx;
+
/* sanity check MCE firmware compatibility */
mce_verify_firmware_version();
@@ -250,6 +254,23 @@
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
}
+
+ /*
+ * Enable dual execution optimized translations for all ELx.
+ */
+ if (enable_ccplex_lock_step != 0U) {
+ actlr_elx = read_actlr_el3();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3;
+ write_actlr_el3(actlr_elx);
+
+ actlr_elx = read_actlr_el2();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2;
+ write_actlr_el2(actlr_elx);
+
+ actlr_elx = read_actlr_el1();
+ actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1;
+ write_actlr_el1(actlr_elx);
+ }
}
/* Secure IRQs for Tegra194 */
diff --git a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
index 33694a1..884762d 100644
--- a/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
+++ b/plat/nvidia/tegra/soc/t194/plat_sip_calls.c
@@ -16,11 +16,13 @@
#include <common/runtime_svc.h>
#include <tegra_private.h>
#include <tegra_platform.h>
+#include <smmu.h>
#include <stdbool.h>
/*******************************************************************************
* Tegra194 SiP SMCs
******************************************************************************/
+#define TEGRA_SIP_GET_SMMU_PER 0xC200FF00U
/*******************************************************************************
* This function is responsible for handling all T194 SiP calls
@@ -34,13 +36,43 @@
void *handle,
uint64_t flags)
{
- int32_t ret = -ENOTSUP;
+ int32_t ret = 0;
+ uint32_t i, smmu_per[6] = {0};
+ uint32_t num_smmu_devices = plat_get_num_smmu_devices();
+ uint64_t per[3] = {0ULL};
- (void)smc_fid;
(void)x1;
(void)x4;
(void)cookie;
(void)flags;
+ switch (smc_fid) {
+ case TEGRA_SIP_GET_SMMU_PER:
+
+ /* make sure we dont go past the array length */
+ assert(num_smmu_devices <= ARRAY_SIZE(smmu_per));
+
+ /* read all supported SMMU_PER records */
+ for (i = 0U; i < num_smmu_devices; i++) {
+ smmu_per[i] = tegra_smmu_read_32(i, SMMU_GSR0_PER);
+ }
+
+ /* pack results into 3 64bit variables. */
+ per[0] = smmu_per[0] | ((uint64_t)smmu_per[1] << 32U);
+ per[1] = smmu_per[2] | ((uint64_t)smmu_per[3] << 32U);
+ per[2] = smmu_per[4] | ((uint64_t)smmu_per[5] << 32U);
+
+ /* provide the results via X1-X3 CPU registers */
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, per[0]);
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, per[1]);
+ write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X3, per[2]);
+
+ break;
+
+ default:
+ ret = -ENOTSUP;
+ break;
+ }
+
return ret;
}
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index 78766fc..c02128c 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -24,12 +24,6 @@
TZDRAM_BASE := 0x40000000
$(eval $(call add_define,TZDRAM_BASE))
-PLATFORM_CLUSTER_COUNT := 4
-$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
-
-PLATFORM_MAX_CPUS_PER_CLUSTER := 2
-$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
-
MAX_XLAT_TABLES := 25
$(eval $(call add_define,MAX_XLAT_TABLES))
@@ -37,7 +31,8 @@
$(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files
-PLAT_INCLUDES += -I${SOC_DIR}/drivers/include
+PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t194 \
+ -I${SOC_DIR}/drivers/include
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/denver.S \
diff --git a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c
index 635018d..4860858 100644
--- a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c
+++ b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c
@@ -927,17 +927,12 @@
val &= ~ENTROPY_RESET_BIT;
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEVICES_W, val);
- if (!tegra_chipid_is_t210_b01()) {
-
- /*
- * T210 SE clock source is turned off in kernel, to simplify
- * SE clock source setting, we switch SE clock source to
- * CLK_M, SE_CLK_DIVISOR = 0. T210 B01 SE clock source is
- * always on, so don't need this setting.
- */
- mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_RST_CTL_CLK_SRC_SE,
- SE_CLK_SRC_CLK_M);
- }
+ /*
+ * Switch SE clock source to CLK_M, to make sure SE clock
+ * is on when saving SE context
+ */
+ mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_RST_CTL_CLK_SRC_SE,
+ SE_CLK_SRC_CLK_M);
/* Enable SE clock */
val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_V);
diff --git a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
index f29e624..7f73ea5 100644
--- a/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
@@ -534,6 +534,13 @@
}
/*
+ * Mark this CPU as ON in the cpu_powergate_mask[],
+ * so that we use Flow Controller for all subsequent
+ * power ups.
+ */
+ cpu_powergate_mask[plat_my_core_pos()] = 1;
+
+ /*
* T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's
* used for power management and boot purposes. Inform the BPMP that
* we have completed the cluster power up.
@@ -561,7 +568,6 @@
/* Turn on CPU using flow controller or PMC */
if (cpu_powergate_mask[cpu] == 0) {
tegra_pmc_cpu_on(cpu);
- cpu_powergate_mask[cpu] = 1;
} else {
tegra_fc_cpu_on(cpu);
}
diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk
index ba827a0..14e3324 100644
--- a/plat/nvidia/tegra/soc/t210/platform_t210.mk
+++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk
@@ -23,10 +23,10 @@
MAX_MMAP_REGIONS := 16
$(eval $(call add_define,MAX_MMAP_REGIONS))
-ENABLE_WDT_LEGACY_FIQ_HANDLING := 1
-$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING))
+ENABLE_TEGRA_WDT_LEGACY_FIQ_HANDLING := 1
-PLAT_INCLUDES += -I${SOC_DIR}/drivers/se
+PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t210 \
+ -I${SOC_DIR}/drivers/se
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
lib/cpus/aarch64/cortex_a53.S \
diff --git a/plat/rpi/common/include/rpi_shared.h b/plat/rpi/common/include/rpi_shared.h
index de83571..6863438 100644
--- a/plat/rpi/common/include/rpi_shared.h
+++ b/plat/rpi/common/include/rpi_shared.h
@@ -14,7 +14,7 @@
******************************************************************************/
/* Utility functions */
-void rpi3_console_init(unsigned int base_clk_rate);
+void rpi3_console_init(void);
void rpi3_setup_page_tables(uintptr_t total_base, size_t total_size,
uintptr_t code_start, uintptr_t code_limit,
uintptr_t rodata_start, uintptr_t rodata_limit
diff --git a/plat/rpi/common/rpi3_common.c b/plat/rpi/common/rpi3_common.c
index 27281f2..ef88bf1 100644
--- a/plat/rpi/common/rpi3_common.c
+++ b/plat/rpi/common/rpi3_common.c
@@ -13,7 +13,9 @@
#include <common/debug.h>
#include <bl31/interrupt_mgmt.h>
#include <drivers/console.h>
+#include <drivers/rpi3/gpio/rpi3_gpio.h>
#include <drivers/ti/uart/uart_16550.h>
+#include <drivers/arm/pl011.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <rpi_hw.h>
@@ -104,16 +106,33 @@
******************************************************************************/
static console_t rpi3_console;
-void rpi3_console_init(unsigned int base_clk_rate)
+
+static bool rpi3_use_mini_uart(void)
+{
+ return rpi3_gpio_get_select(14) == RPI3_GPIO_FUNC_ALT5;
+}
+
+void rpi3_console_init(void)
{
int console_scope = CONSOLE_FLAG_BOOT;
-#if RPI3_RUNTIME_UART != -1
- console_scope |= CONSOLE_FLAG_RUNTIME;
-#endif
- int rc = console_16550_register(PLAT_RPI3_UART_BASE,
- base_clk_rate,
- PLAT_RPI3_UART_BAUDRATE,
- &rpi3_console);
+ int rc;
+
+ if (RPI3_RUNTIME_UART != -1)
+ console_scope |= CONSOLE_FLAG_RUNTIME;
+
+ rpi3_gpio_init();
+
+ if (rpi3_use_mini_uart())
+ rc = console_16550_register(PLAT_RPI_MINI_UART_BASE,
+ 0,
+ PLAT_RPI_UART_BAUDRATE,
+ &rpi3_console);
+ else
+ rc = console_pl011_register(PLAT_RPI_PL011_UART_BASE,
+ PLAT_RPI_PL011_UART_CLOCK,
+ PLAT_RPI_UART_BAUDRATE,
+ &rpi3_console);
+
if (rc == 0) {
/*
* The crash console doesn't use the multi console API, it uses
diff --git a/plat/rpi/rpi3/aarch64/plat_helpers.S b/plat/rpi/rpi3/aarch64/plat_helpers.S
index 24278bd..ab925b6 100644
--- a/plat/rpi/rpi3/aarch64/plat_helpers.S
+++ b/plat/rpi/rpi3/aarch64/plat_helpers.S
@@ -9,8 +9,6 @@
#include <assert_macros.S>
#include <platform_def.h>
-#include "../include/rpi_hw.h"
-
.globl plat_crash_console_flush
.globl plat_crash_console_init
.globl plat_crash_console_putc
@@ -133,9 +131,9 @@
* ---------------------------------------------
*/
func plat_crash_console_init
- mov_imm x0, PLAT_RPI3_UART_BASE
- mov_imm x1, PLAT_RPI3_UART_CLK_IN_HZ
- mov_imm x2, PLAT_RPI3_UART_BAUDRATE
+ mov_imm x0, PLAT_RPI_MINI_UART_BASE
+ mov x1, xzr
+ mov x2, xzr
b console_16550_core_init
endfunc plat_crash_console_init
@@ -147,7 +145,7 @@
* ---------------------------------------------
*/
func plat_crash_console_putc
- mov_imm x1, PLAT_RPI3_UART_BASE
+ mov_imm x1, PLAT_RPI_MINI_UART_BASE
b console_16550_core_putc
endfunc plat_crash_console_putc
@@ -160,6 +158,6 @@
* ---------------------------------------------
*/
func plat_crash_console_flush
- mov_imm x0, PLAT_RPI3_UART_BASE
+ mov_imm x0, PLAT_RPI_MINI_UART_BASE
b console_16550_core_flush
endfunc plat_crash_console_flush
diff --git a/plat/rpi/rpi3/include/platform_def.h b/plat/rpi/rpi3/include/platform_def.h
index e308f70..9cacd99 100644
--- a/plat/rpi/rpi3/include/platform_def.h
+++ b/plat/rpi/rpi3/include/platform_def.h
@@ -249,9 +249,10 @@
/*
* Serial-related constants.
*/
-#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE
-#define PLAT_RPI3_UART_CLK_IN_HZ RPI3_MINI_UART_CLK_IN_HZ
-#define PLAT_RPI3_UART_BAUDRATE ULL(115200)
+#define PLAT_RPI_MINI_UART_BASE RPI3_MINI_UART_BASE
+#define PLAT_RPI_PL011_UART_BASE RPI3_PL011_UART_BASE
+#define PLAT_RPI_PL011_UART_CLOCK RPI3_PL011_UART_CLOCK
+#define PLAT_RPI_UART_BAUDRATE ULL(115200)
/*
* System counter
diff --git a/plat/rpi/rpi3/include/rpi_hw.h b/plat/rpi/rpi3/include/rpi_hw.h
index 01d5b4a..2aecab3 100644
--- a/plat/rpi/rpi3/include/rpi_hw.h
+++ b/plat/rpi/rpi3/include/rpi_hw.h
@@ -77,11 +77,15 @@
#define RPI3_RNG_INT_MASK_DISABLE U(0x1)
/*
- * Serial port (called 'Mini UART' in the BCM docucmentation).
+ * Serial ports:
+ * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART.
+ * There is also a PL011 UART, multiplexed to the same pins.
*/
#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040)
#define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
-#define RPI3_MINI_UART_CLK_IN_HZ ULL(500000000)
+#define RPI3_IO_PL011_UART_OFFSET ULL(0x00201000)
+#define RPI3_PL011_UART_BASE (RPI_IO_BASE + RPI3_IO_PL011_UART_OFFSET)
+#define RPI3_PL011_UART_CLOCK ULL(48000000)
/*
* GPIO controller
diff --git a/plat/rpi/rpi3/platform.mk b/plat/rpi/rpi3/platform.mk
index a21a770..a5b8904 100644
--- a/plat/rpi/rpi3/platform.mk
+++ b/plat/rpi/rpi3/platform.mk
@@ -11,6 +11,10 @@
-Iplat/rpi/rpi3/include
PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \
+ drivers/arm/pl011/aarch64/pl011_console.S \
+ drivers/gpio/gpio.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/rpi3/gpio/rpi3_gpio.c \
plat/rpi/common/rpi3_common.c \
${XLAT_TABLES_LIB_SRCS}
@@ -29,10 +33,7 @@
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
- drivers/gpio/gpio.c \
- drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
- drivers/rpi3/gpio/rpi3_gpio.c \
drivers/io/io_block.c \
drivers/mmc/mmc.c \
drivers/rpi3/sdhost/rpi3_sdhost.c \
diff --git a/plat/rpi/rpi3/rpi3_bl1_setup.c b/plat/rpi/rpi3/rpi3_bl1_setup.c
index dcce76e..3ac30e0 100644
--- a/plat/rpi/rpi3/rpi3_bl1_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl1_setup.c
@@ -35,7 +35,7 @@
0x80000000);
/* Initialize the console to provide early debug support */
- rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ);
+ rpi3_console_init();
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL_RAM_BASE;
diff --git a/plat/rpi/rpi3/rpi3_bl2_setup.c b/plat/rpi/rpi3/rpi3_bl2_setup.c
index 44827c6..db71817 100644
--- a/plat/rpi/rpi3/rpi3_bl2_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl2_setup.c
@@ -24,17 +24,6 @@
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
-/* rpi3 GPIO setup function. */
-static void rpi3_gpio_setup(void)
-{
- struct rpi3_gpio_params params;
-
- memset(¶ms, 0, sizeof(struct rpi3_gpio_params));
- params.reg_base = RPI3_GPIO_BASE;
-
- rpi3_gpio_init(¶ms);
-}
-
/* Data structure which holds the MMC info */
static struct mmc_device_info mmc_info;
@@ -62,13 +51,13 @@
meminfo_t *mem_layout = (meminfo_t *) arg1;
/* Initialize the console to provide early debug support */
- rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ);
+ rpi3_console_init();
/* Enable arch timer */
generic_delay_timer_init();
/* Setup GPIO driver */
- rpi3_gpio_setup();
+ rpi3_gpio_init();
/* Setup the BL2 memory layout */
bl2_tzram_layout = *mem_layout;
diff --git a/plat/rpi/rpi3/rpi3_bl31_setup.c b/plat/rpi/rpi3/rpi3_bl31_setup.c
index 24a5613..5915753 100644
--- a/plat/rpi/rpi3/rpi3_bl31_setup.c
+++ b/plat/rpi/rpi3/rpi3_bl31_setup.c
@@ -72,7 +72,7 @@
{
/* Initialize the console to provide early debug support */
- rpi3_console_init(PLAT_RPI3_UART_CLK_IN_HZ);
+ rpi3_console_init();
/*
* In debug builds, a special value is passed in 'arg1' to verify
diff --git a/plat/rpi/rpi4/aarch64/plat_helpers.S b/plat/rpi/rpi4/aarch64/plat_helpers.S
index 083c30e..fac1b20 100644
--- a/plat/rpi/rpi4/aarch64/plat_helpers.S
+++ b/plat/rpi/rpi4/aarch64/plat_helpers.S
@@ -10,8 +10,6 @@
#include <platform_def.h>
#include <cortex_a72.h>
-#include "../include/rpi_hw.h"
-
.globl plat_crash_console_flush
.globl plat_crash_console_init
.globl plat_crash_console_putc
@@ -135,7 +133,7 @@
* ---------------------------------------------
*/
func plat_crash_console_init
- mov_imm x0, PLAT_RPI3_UART_BASE
+ mov_imm x0, PLAT_RPI_MINI_UART_BASE
mov x1, xzr
mov x2, xzr
b console_16550_core_init
@@ -149,7 +147,7 @@
* ---------------------------------------------
*/
func plat_crash_console_putc
- mov_imm x1, PLAT_RPI3_UART_BASE
+ mov_imm x1, PLAT_RPI_MINI_UART_BASE
b console_16550_core_putc
endfunc plat_crash_console_putc
@@ -162,7 +160,7 @@
* ---------------------------------------------
*/
func plat_crash_console_flush
- mov_imm x0, PLAT_RPI3_UART_BASE
+ mov_imm x0, PLAT_RPI_MINI_UART_BASE
b console_16550_core_flush
endfunc plat_crash_console_flush
diff --git a/plat/rpi/rpi4/include/platform_def.h b/plat/rpi/rpi4/include/platform_def.h
index a9ecdba..6f6bbbe 100644
--- a/plat/rpi/rpi4/include/platform_def.h
+++ b/plat/rpi/rpi4/include/platform_def.h
@@ -126,8 +126,10 @@
/*
* Serial-related constants.
*/
-#define PLAT_RPI3_UART_BASE RPI3_MINI_UART_BASE
-#define PLAT_RPI3_UART_BAUDRATE ULL(115200)
+#define PLAT_RPI_MINI_UART_BASE RPI4_MINI_UART_BASE
+#define PLAT_RPI_PL011_UART_BASE RPI4_PL011_UART_BASE
+#define PLAT_RPI_PL011_UART_CLOCK RPI4_PL011_UART_CLOCK
+#define PLAT_RPI_UART_BAUDRATE ULL(115200)
/*
* System counter
diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h
index b1dd4e9..7185106 100644
--- a/plat/rpi/rpi4/include/rpi_hw.h
+++ b/plat/rpi/rpi4/include/rpi_hw.h
@@ -77,10 +77,15 @@
#define RPI3_RNG_INT_MASK_DISABLE U(0x1)
/*
- * Serial port (called 'Mini UART' in the Broadcom documentation).
+ * Serial ports:
+ * 'Mini UART' in the BCM docucmentation is the 8250 compatible UART.
+ * There is also a PL011 UART, multiplexed to the same pins.
*/
-#define RPI3_IO_MINI_UART_OFFSET ULL(0x00215040)
-#define RPI3_MINI_UART_BASE (RPI_IO_BASE + RPI3_IO_MINI_UART_OFFSET)
+#define RPI4_IO_MINI_UART_OFFSET ULL(0x00215040)
+#define RPI4_MINI_UART_BASE (RPI_IO_BASE + RPI4_IO_MINI_UART_OFFSET)
+#define RPI4_IO_PL011_UART_OFFSET ULL(0x00201000)
+#define RPI4_PL011_UART_BASE (RPI_IO_BASE + RPI4_IO_PL011_UART_OFFSET)
+#define RPI4_PL011_UART_CLOCK ULL(48000000)
/*
* GPIO controller
diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk
index 2038021..49e78df 100644
--- a/plat/rpi/rpi4/platform.mk
+++ b/plat/rpi/rpi4/platform.mk
@@ -11,6 +11,7 @@
-Iplat/rpi/rpi4/include
PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \
+ drivers/arm/pl011/aarch64/pl011_console.S \
plat/rpi/common/rpi3_common.c \
${XLAT_TABLES_LIB_SRCS}
@@ -20,6 +21,9 @@
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_helpers.c \
drivers/arm/gic/v2/gicv2_main.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/gpio/gpio.c \
+ drivers/rpi3/gpio/rpi3_gpio.c \
plat/common/plat_gicv2.c \
plat/rpi/rpi4/rpi4_bl31_setup.c \
plat/rpi/common/rpi3_pm.c \
diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c
index 9e3b539..0a49d81 100644
--- a/plat/rpi/rpi4/rpi4_bl31_setup.c
+++ b/plat/rpi/rpi4/rpi4_bl31_setup.c
@@ -132,14 +132,8 @@
/* Early GPU firmware revisions need a little break here. */
ldelay(100000);
- /*
- * Initialize the console to provide early debug support.
- * We rely on the GPU firmware to have initialised the UART correctly,
- * as the baud base clock rate differs across GPU firmware revisions.
- * Providing a base clock of 0 lets the 16550 UART init routine skip
- * the initial enablement and baud rate setup.
- */
- rpi3_console_init(0);
+ /* Initialize the console to provide early debug support. */
+ rpi3_console_init();
bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
bl33_image_ep_info.spsr = rpi3_get_spsr_for_bl33_entry();
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index 4fa796f..acb323c 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,6 +92,7 @@
return status;
}
+#if ENABLE_ASSERTIONS
/*******************************************************************************
* This function returns the address cells from the node parent.
* Returns:
@@ -100,7 +101,7 @@
* - a default value if undefined #address-cells property as per libfdt
* implementation.
******************************************************************************/
-int fdt_get_node_parent_address_cells(int node)
+static int fdt_get_node_parent_address_cells(int node)
{
int parent;
@@ -120,7 +121,7 @@
* - a default value if undefined #size-cells property as per libfdt
* implementation.
******************************************************************************/
-int fdt_get_node_parent_size_cells(int node)
+static int fdt_get_node_parent_size_cells(int node)
{
int parent;
@@ -131,6 +132,7 @@
return fdt_size_cells(fdt, parent);
}
+#endif
/*******************************************************************************
* This function reads a value of a node property (generic use of fdt
@@ -467,7 +469,7 @@
}
pwr_regulators_node = fdt_subnode_offset(fdt, node, "pwr-regulators");
- if (node < 0) {
+ if (pwr_regulators_node < 0) {
INFO("%s: Cannot read pwr-regulators node in DT\n", __func__);
return 0;
}
diff --git a/services/spd/tlkd/tlkd_main.c b/services/spd/tlkd/tlkd_main.c
index 32ae8ec..ecac435 100644
--- a/services/spd/tlkd/tlkd_main.c
+++ b/services/spd/tlkd/tlkd_main.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -271,6 +272,9 @@
case TLK_TA_LAUNCH_OP:
case TLK_TA_SEND_EVENT:
case TLK_RESUME_FID:
+ case TLK_SET_BL_VERSION:
+ case TLK_LOCK_BL_INTERFACE:
+ case TLK_BL_RPMB_SERVICE:
if (!ns)
SMC_RET1(handle, SMC_UNK);
@@ -429,7 +433,6 @@
*/
case TLK_SUSPEND_DONE:
case TLK_RESUME_DONE:
- case TLK_SYSTEM_OFF_DONE:
if (ns)
SMC_RET1(handle, SMC_UNK);
diff --git a/services/spd/tlkd/tlkd_pm.c b/services/spd/tlkd/tlkd_pm.c
index 7d1959b..ed5bf77 100644
--- a/services/spd/tlkd/tlkd_pm.c
+++ b/services/spd/tlkd/tlkd_pm.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -98,29 +99,6 @@
}
/*******************************************************************************
- * System is about to be reset. Inform the SP to allow any book-keeping
- ******************************************************************************/
-static void system_off_handler(void)
-{
- int cpu = read_mpidr() & MPIDR_CPU_MASK;
- gp_regs_t *gp_regs;
-
- /* TLK runs only on CPU0 */
- if (cpu != 0)
- return;
-
- /* pass system off/reset events to TLK */
- gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx);
- write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_OFF);
-
- /*
- * Enter the SP. We do not care about the return value because we
- * must continue with the shutdown anyway.
- */
- (void)tlkd_synchronous_sp_entry(&tlk_ctx);
-}
-
-/*******************************************************************************
* Structure populated by the Dispatcher to be given a chance to perform any
* bookkeeping before PSCI executes a power mgmt. operation.
******************************************************************************/
@@ -128,6 +106,4 @@
.svc_migrate_info = cpu_migrate_info,
.svc_suspend = cpu_suspend_handler,
.svc_suspend_finish = cpu_resume_handler,
- .svc_system_off = system_off_handler,
- .svc_system_reset = system_off_handler
};
diff --git a/services/spd/trusty/trusty.c b/services/spd/trusty/trusty.c
index ba2f4a6..b10da76 100644
--- a/services/spd/trusty/trusty.c
+++ b/services/spd/trusty/trusty.c
@@ -413,7 +413,7 @@
/* Get trusty's entry point info */
ep_info = bl31_plat_get_next_image_ep_info(SECURE);
if (ep_info == NULL) {
- INFO("Trusty image missing.\n");
+ VERBOSE("Trusty image missing.\n");
return -1;
}
@@ -466,7 +466,7 @@
trusty_fiq_handler,
flags);
if (ret != 0) {
- ERROR("trusty: failed to register fiq handler, ret = %d\n", ret);
+ VERBOSE("trusty: failed to register fiq handler, ret = %d\n", ret);
}
if (aarch32) {