Tegra194: smmu: ISO support
The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not. This patch implements this encoding and returns
the proper number of SMMU instances.
Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe
Signed-off-by: Steven Kao <skao@nvidia.com>
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 9b6e18e..a9b7271 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -42,10 +42,13 @@
/*******************************************************************************
* Tegra Miscellanous register constants
******************************************************************************/
-#define TEGRA_MISC_BASE 0x00100000
-#define HARDWARE_REVISION_OFFSET 0x4
+#define TEGRA_MISC_BASE 0x00100000U
-#define MISCREG_PFCFG 0x200C
+#define HARDWARE_REVISION_OFFSET 0x4U
+#define MISCREG_EMU_REVID 0x3160U
+#define BOARD_MASK_BITS 0xFFU
+#define BOARD_SHIFT_BITS 24U
+#define MISCREG_PFCFG 0x200CU
/*******************************************************************************
* Tegra TSA Controller constants
diff --git a/plat/nvidia/tegra/soc/t194/plat_smmu.c b/plat/nvidia/tegra/soc/t194/plat_smmu.c
index 2b82f24..64e605b 100644
--- a/plat/nvidia/tegra/soc/t194/plat_smmu.c
+++ b/plat/nvidia/tegra/soc/t194/plat_smmu.c
@@ -9,6 +9,15 @@
#include <smmu.h>
#include <tegra_def.h>
+#define BOARD_SYSTEM_FPGA_BASE U(1)
+#define BASE_CONFIG_SMMU_DEVICES U(2)
+#define MAX_NUM_SMMU_DEVICES U(3)
+
+static uint32_t tegra_misc_read_32(uint32_t off)
+{
+ return mmio_read_32(TEGRA_MISC_BASE + off);
+}
+
/*******************************************************************************
* Array to hold SMMU context for Tegra186
******************************************************************************/
@@ -411,3 +420,19 @@
return tegra194_smmu_context;
}
+
+/*******************************************************************************
+ * Handler to return the support SMMU devices number
+ ******************************************************************************/
+uint32_t plat_get_num_smmu_devices(void)
+{
+ uint32_t ret_num = MAX_NUM_SMMU_DEVICES;
+ uint32_t board_revid = ((tegra_misc_read_32(MISCREG_EMU_REVID) >> \
+ BOARD_SHIFT_BITS) && BOARD_MASK_BITS);
+
+ if (board_revid == BOARD_SYSTEM_FPGA_BASE) {
+ ret_num = BASE_CONFIG_SMMU_DEVICES;
+ }
+
+ return ret_num;
+}
diff --git a/plat/nvidia/tegra/soc/t194/platform_t194.mk b/plat/nvidia/tegra/soc/t194/platform_t194.mk
index 95c967f..3f624dd 100644
--- a/plat/nvidia/tegra/soc/t194/platform_t194.mk
+++ b/plat/nvidia/tegra/soc/t194/platform_t194.mk
@@ -23,9 +23,6 @@
ENABLE_SMMU_DEVICE := 1
$(eval $(call add_define,ENABLE_SMMU_DEVICE))
-NUM_SMMU_DEVICES := 3
-$(eval $(call add_define,NUM_SMMU_DEVICES))
-
RESET_TO_BL31 := 1
PROGRAMMABLE_RESET_ADDRESS := 1