diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index d1bf0d3..bf04558 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -523,11 +523,27 @@
 
 For Neoverse V2, the following errata build flags are defined :
 
+-  ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2
+   CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still
+   open.
+
 -  ``ERRATA_V2_2719103``: This applies errata 2719103 workaround to Neoverse-V2
    CPU, this affects system configurations that do not use and ARM interconnect
    IP. This needs to be enabled for revisions r0p0 and r0p1. It has been fixed
    in r0p2.
 
+-  ``ERRATA_V2_2719105``: This applies errata 2719105 workaround to Neoverse-V2
+   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
+   r0p2.
+
+-  ``ERRATA_V2_2743011``: This applies errata 2743011 workaround to Neoverse-V2
+   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
+   r0p2.
+
+-  ``ERRATA_V2_2779510``: This applies errata 2779510 workaround to Neoverse-V2
+   CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
+   r0p2.
+
 -  ``ERRATA_V2_2801372``: This applies errata 2801372 workaround to Neoverse-V2
    CPU, this affects all configurations. This needs to be enabled for revisions
    r0p0 and r0p1. It has been fixed in r0p2.
diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c
index b510c8f..c96fa04 100644
--- a/drivers/st/ddr/stm32mp1_ram.c
+++ b/drivers/st/ddr/stm32mp1_ram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2023, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -56,7 +56,8 @@
 	int ret;
 	struct stm32mp_ddr_config config;
 	int node;
-	uint32_t uret;
+	uintptr_t uret;
+	size_t retsize;
 	void *fdt;
 
 	const struct stm32mp_ddr_param param[] = {
@@ -106,26 +107,28 @@
 	}
 
 	uret = stm32mp_ddr_test_data_bus();
-	if (uret != 0U) {
-		ERROR("DDR data bus test: can't access memory @ 0x%x\n",
+	if (uret != 0UL) {
+		ERROR("DDR data bus test: can't access memory @ 0x%lx\n",
 		      uret);
 		panic();
 	}
 
 	uret = stm32mp_ddr_test_addr_bus(config.info.size);
-	if (uret != 0U) {
-		ERROR("DDR addr bus test: can't access memory @ 0x%x\n",
+	if (uret != 0UL) {
+		ERROR("DDR addr bus test: can't access memory @ 0x%lx\n",
 		      uret);
 		panic();
 	}
 
-	uret = stm32mp_ddr_check_size();
-	if (uret < config.info.size) {
-		ERROR("DDR size: 0x%x does not match DT config: 0x%x\n",
-		      uret, config.info.size);
+	retsize = stm32mp_ddr_check_size();
+	if (retsize < config.info.size) {
+		ERROR("DDR size: 0x%zx does not match DT config: 0x%zx\n",
+		      retsize, config.info.size);
 		panic();
 	}
 
+	INFO("Memory size = 0x%zx (%zu MB)\n", retsize, retsize / (1024U * 1024U));
+
 	if (stm32mp_unmap_ddr() != 0) {
 		panic();
 	}
diff --git a/drivers/st/ddr/stm32mp_ddr_test.c b/drivers/st/ddr/stm32mp_ddr_test.c
index 6733cc6..0f6aff1 100644
--- a/drivers/st/ddr/stm32mp_ddr_test.c
+++ b/drivers/st/ddr/stm32mp_ddr_test.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,19 +18,19 @@
  * Note that the previous content is restored after test.
  * Returns 0 if success, and address value else.
  ******************************************************************************/
-uint32_t stm32mp_ddr_test_rw_access(void)
+uintptr_t stm32mp_ddr_test_rw_access(void)
 {
 	uint32_t saved_value = mmio_read_32(STM32MP_DDR_BASE);
 
 	mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN);
 
 	if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
-		return (uint32_t)STM32MP_DDR_BASE;
+		return STM32MP_DDR_BASE;
 	}
 
 	mmio_write_32(STM32MP_DDR_BASE, saved_value);
 
-	return 0U;
+	return 0UL;
 }
 
 /*******************************************************************************
@@ -41,7 +41,7 @@
  * File: memtest.c - This source code belongs to Public Domain.
  * Returns 0 if success, and address value else.
  ******************************************************************************/
-uint32_t stm32mp_ddr_test_data_bus(void)
+uintptr_t stm32mp_ddr_test_data_bus(void)
 {
 	uint32_t pattern;
 
@@ -49,11 +49,11 @@
 		mmio_write_32(STM32MP_DDR_BASE, pattern);
 
 		if (mmio_read_32(STM32MP_DDR_BASE) != pattern) {
-			return (uint32_t)STM32MP_DDR_BASE;
+			return STM32MP_DDR_BASE;
 		}
 	}
 
-	return 0;
+	return 0UL;
 }
 
 /*******************************************************************************
@@ -65,38 +65,34 @@
  * size: size in bytes of the DDR memory device.
  * Returns 0 if success, and address value else.
  ******************************************************************************/
-uint32_t stm32mp_ddr_test_addr_bus(uint64_t size)
+uintptr_t stm32mp_ddr_test_addr_bus(size_t size)
 {
-	uint64_t addressmask = size - 1U;
-	uint64_t offset;
-	uint64_t testoffset = 0U;
+	size_t addressmask = size - 1U;
+	size_t offset;
+	size_t testoffset = 0U;
 
 	/* Write the default pattern at each of the power-of-two offsets. */
 	for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
 	     offset <<= 1U) {
-		mmio_write_32(STM32MP_DDR_BASE + (uint32_t)offset,
-			      DDR_PATTERN);
+		mmio_write_32(STM32MP_DDR_BASE + offset, DDR_PATTERN);
 	}
 
 	/* Check for address bits stuck high. */
-	mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
-		      DDR_ANTIPATTERN);
+	mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN);
 
 	for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
 	     offset <<= 1U) {
-		if (mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) !=
-		    DDR_PATTERN) {
-			return (uint32_t)(STM32MP_DDR_BASE + offset);
+		if (mmio_read_32(STM32MP_DDR_BASE + offset) != DDR_PATTERN) {
+			return STM32MP_DDR_BASE + offset;
 		}
 	}
 
-	mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN);
+	mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_PATTERN);
 
 	/* Check for address bits stuck low or shorted. */
 	for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U;
 	     testoffset <<= 1U) {
-		mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
-			      DDR_ANTIPATTERN);
+		mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_ANTIPATTERN);
 
 		if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
 			return STM32MP_DDR_BASE;
@@ -104,18 +100,16 @@
 
 		for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
 		     offset <<= 1) {
-			if ((mmio_read_32(STM32MP_DDR_BASE +
-					  (uint32_t)offset) != DDR_PATTERN) &&
+			if ((mmio_read_32(STM32MP_DDR_BASE + offset) != DDR_PATTERN) &&
 			    (offset != testoffset)) {
-				return (uint32_t)(STM32MP_DDR_BASE + offset);
+				return STM32MP_DDR_BASE + offset;
 			}
 		}
 
-		mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
-			      DDR_PATTERN);
+		mmio_write_32(STM32MP_DDR_BASE + testoffset, DDR_PATTERN);
 	}
 
-	return 0U;
+	return 0UL;
 }
 
 /*******************************************************************************
@@ -125,9 +119,9 @@
  * restore its content.
  * Returns DDR computed size.
  ******************************************************************************/
-uint32_t stm32mp_ddr_check_size(void)
+size_t stm32mp_ddr_check_size(void)
 {
-	uint32_t offset = sizeof(uint32_t);
+	size_t offset = sizeof(uint32_t);
 
 	mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN);
 
@@ -142,7 +136,5 @@
 		offset <<= 1U;
 	}
 
-	INFO("Memory size = 0x%x (%u MB)\n", offset, offset / (1024U * 1024U));
-
 	return offset;
 }
diff --git a/drivers/st/ddr/stm32mp_ram.c b/drivers/st/ddr/stm32mp_ram.c
index 0804568..28dc17d 100644
--- a/drivers/st/ddr/stm32mp_ram.c
+++ b/drivers/st/ddr/stm32mp_ram.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,8 +23,8 @@
 		VERBOSE("%s: no st,mem-speed\n", __func__);
 		return -EINVAL;
 	}
-	ret = fdt_read_uint32(fdt, node, "st,mem-size", &info->size);
-	if (ret < 0) {
+	info->size = dt_get_ddr_size();
+	if (info->size == 0U) {
 		VERBOSE("%s: no st,mem-size\n", __func__);
 		return -EINVAL;
 	}
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index 5ba5eb0..19f894f 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -609,7 +609,7 @@
 	       UTRIACR_IATOVAL(0xFF);
 	mmio_write_32(ufs_params.reg_base + UTRIACR, data);
 	/* send request */
-	mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1 << slot);
+	mmio_setbits_32(ufs_params.reg_base + UTRLDBR, 1U << slot);
 }
 
 static int ufs_check_resp(utp_utrd_t *utrd, int trans_type, unsigned int timeout_ms)
diff --git a/include/drivers/st/stm32mp_ddr.h b/include/drivers/st/stm32mp_ddr.h
index 1efca42..4535e3c 100644
--- a/include/drivers/st/stm32mp_ddr.h
+++ b/include/drivers/st/stm32mp_ddr.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -53,8 +53,8 @@
 
 struct stm32mp_ddr_info {
 	const char *name;
-	uint32_t speed; /* in kHZ */
-	uint32_t size;  /* Memory size in byte = col * row * width */
+	uint32_t speed; /* in kHz */
+	size_t size;    /* Memory size in byte = col * row * width */
 };
 
 #define TIMEOUT_US_1S	1000000U
diff --git a/include/drivers/st/stm32mp_ddr_test.h b/include/drivers/st/stm32mp_ddr_test.h
index 34e522a..cef5b48 100644
--- a/include/drivers/st/stm32mp_ddr_test.h
+++ b/include/drivers/st/stm32mp_ddr_test.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2022, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2022-2023, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -9,9 +9,9 @@
 
 #include <stdint.h>
 
-uint32_t stm32mp_ddr_test_rw_access(void);
-uint32_t stm32mp_ddr_test_data_bus(void);
-uint32_t stm32mp_ddr_test_addr_bus(uint64_t size);
-uint32_t stm32mp_ddr_check_size(void);
+uintptr_t stm32mp_ddr_test_rw_access(void);
+uintptr_t stm32mp_ddr_test_data_bus(void);
+uintptr_t stm32mp_ddr_test_addr_bus(size_t size);
+size_t stm32mp_ddr_check_size(void);
 
 #endif /* STM32MP_DDR_TEST_H */
diff --git a/include/lib/cpus/aarch64/neoverse_v2.h b/include/lib/cpus/aarch64/neoverse_v2.h
index efb960e..68c1558 100644
--- a/include/lib/cpus/aarch64/neoverse_v2.h
+++ b/include/lib/cpus/aarch64/neoverse_v2.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,4 +23,31 @@
 #define NEOVERSE_V2_CPUPWRCTLR_EL1			S3_0_C15_C2_7
 #define NEOVERSE_V2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT	U(1)
 
+/*******************************************************************************
+ * CPU Extended Control register 2 specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_V2_CPUECTLR2_EL1			S3_0_C15_C1_5
+#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV		ULL(9)
+#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB		U(11)
+#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH		U(4)
+
+/*******************************************************************************
+ * CPU Auxiliary Control register 2 specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_V2_CPUACTLR2_EL1			S3_0_C15_C1_1
+#define NEOVERSE_V2_CPUACTLR2_EL1_BIT_0			(ULL(1) << 0)
+
+/*******************************************************************************
+ * CPU Auxiliary Control register 3 specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_V2_CPUACTLR3_EL1			S3_0_C15_C1_2
+#define NEOVERSE_V2_CPUACTLR3_EL1_BIT_47		(ULL(1) << 47)
+
+/*******************************************************************************
+ * CPU Auxiliary Control register 5 specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_V2_CPUACTLR5_EL1			S3_0_C15_C8_0
+#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_56		(ULL(1) << 56)
+#define NEOVERSE_V2_CPUACTLR5_EL1_BIT_55		(ULL(1) << 55)
+
 #endif /* NEOVERSE_V2_H */
diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S
index 9f729c1..94f6465 100644
--- a/lib/cpus/aarch64/cortex_a78_ae.S
+++ b/lib/cpus/aarch64/cortex_a78_ae.S
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
- * Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2021-2023, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,7 +23,7 @@
 #endif /* WORKAROUND_CVE_2022_23960 */
 
 workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500
-	sysreg_bit_clear CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
+	sysreg_bit_set CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
 workaround_reset_end cortex_a78_ae, ERRATUM(1941500)
 
 check_erratum_ls cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 1)
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index 36ae4de..bfd088d 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -22,6 +22,32 @@
 #error "Neoverse V2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
 #endif
 
+workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132
+	sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
+		NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH
+workaround_reset_end neoverse_v2, ERRATUM(2331132)
+
+check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2)
+
+workaround_reset_start neoverse_v2, ERRATUM(2719105), ERRATA_V2_2719105
+	sysreg_bit_set NEOVERSE_V2_CPUACTLR2_EL1, NEOVERSE_V2_CPUACTLR2_EL1_BIT_0
+workaround_reset_end neoverse_v2, ERRATUM(2719105)
+
+check_erratum_ls neoverse_v2, ERRATUM(2719105), CPU_REV(0, 1)
+
+workaround_reset_start neoverse_v2, ERRATUM(2743011), ERRATA_V2_2743011
+	sysreg_bit_set NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_55
+	sysreg_bit_clear NEOVERSE_V2_CPUACTLR5_EL1, NEOVERSE_V2_CPUACTLR5_EL1_BIT_56
+workaround_reset_end neoverse_v2, ERRATUM(2743011)
+
+check_erratum_ls neoverse_v2, ERRATUM(2743011), CPU_REV(0, 1)
+
+workaround_reset_start neoverse_v2, ERRATUM(2779510), ERRATA_V2_2779510
+	sysreg_bit_set NEOVERSE_V2_CPUACTLR3_EL1, NEOVERSE_V2_CPUACTLR3_EL1_BIT_47
+workaround_reset_end neoverse_v2, ERRATUM(2779510)
+
+check_erratum_ls neoverse_v2, ERRATUM(2779510), CPU_REV(0, 1)
+
 workaround_runtime_start neoverse_v2, ERRATUM(2801372), ERRATA_V2_2801372
 	/* dsb before isb of power down sequence */
 	dsb	sy
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 0d8f4d4..77cc41e 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -794,10 +794,26 @@
 # Cortex-A510 cpu and is fixed in r1p3.
 CPU_FLAG_LIST += ERRATA_A510_2684597
 
+# Flag to apply erratum 2331132 workaround during reset. This erratum applies
+# to revisions r0p0, r0p1 and r0p2. It is still open.
+CPU_FLAG_LIST += ERRATA_V2_2331132
+
 # Flag to apply erratum 2719103 workaround for non-arm interconnect ip. This
 # erratum applies to revisions r0p0, rop1. Fixed in r0p2.
 CPU_FLAG_LIST += ERRATA_V2_2719103
 
+# Flag to apply erratum 2719105 workaround during reset. This erratum applies
+# to revisions r0p0 and r0p1. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_V2_2719105
+
+# Flag to apply erratum 2743011 workaround during reset. This erratum applies
+# to revisions r0p0 and r0p1. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_V2_2743011
+
+# Flag to apply erratum 2779510 workaround during reset. This erratum applies
+# to revisions r0p0 and r0p1. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_V2_2779510
+
 # Flag to apply erratum 2801372 workaround for all configurations.
 # This erratum applies to revisions r0p0, r0p1. Fixed in r0p2.
 CPU_FLAG_LIST += ERRATA_V2_2801372
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 3a56120..ca66396 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -401,10 +401,14 @@
 {
 	.cpu_partnumber = NEOVERSE_V2_MIDR,
 	.cpu_errata_list = {
-		[0] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
+		[0] = {2331132, 0x00, 0x02, ERRATA_V2_2331132},
+		[1] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
 			ERRATA_NON_ARM_INTERCONNECT},
-		[1] = {2801372, 0x00, 0x01, ERRATA_V2_2801372},
-		[2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+		[2] = {2719105, 0x00, 0x01, ERRATA_V2_2719105},
+		[3] = {2743011, 0x00, 0x01, ERRATA_V2_2743011},
+		[4] = {2779510, 0x00, 0x01, ERRATA_V2_2779510},
+		[5] = {2801372, 0x00, 0x01, ERRATA_V2_2801372},
+		[6 ... ERRATA_LIST_END] = UNDEF_ERRATA,
 	}
 },
 #endif /* NEOVERSE_V2_H_INC */