docs(stm32mp2): introduce new STM32MP21 family
STM32MP21 is a derivative from STM32MP25. It comes in 3 different lines:
- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
CSI - LTDC
- STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
- STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
Change-Id: Ie3db430bedd86c3b444bec647792be24b20a0cba
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
diff --git a/docs/plat/st/stm32mp2.rst b/docs/plat/st/stm32mp2.rst
index 87bb6a5..d63fc50 100644
--- a/docs/plat/st/stm32mp2.rst
+++ b/docs/plat/st/stm32mp2.rst
@@ -12,6 +12,27 @@
STM32MP2 Versions
-----------------
+Here are the variants for STM32MP2:
+- STM32MP21
+- STM32MP25
+
+STM32MP21 Versions
+~~~~~~~~~~~~~~~~~~
+The STM32MP21 series is available in 3 different lines which are pin-to-pin compatible:
+
+- STM32MP215: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD - CSI - LTDC
+- STM32MP213: Single Cortex-A35 + Cortex-M33 - 2x Ethernet - 2x CAN FD
+- STM32MP211: Single Cortex-A35 + Cortex-M33 - 1x Ethernet
+
+Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
+
+- A Basic + Cortex-A35 @ 1.2GHz
+- C Secure Boot + HW Crypto + Cortex-A35 @ 1.2GHz
+- D Basic + Cortex-A35 @ 1.5GHz
+- F Secure Boot + HW Crypto + Cortex-A35 @ 1.5GHz
+
+STM32MP25 Versions
+~~~~~~~~~~~~~~~~~~
The STM32MP25 series is available in 4 different lines which are pin-to-pin compatible:
- STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 - 3D GPU – AI / NN - LVDS
@@ -70,6 +91,8 @@
- | ``STM32MP_DDR_FIP_IO_STORAGE``: to store DDR firmware in FIP.
| Default: 1
+- | ``STM32MP21``: to select STM32MP21 variant configuration.
+ | Default: 0
- | ``STM32MP25``: to select STM32MP25 variant configuration.
| Default: 1
@@ -154,4 +177,4 @@
.. _STM32MP2 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP25_microprocessor#Part_number_codification
.. _STMicroelectronics DDR PHY github: https://github.com/STMicroelectronics/stm32-ddr-phy-binary
-*Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved*
+*Copyright (c) 2023-2025, STMicroelectronics - All Rights Reserved*
diff --git a/plat/st/stm32mp2/platform.mk b/plat/st/stm32mp2/platform.mk
index 06298a4..653b9d9 100644
--- a/plat/st/stm32mp2/platform.mk
+++ b/plat/st/stm32mp2/platform.mk
@@ -30,11 +30,29 @@
# Default Device tree
DTB_FILE_NAME ?= stm32mp257f-ev1.dtb
+STM32MP21 ?= 0
+STM32MP25 ?= 0
+
+ifneq ($(findstring stm32mp21,$(DTB_FILE_NAME)),)
+STM32MP21 := 1
+endif
+ifneq ($(findstring stm32mp25,$(DTB_FILE_NAME)),)
STM32MP25 := 1
+endif
+ifneq ($(filter 1,$(STM32MP21) $(STM32MP25)), 1)
+$(warning STM32MP21=$(STM32MP21))
+$(warning STM32MP25=$(STM32MP25))
+$(warning DTB_FILE_NAME=$(DTB_FILE_NAME))
+$(error Cannot enable 2 flags STM32MP2X)
+endif
-# STM32 image header version v2.2
+# STM32 image header version v2.2 or v2.3 for STM32MP21
STM32_HEADER_VERSION_MAJOR := 2
+ifeq ($(STM32MP21),1)
+STM32_HEADER_VERSION_MINOR := 3
+else
STM32_HEADER_VERSION_MINOR := 2
+endif
# Set load address for serial boot devices
DWL_BUFFER_BASE ?= 0x87000000
@@ -110,6 +128,7 @@
STM32MP_DDR3_TYPE \
STM32MP_DDR4_TYPE \
STM32MP_LPDDR4_TYPE \
+ STM32MP21 \
STM32MP25 \
STM32MP_BL33_EL1 \
)))
@@ -133,6 +152,7 @@
STM32MP_DDR3_TYPE \
STM32MP_DDR4_TYPE \
STM32MP_LPDDR4_TYPE \
+ STM32MP21 \
STM32MP25 \
STM32MP_BL33_EL1 \
)))