drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.
This will allow non-secure word drivers access some white-listed
registers related to e.g.: Sample at reset, efuses, SoC type and
revision ID accesses.
Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
diff --git a/drivers/marvell/secure_dfx_access/dfx.h b/drivers/marvell/secure_dfx_access/dfx.h
index 52efbf9..88c4de8 100644
--- a/drivers/marvell/secure_dfx_access/dfx.h
+++ b/drivers/marvell/secure_dfx_access/dfx.h
@@ -13,5 +13,10 @@
#define MV_SIP_DFX_THERMAL_THRESH 5
#define MV_SIP_DFX_THERMAL_SEL_CHANNEL 6
+#define MV_SIP_DFX_SREAD 20
+#define MV_SIP_DFX_SWRITE 21
+
int mvebu_dfx_thermal_handle(u_register_t func, u_register_t *read,
u_register_t x2, u_register_t x3);
+int mvebu_dfx_misc_handle(u_register_t func, u_register_t *read,
+ u_register_t addr, u_register_t val);
diff --git a/drivers/marvell/secure_dfx_access/misc_dfx.c b/drivers/marvell/secure_dfx_access/misc_dfx.c
new file mode 100644
index 0000000..c5512ab
--- /dev/null
+++ b/drivers/marvell/secure_dfx_access/misc_dfx.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include "dfx.h"
+#include <mvebu_def.h>
+#include <mvebu.h>
+#include <errno.h>
+
+/* #define DEBUG_DFX */
+#ifdef DEBUG_DFX
+#define debug(format...) NOTICE(format)
+#else
+#define debug(format, arg...)
+#endif
+
+#define SAR_BASE (MVEBU_REGS_BASE + 0x6F8200)
+#define SAR_SIZE 0x4
+#define AP_DEV_ID_STATUS_REG (MVEBU_REGS_BASE + 0x6F8240)
+#define JTAG_DEV_ID_STATUS_REG (MVEBU_REGS_BASE + 0x6F8244)
+#define EFUSE_CTRL (MVEBU_REGS_BASE + 0x6F8008)
+#define EFUSE_LD_BASE (MVEBU_REGS_BASE + 0x6F8F00)
+#define EFUSE_LD_SIZE 0x1C
+#define EFUSE_HD_BASE (MVEBU_REGS_BASE + 0x6F9000)
+#define EFUSE_HD_SIZE 0x3F8
+
+static _Bool is_valid(u_register_t addr)
+{
+ switch (addr) {
+ case AP_DEV_ID_STATUS_REG:
+ case JTAG_DEV_ID_STATUS_REG:
+ case SAR_BASE ... (SAR_BASE + SAR_SIZE):
+ case EFUSE_LD_BASE ... (EFUSE_LD_BASE + EFUSE_LD_SIZE):
+ case EFUSE_HD_BASE ... (EFUSE_HD_BASE + EFUSE_HD_SIZE):
+ case EFUSE_CTRL:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static int armada_dfx_sread(u_register_t *read, u_register_t addr)
+{
+ if (!is_valid(addr))
+ return -EINVAL;
+
+ *read = mmio_read_32(addr);
+
+ return 0;
+}
+
+static int armada_dfx_swrite(u_register_t addr, u_register_t val)
+{
+ if (!is_valid(addr))
+ return -EINVAL;
+
+ mmio_write_32(addr, val);
+
+ return 0;
+}
+
+int mvebu_dfx_misc_handle(u_register_t func, u_register_t *read,
+ u_register_t addr, u_register_t val)
+{
+ debug_enter();
+
+ debug("func %ld, addr 0x%lx, val 0x%lx\n", func, addr, val);
+
+ switch (func) {
+ case MV_SIP_DFX_SREAD:
+ return armada_dfx_sread(read, addr);
+ case MV_SIP_DFX_SWRITE:
+ return armada_dfx_swrite(addr, val);
+ default:
+ ERROR("unsupported dfx misc sub-func\n");
+ return -EINVAL;
+ }
+
+ debug_exit();
+
+ return 0;
+}
diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk
index dcb64ce..3acc3b4 100644
--- a/plat/marvell/armada/a8k/common/a8k_common.mk
+++ b/plat/marvell/armada/a8k/common/a8k_common.mk
@@ -116,6 +116,7 @@
$(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \
$(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c \
$(MARVELL_DRV_BASE)/secure_dfx_access/armada_thermal.c \
+ $(MARVELL_DRV_BASE)/secure_dfx_access/misc_dfx.c \
$(MARVELL_DRV_BASE)/ddr_phy_access.c \
drivers/rambus/trng_ip_76.c
diff --git a/plat/marvell/armada/common/mrvl_sip_svc.c b/plat/marvell/armada/common/mrvl_sip_svc.c
index ebc7632..48172b2 100644
--- a/plat/marvell/armada/common/mrvl_sip_svc.c
+++ b/plat/marvell/armada/common/mrvl_sip_svc.c
@@ -147,6 +147,11 @@
ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3);
SMC_RET2(handle, ret, read);
}
+ if (x1 >= MV_SIP_DFX_SREAD && x1 <= MV_SIP_DFX_SWRITE) {
+ ret = mvebu_dfx_misc_handle(x1, &read, x2, x3);
+ SMC_RET2(handle, ret, read);
+ }
+
SMC_RET1(handle, SMC_UNK);
case MV_SIP_DDR_PHY_WRITE:
ret = mvebu_ddr_phy_write(x1, x2);