Merge changes from topic "stm32mp13" into integration
* changes:
feat(stm32mp1): select platform compilation either by flag or DT
feat(stm32mp1-fdts): add support for STM32MP13 DK board
feat(stm32mp1-fdts): add DDR support for STM32MP13
feat(stm32mp1-fdts): add st-io_policies node for STM32MP13
feat(stm32mp1): updates for STM32MP13 device tree compilation
feat(stm32mp1-fdts): add DT files for STM32MP13
feat(dt-bindings): add TZC400 bindings for STM32MP13
feat(stm32mp1): add "Boot mode" management for STM32MP13
feat(stm32mp1): manage HSLV on STM32MP13
feat(stm32mp1): add sdmmc compatible in platform define
feat(st-sdmmc2): allow compatible to be defined in platform code
feat(stm32mp1): update IO compensation on STM32MP13
feat(stm32mp1): call pmic_voltages_init() in platform init
feat(st-pmic): add pmic_voltages_init() function
feat(stm32mp1): update CFG0 OTP for STM32MP13
feat(stm32mp1): usb descriptor update for STM32MP13
feat(st-clock): add clock driver for STM32MP13
feat(dt-bindings): add bindings for STM32MP13
feat(stm32mp1): get CPU info from SYSCFG on STM32MP13
feat(stm32mp1): use only one filter for TZC400 on STM32MP13
feat(stm32mp1): add a second fixed regulator
feat(stm32mp1): adaptations for STM32MP13 image header
feat(stm32mp1): update boot API for header v2.0
feat(stm32mp1): update IP addresses for STM32MP13
feat(stm32mp1): add part numbers for STM32MP13
feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13
feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13
feat(stm32mp1): stm32mp_is_single_core() for STM32MP13
feat(stm32mp1): remove unsupported features on STM32MP13
feat(stm32mp1): update memory mapping for STM32MP13
feat(stm32mp1): introduce new flag for STM32MP13
feat(st): update stm32image tool for header v2
diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index 5147cf2..adb9603 100644
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -68,8 +68,9 @@
- DEBUG
Default is without debug information (=0). in order to enable it use ``DEBUG=1``.
- Must be disabled when building UART recovery images due to current console driver
- implementation that is not compatible with Xmodem protocol used for boot image download.
+ Can be enabled also when building UART recovery images, there is no issue with it.
+
+ Production TF-A images should be built without this debug option!
- LOG_LEVEL
diff --git a/drivers/ufs/ufs.c b/drivers/ufs/ufs.c
index 3d6d99f..3c27aff 100644
--- a/drivers/ufs/ufs.c
+++ b/drivers/ufs/ufs.c
@@ -490,6 +490,21 @@
return 0;
}
+static void ufs_send_cmd(utp_utrd_t *utrd, uint8_t cmd_op, uint8_t lun, int lba, uintptr_t buf,
+ size_t length)
+{
+ int result;
+
+ get_utrd(utrd);
+
+ result = ufs_prepare_cmd(utrd, cmd_op, lun, lba, buf, length);
+ assert(result == 0);
+ ufs_send_request(utrd->task_tag);
+ result = ufs_check_resp(utrd, RESPONSE_UPIU);
+ assert(result == 0);
+ (void)result;
+}
+
#ifdef UFS_RESP_DEBUG
static void dump_upiu(utp_utrd_t *utrd)
{
@@ -540,14 +555,7 @@
static void ufs_verify_ready(void)
{
utp_utrd_t utrd;
- int result;
-
- get_utrd(&utrd);
- ufs_prepare_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0);
- ufs_send_request(utrd.task_tag);
- result = ufs_check_resp(&utrd, RESPONSE_UPIU);
- assert(result == 0);
- (void)result;
+ ufs_send_cmd(&utrd, CDBCMD_TEST_UNIT_READY, 0, 0, 0, 0);
}
static void ufs_query(uint8_t op, uint8_t idn, uint8_t index, uint8_t sel,
@@ -663,12 +671,8 @@
memset((void *)buf, 0, CACHE_WRITEBACK_GRANULE);
flush_dcache_range(buf, CACHE_WRITEBACK_GRANULE);
do {
- get_utrd(&utrd);
- ufs_prepare_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0,
- buf, READ_CAPACITY_LENGTH);
- ufs_send_request(utrd.task_tag);
- result = ufs_check_resp(&utrd, RESPONSE_UPIU);
- assert(result == 0);
+ ufs_send_cmd(&utrd, CDBCMD_READ_CAPACITY_10, lun, 0,
+ buf, READ_CAPACITY_LENGTH);
#ifdef UFS_RESP_DEBUG
dump_upiu(&utrd);
#endif
@@ -702,11 +706,7 @@
(ufs_params.desc_base != 0) &&
(ufs_params.desc_size >= UFS_DESC_SIZE));
- get_utrd(&utrd);
- ufs_prepare_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size);
- ufs_send_request(utrd.task_tag);
- result = ufs_check_resp(&utrd, RESPONSE_UPIU);
- assert(result == 0);
+ ufs_send_cmd(&utrd, CDBCMD_READ_10, lun, lba, buf, size);
#ifdef UFS_RESP_DEBUG
dump_upiu(&utrd);
#endif
@@ -725,11 +725,7 @@
(ufs_params.desc_base != 0) &&
(ufs_params.desc_size >= UFS_DESC_SIZE));
- get_utrd(&utrd);
- ufs_prepare_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size);
- ufs_send_request(utrd.task_tag);
- result = ufs_check_resp(&utrd, RESPONSE_UPIU);
- assert(result == 0);
+ ufs_send_cmd(&utrd, CDBCMD_WRITE_10, lun, lba, buf, size);
#ifdef UFS_RESP_DEBUG
dump_upiu(&utrd);
#endif
@@ -743,11 +739,6 @@
unsigned int blk_num, blk_size;
int i;
- /* 0 means 1 slot */
- nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1;
- if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE))
- nutrs = ufs_params.desc_size / UFS_DESC_SIZE;
-
ufs_verify_init();
ufs_verify_ready();
@@ -792,6 +783,13 @@
memcpy(&ufs_params, params, sizeof(ufs_params_t));
+ /* 0 means 1 slot */
+ nutrs = (mmio_read_32(ufs_params.reg_base + CAP) & CAP_NUTRS_MASK) + 1;
+ if (nutrs > (ufs_params.desc_size / UFS_DESC_SIZE)) {
+ nutrs = ufs_params.desc_size / UFS_DESC_SIZE;
+ }
+
+
if (ufs_params.flags & UFS_FLAGS_SKIPINIT) {
result = ufshc_dme_get(0x1571, 0, &data);
assert(result == 0);
diff --git a/plat/arm/common/fconf/arm_fconf_sp.c b/plat/arm/common/fconf/arm_fconf_sp.c
index 95e0873..18c83c7 100644
--- a/plat/arm/common/fconf/arm_fconf_sp.c
+++ b/plat/arm/common/fconf/arm_fconf_sp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -30,13 +30,16 @@
union uuid_helper_t uuid_helper;
unsigned int index = 0;
uint32_t val32;
- bool is_plat_owned = false;
const unsigned int sip_start = SP_PKG1_ID;
unsigned int sip_index = sip_start;
+#if defined(ARM_COT_dualroot)
const unsigned int sip_end = sip_start + MAX_SP_IDS / 2;
+ /* Allocating index range for platform SPs */
const unsigned int plat_start = SP_PKG5_ID;
unsigned int plat_index = plat_start;
const unsigned int plat_end = plat_start + MAX_SP_IDS / 2;
+ bool is_plat_owned = false;
+#endif /* ARM_COT_dualroot */
/* As libfdt use void *, we can't avoid this cast */
const void *dtb = (void *)config;
@@ -51,12 +54,18 @@
}
fdt_for_each_subnode(sp_node, dtb, node) {
- if ((index == MAX_SP_IDS) || (sip_index == sip_end)
- || (plat_index == plat_end)) {
+ if (index == MAX_SP_IDS) {
ERROR("FCONF: Reached max number of SPs\n");
return -1;
}
+#if defined(ARM_COT_dualroot)
+ if ((sip_index == sip_end) || (plat_index == plat_end)) {
+ ERROR("FCONF: Reached max number of plat/SiP SPs\n");
+ return -1;
+ }
+#endif /* ARM_COT_dualroot */
+
/* Read UUID */
err = fdtw_read_uuid(dtb, sp_node, "uuid", 16,
(uint8_t *)&uuid_helper);
@@ -96,7 +105,7 @@
/* Owner is an optional field, no need to catch error */
fdtw_read_string(dtb, sp_node, "owner",
arm_sp.owner[index], ARM_SP_OWNER_NAME_LEN);
-#endif
+
/* If owner is empty mark it as SiP owned */
if ((strncmp(arm_sp.owner[index], "SiP",
ARM_SP_OWNER_NAME_LEN) == 0) ||
@@ -121,7 +130,9 @@
policies[plat_index].dev_handle = &fip_dev_handle;
policies[plat_index].check = open_fip;
plat_index++;
- } else {
+ } else
+#endif /* ARM_COT_dualroot */
+ {
sp_mem_params_descs[index].image_id = sip_index;
policies[sip_index].image_spec =
(uintptr_t)&arm_sp.uuids[index];
diff --git a/plat/nxp/common/soc_errata/errata_a050426.c b/plat/nxp/common/soc_errata/errata_a050426.c
index 13a0000..ba4f71f 100644
--- a/plat/nxp/common/soc_errata/errata_a050426.c
+++ b/plat/nxp/common/soc_errata/errata_a050426.c
@@ -1,16 +1,26 @@
/*
- * Copyright 2021 NXP
+ * Copyright 2021-2022 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
+#include <common/debug.h>
#include <mmio.h>
void erratum_a050426(void)
{
uint32_t i, val3, val4;
+ /*
+ * Part of this Errata is implemented in RCW and SCRATCHRW5
+ * register is updated to hold Errata number.
+ * Validate whether RCW has already included required changes
+ */
+ if (mmio_read_32(0x01e00210) != 0x00050426) {
+ ERROR("%s: Invalid RCW : ERR050426 not implemented\n", __func__);
+ }
+
/* Enable BIST to access Internal memory locations */
val3 = mmio_read_32(0x700117E60);
mmio_write_32(0x700117E60, (val3 | 0x80000001));
@@ -63,7 +73,7 @@
mmio_write_32(0x706718000 + (i * 4), 0x55555555);
mmio_write_32(0x706718800 + (i * 4), 0x55555555);
}
- mmio_write_32(0x706b0a000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706b0a000, 0x55555555);
for (i = 0U; i < 4U; i++) {
mmio_write_32(0x706b0e000 + (i * 4), 0x55555555);
@@ -79,7 +89,7 @@
mmio_write_32(0x706b15000 + (i * 4), 0x55555555);
mmio_write_32(0x706b15800 + (i * 4), 0x55555555);
}
- mmio_write_32(0x706e12000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e12000, 0x55555555);
for (i = 0U; i < 4U; i++) {
mmio_write_32(0x706e14000 + (i * 4), 0x55555555);
@@ -147,62 +157,6 @@
mmio_write_32(0x70a209800 + (i * 4), 0x55555555);
}
- /* PEX1 Internal Memory.*/
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70a508000 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70a520000 + (i * 4), 0x55555555);
- mmio_write_32(0x70a528000 + (i * 4), 0x55555555);
- }
-
- /* PEX2 Internal Memory.*/
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70a608000 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70a620000 + (i * 4), 0x55555555);
- mmio_write_32(0x70a628000 + (i * 4), 0x55555555);
- }
-
- /* PEX3 Internal Memory.*/
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70a708000 + (i * 4), 0x55555555);
- mmio_write_32(0x70a728000 + (i * 4), 0x55555555);
- mmio_write_32(0x70a730000 + (i * 4), 0x55555555);
- mmio_write_32(0x70a738000 + (i * 4), 0x55555555);
- mmio_write_32(0x70a748000 + (i * 4), 0x55555555);
- mmio_write_32(0x70a758000 + (i * 4), 0x55555555);
- }
-
- /* PEX4 Internal Memory.*/
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70a808000 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70a820000 + (i * 4), 0x55555555);
- mmio_write_32(0x70a828000 + (i * 4), 0x55555555);
- }
-
- /* PEX5 Internal Memory.*/
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70aa08000 + (i * 4), 0x55555555);
- mmio_write_32(0x70aa28000 + (i * 4), 0x55555555);
- mmio_write_32(0x70aa30000 + (i * 4), 0x55555555);
- mmio_write_32(0x70aa38000 + (i * 4), 0x55555555);
- mmio_write_32(0x70aa48000 + (i * 4), 0x55555555);
- mmio_write_32(0x70aa58000 + (i * 4), 0x55555555);
- }
-
- /* PEX6 Internal Memory.*/
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70ab08000 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70ab20000 + (i * 4), 0x55555555);
- mmio_write_32(0x70ab28000 + (i * 4), 0x55555555);
- }
-
/* QDMA Internal Memory.*/
for (i = 0U; i < 5U; i++) {
mmio_write_32(0x70b008000 + (i * 4), 0x55555555);
@@ -241,174 +195,6 @@
mmio_write_32(0x70b029800 + (i * 4), 0x55555555);
}
- /* lnx1_e1000#0 Internal Memory.*/
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c00a000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00a200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00a400 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00a600 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00a800 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00aa00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00ac00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00ae00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00b000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00b200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00b400 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00b600 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00b800 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00ba00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00bc00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00be00 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c00c000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00c400 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00c800 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00cc00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00d000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00d400 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00d800 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00dc00 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c00e000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c00f000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c012000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c012200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c012400 + (i * 4), 0x55555555);
- mmio_write_32(0x70c012600 + (i * 4), 0x55555555);
- mmio_write_32(0x70c012800 + (i * 4), 0x55555555);
- mmio_write_32(0x70c012a00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c012c00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c012e00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c013000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c013200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c013400 + (i * 4), 0x55555555);
- mmio_write_32(0x70c013600 + (i * 4), 0x55555555);
- mmio_write_32(0x70c013800 + (i * 4), 0x55555555);
- mmio_write_32(0x70c013a00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c013c00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c013e00 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c014000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c014400 + (i * 4), 0x55555555);
- mmio_write_32(0x70c014800 + (i * 4), 0x55555555);
- mmio_write_32(0x70c014c00 + (i * 4), 0x55555555);
- mmio_write_32(0x70c015000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c015400 + (i * 4), 0x55555555);
- mmio_write_32(0x70c015800 + (i * 4), 0x55555555);
- mmio_write_32(0x70c015c00 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c016000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c017000 + (i * 4), 0x55555555);
- }
-
- /* lnx1_xfi Internal Memory.*/
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c108000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c108200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c10a000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c10a400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c10c000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c10c400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c10e000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c10e200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c110000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c110400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c112000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c112400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c114000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c114200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c116000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c116400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c118000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c118400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c11a000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c11a200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c11c000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c11c400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c11e000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c11e400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c120000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c120200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c122000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c122400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c124000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c124400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c126000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c126200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c128000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c128400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c12a000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c12a400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c12c000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c12c200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c12e000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c12e400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c130000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c130400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c132000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c132200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c134000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c134400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c136000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c136400 + (i * 4), 0x55555555);
- }
-
- /* lnx2_xfi Internal Memory.*/
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c308000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c308200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c30a000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c30a400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c30c000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c30c400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 3U; i++) {
- mmio_write_32(0x70c30e000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c30e200 + (i * 4), 0x55555555);
- mmio_write_32(0x70c310000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c310400 + (i * 4), 0x55555555);
- }
- for (i = 0U; i < 5U; i++) {
- mmio_write_32(0x70c312000 + (i * 4), 0x55555555);
- mmio_write_32(0x70c312400 + (i * 4), 0x55555555);
- }
-
/* Disable BIST */
mmio_write_32(0x700117E60, val3);
mmio_write_32(0x700117E90, val4);