tree 4d735faceb0449e4de072adc56e60e88d105a69f
parent 643f493652c04b288de0d351bf25c115fdbb6f5e
author Nishanth Menon <nm@ti.com> 1484062447 -0600
committer Nishanth Menon <nm@ti.com> 1484062604 -0600

uart: 16550: Fix getc

tbz check for RDR status is to check for a bit being zero.
Unfortunately, we are using a mask rather than the bit position.

Further as per http://www.ti.com/lit/ds/symlink/pc16550d.pdf (page 17),
LSR register bit 0 is Data ready status (RDR), not bit position 2.

Update the same to match the specification.

Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>