tree 4f88a9ed2042de8c7c344a8450e9f660f8598c1e
parent 0727b01cc167726117097a844d2f6b1836e7b95a
author Tien Hock Loh <tien.hock.loh@intel.com> 1589184683 -0700
committer Manish Pandey <manish.pandey2@arm.com> 1591653807 +0000

plat: intel: Fix clock configuration bugs

This fixes a few issues on the Agilex clock configuration:
- Set clock manager into boot mode before configuring clock
- Fix wrong divisor used when calculating vcocalib
- PLL sync configuration should be read and then written
- Wait PLL lock after PLL sync configuration is done
- Clear interrupt bits instead of set interrupt bits after configuration

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: I54c1dc5fe9b102e3bbc1237a92d8471173b8af70