Merge changes from topic "qemu-rme" into integration
* changes:
feat(qemu): support TRP for RME
feat(qemu): load and run RMM image
feat(qemu): setup Granule Protection Table
feat(qemu): setup memory map for RME
feat(qemu): update mapping types for RME
feat(qemu): use mock attestation functions for RME
fix(qemu): increase max FIP size
diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
index 2dcac69..36d9f5b 100644
--- a/plat/qemu/common/common.mk
+++ b/plat/qemu/common/common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved.
+# Copyright (c) 2023-2024, Linaro Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -126,6 +126,11 @@
ENABLE_SME_FOR_NS := 2
endif
+ifeq (${ENABLE_RME},1)
+BL31_SOURCES += plat/qemu/common/qemu_plat_attest_token.c \
+ plat/qemu/common/qemu_realm_attest_key.c
+endif
+
# Treating this as a memory-constrained port for now
USE_COHERENT_MEM := 0
diff --git a/plat/qemu/common/qemu_bl2_mem_params_desc.c b/plat/qemu/common/qemu_bl2_mem_params_desc.c
index bb1797d..c444be4 100644
--- a/plat/qemu/common/qemu_bl2_mem_params_desc.c
+++ b/plat/qemu/common/qemu_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -67,11 +67,28 @@
# ifdef QEMU_LOAD_BL32
.next_handoff_image_id = BL32_IMAGE_ID,
+# elif ENABLE_RME
+ .next_handoff_image_id = RMM_IMAGE_ID,
# else
.next_handoff_image_id = BL33_IMAGE_ID,
# endif
},
#endif /* __aarch64__ */
+
+#if ENABLE_RME
+ /* Fill RMM related information */
+ { .image_id = RMM_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, EP_REALM | EXECUTABLE),
+ .ep_info.pc = RMM_BASE,
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = RMM_BASE,
+ .image_info.image_max_size = RMM_LIMIT - RMM_BASE,
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+#endif /* ENABLE_RME */
+
# ifdef QEMU_LOAD_BL32
#ifdef __aarch64__
@@ -95,7 +112,11 @@
.image_info.image_base = BL32_BASE,
.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+#if ENABLE_RME
+ .next_handoff_image_id = RMM_IMAGE_ID,
+#else
.next_handoff_image_id = BL33_IMAGE_ID,
+#endif
},
/*
diff --git a/plat/qemu/common/qemu_bl2_setup.c b/plat/qemu/common/qemu_bl2_setup.c
index 231f23a..8c7518d 100644
--- a/plat/qemu/common/qemu_bl2_setup.c
+++ b/plat/qemu/common/qemu_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#include <platform_def.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
@@ -23,30 +24,33 @@
#endif
#include <lib/utils.h>
#include <plat/common/platform.h>
+#if ENABLE_RME
+#include <qemu_pas_def.h>
+#endif
#include "qemu_private.h"
#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
bl2_tzram_layout.total_base, \
bl2_tzram_layout.total_size, \
- MT_MEMORY | MT_RW | MT_SECURE)
+ MT_MEMORY | MT_RW | EL3_PAS)
#define MAP_BL2_RO MAP_REGION_FLAT( \
BL_CODE_BASE, \
BL_CODE_END - BL_CODE_BASE, \
- MT_CODE | MT_SECURE), \
+ MT_CODE | EL3_PAS), \
MAP_REGION_FLAT( \
BL_RO_DATA_BASE, \
BL_RO_DATA_END \
- BL_RO_DATA_BASE, \
- MT_RO_DATA | MT_SECURE)
+ MT_RO_DATA | EL3_PAS)
#if USE_COHERENT_MEM
#define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
BL_COHERENT_RAM_BASE, \
BL_COHERENT_RAM_END \
- BL_COHERENT_RAM_BASE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+ MT_DEVICE | MT_RW | EL3_PAS)
#endif
/* Data structure which holds the extents of the trusted SRAM for BL2 */
@@ -101,6 +105,18 @@
return;
}
+#if ENABLE_RME
+ if (fdt_add_reserved_memory(fdt, "rmm", REALM_DRAM_BASE,
+ REALM_DRAM_SIZE)) {
+ ERROR("Failed to reserve RMM memory in Device Tree\n");
+ return;
+ }
+
+ INFO("Reserved RMM memory [0x%lx, 0x%lx] in Device tree\n",
+ (uintptr_t)REALM_DRAM_BASE,
+ (uintptr_t)REALM_DRAM_BASE + REALM_DRAM_SIZE - 1);
+#endif
+
ret = fdt_pack(fdt);
if (ret < 0)
ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret);
@@ -137,6 +153,53 @@
transfer_list_update_checksum(bl2_tl);
#endif
}
+
+#if ENABLE_RME
+static void bl2_plat_gpt_setup(void)
+{
+ /*
+ * The GPT library might modify the gpt regions structure to optimize
+ * the layout, so the array cannot be constant.
+ */
+ pas_region_t pas_regions[] = {
+ QEMU_PAS_ROOT,
+ QEMU_PAS_SECURE,
+ QEMU_PAS_GPTS,
+ QEMU_PAS_NS0,
+ QEMU_PAS_REALM,
+ QEMU_PAS_NS1,
+ };
+
+ /*
+ * Initialize entire protected space to GPT_GPI_ANY. With each L0 entry
+ * covering 1GB (currently the only supported option), then covering
+ * 256TB of RAM (48-bit PA) would require a 2MB L0 region. At the
+ * moment we use a 8KB table, which covers 1TB of RAM (40-bit PA).
+ */
+ if (gpt_init_l0_tables(GPCCR_PPS_1TB, PLAT_QEMU_L0_GPT_BASE,
+ PLAT_QEMU_L0_GPT_SIZE) < 0) {
+ ERROR("gpt_init_l0_tables() failed!\n");
+ panic();
+ }
+
+ /* Carve out defined PAS ranges. */
+ if (gpt_init_pas_l1_tables(GPCCR_PGS_4K,
+ PLAT_QEMU_L1_GPT_BASE,
+ PLAT_QEMU_L1_GPT_SIZE,
+ pas_regions,
+ (unsigned int)(sizeof(pas_regions) /
+ sizeof(pas_region_t))) < 0) {
+ ERROR("gpt_init_pas_l1_tables() failed!\n");
+ panic();
+ }
+
+ INFO("Enabling Granule Protection Checks\n");
+ if (gpt_enable() < 0) {
+ ERROR("gpt_enable() failed!\n");
+ panic();
+ }
+}
+#endif
void bl2_plat_arch_setup(void)
{
@@ -146,16 +209,31 @@
#if USE_COHERENT_MEM
MAP_BL_COHERENT_RAM,
#endif
+#if ENABLE_RME
+ MAP_RMM_DRAM,
+ MAP_GPT_L0_REGION,
+ MAP_GPT_L1_REGION,
+#endif
{0}
};
setup_page_tables(bl_regions, plat_qemu_get_mmap());
+#if ENABLE_RME
+ /* BL2 runs in EL3 when RME enabled. */
+ assert(get_armv9_2_feat_rme_support() != 0U);
+ enable_mmu_el3(0);
+
+ /* Initialise and enable granule protection after MMU. */
+ bl2_plat_gpt_setup();
+#else /* ENABLE_RME */
+
#ifdef __aarch64__
enable_mmu_el1(0);
#else
enable_mmu_svc_mon(0);
#endif
+#endif /* ENABLE_RME */
}
/*******************************************************************************
diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index f309efd..894b842 100644
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,7 @@
#include <common/bl_common.h>
#include <drivers/arm/pl061_gpio.h>
+#include <lib/gpt_rme/gpt_rme.h>
#include <plat/common/platform.h>
#include "qemu_private.h"
@@ -40,6 +41,9 @@
*/
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
+#if ENABLE_RME
+static entry_point_info_t rmm_image_ep_info;
+#endif
/*******************************************************************************
* Perform any BL3-1 early platform setup. Here is an opportunity to copy
@@ -72,13 +76,18 @@
bl_params_node_t *bl_params = params_from_bl2->head;
/*
- * Copy BL33 and BL32 (if present), entry point information.
+ * Copy BL33, BL32 and RMM (if present), entry point information.
* They are stored in Secure RAM, in BL2's address space.
*/
while (bl_params) {
if (bl_params->image_id == BL32_IMAGE_ID)
bl32_image_ep_info = *bl_params->ep_info;
+#if ENABLE_RME
+ if (bl_params->image_id == RMM_IMAGE_ID)
+ rmm_image_ep_info = *bl_params->ep_info;
+#endif
+
if (bl_params->image_id == BL33_IMAGE_ID)
bl33_image_ep_info = *bl_params->ep_info;
@@ -87,6 +96,10 @@
if (!bl33_image_ep_info.pc)
panic();
+#if ENABLE_RME
+ if (!rmm_image_ep_info.pc)
+ panic();
+#endif
}
void bl31_plat_arch_setup(void)
@@ -97,12 +110,31 @@
#if USE_COHERENT_MEM
MAP_BL_COHERENT_RAM,
#endif
+#if ENABLE_RME
+ MAP_GPT_L0_REGION,
+ MAP_GPT_L1_REGION,
+ MAP_RMM_SHARED_MEM,
+#endif
{0}
};
setup_page_tables(bl_regions, plat_qemu_get_mmap());
enable_mmu_el3(0);
+
+#if ENABLE_RME
+ /*
+ * Initialise Granule Protection library and enable GPC for the primary
+ * processor. The tables have already been initialized by a previous BL
+ * stage, so there is no need to provide any PAS here. This function
+ * sets up pointers to those tables.
+ */
+ if (gpt_runtime_init() < 0) {
+ ERROR("gpt_runtime_init() failed!\n");
+ panic();
+ }
+#endif /* ENABLE_RME */
+
}
static void qemu_gpio_init(void)
@@ -135,8 +167,18 @@
entry_point_info_t *next_image_info;
assert(sec_state_is_valid(type));
- next_image_info = (type == NON_SECURE)
- ? &bl33_image_ep_info : &bl32_image_ep_info;
+ if (type == NON_SECURE) {
+ next_image_info = &bl33_image_ep_info;
+ }
+#if ENABLE_RME
+ else if (type == REALM) {
+ next_image_info = &rmm_image_ep_info;
+ }
+#endif
+ else {
+ next_image_info = &bl32_image_ep_info;
+ }
+
/*
* None of the images on the ARM development platforms can have 0x0
* as the entrypoint
diff --git a/plat/qemu/common/qemu_common.c b/plat/qemu/common/qemu_common.c
index d4488a4..cafee6f 100644
--- a/plat/qemu/common/qemu_common.c
+++ b/plat/qemu/common/qemu_common.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,45 +11,48 @@
#include <common/bl_common.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <services/el3_spmc_ffa_memory.h>
+#if ENABLE_RME
+#include <services/rmm_core_manifest.h>
+#endif
#include <plat/common/platform.h>
#include "qemu_private.h"
#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
DEVICE0_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+ MT_DEVICE | MT_RW | EL3_PAS)
#ifdef DEVICE1_BASE
#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
DEVICE1_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+ MT_DEVICE | MT_RW | EL3_PAS)
#endif
#ifdef DEVICE2_BASE
#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
DEVICE2_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+ MT_DEVICE | MT_RW | EL3_PAS)
#endif
#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
SHARED_RAM_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
+ MT_DEVICE | MT_RW | EL3_PAS)
#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
+ MT_MEMORY | MT_RW | EL3_PAS)
#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
#define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \
- MT_MEMORY | MT_RO | MT_SECURE)
+ MT_MEMORY | MT_RO | EL3_PAS)
#define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \
- MT_MEMORY | MT_RO | MT_SECURE)
+ MT_MEMORY | MT_RO | EL3_PAS)
#ifdef FW_HANDOFF_BASE
#define MAP_FW_HANDOFF MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
+ MT_MEMORY | MT_RW | EL3_PAS)
#endif
#ifdef FW_NS_HANDOFF_BASE
#define MAP_FW_NS_HANDOFF MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE, \
@@ -138,6 +141,19 @@
};
#endif
+#ifdef IMAGE_RMM
+const mmap_region_t plat_qemu_mmap[] = {
+ MAP_DEVICE0,
+#ifdef MAP_DEVICE1
+ MAP_DEVICE1,
+#endif
+#ifdef MAP_DEVICE2
+ MAP_DEVICE2,
+#endif
+ {0}
+};
+#endif
+
/*******************************************************************************
* Returns QEMU platform specific memory map regions.
******************************************************************************/
@@ -190,3 +206,76 @@
return -1;
}
#endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/
+
+#if ENABLE_RME
+/*
+ * Get a pointer to the RMM-EL3 Shared buffer and return it
+ * through the pointer passed as parameter.
+ *
+ * This function returns the size of the shared buffer.
+ */
+size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared)
+{
+ *shared = (uintptr_t)RMM_SHARED_BASE;
+
+ return (size_t)RMM_SHARED_SIZE;
+}
+
+int plat_rmmd_load_manifest(struct rmm_manifest *manifest)
+{
+ uint64_t checksum;
+ uintptr_t base;
+ uint64_t size;
+ struct ns_dram_bank *bank_ptr;
+
+ assert(manifest != NULL);
+
+ manifest->version = RMMD_MANIFEST_VERSION;
+ manifest->padding = 0U; /* RES0 */
+ manifest->plat_data = (uintptr_t)NULL;
+ manifest->plat_dram.num_banks = 1;
+
+ /*
+ * Array ns_dram_banks[] follows ns_dram_info structure:
+ *
+ * +-----------------------------------+
+ * | offset | field | comment |
+ * +----------+-----------+------------+
+ * | 0 | version | 0x00000002 |
+ * +----------+-----------+------------+
+ * | 4 | padding | 0x00000000 |
+ * +----------+-----------+------------+
+ * | 8 | plat_data | NULL |
+ * +----------+-----------+------------+
+ * | 16 | num_banks | |
+ * +----------+-----------+ |
+ * | 24 | banks | plat_dram |
+ * +----------+-----------+ |
+ * | 32 | checksum | |
+ * +----------+-----------+------------+
+ * | 40 | base 0 | |
+ * +----------+-----------+ bank[0] |
+ * | 48 | size 0 | |
+ * +----------+-----------+------------+
+ */
+ bank_ptr = (struct ns_dram_bank *)
+ ((uintptr_t)&manifest->plat_dram.checksum +
+ sizeof(manifest->plat_dram.checksum));
+
+ manifest->plat_dram.banks = bank_ptr;
+
+ /* Calculate checksum of plat_dram structure */
+ checksum = 1 + (uint64_t)bank_ptr;
+
+ base = NS_DRAM0_BASE;
+ size = NS_DRAM0_SIZE;
+ bank_ptr[0].base = base;
+ bank_ptr[0].size = size;
+ checksum += base + size;
+
+ /* Checksum must be 0 */
+ manifest->plat_dram.checksum = ~checksum + 1UL;
+
+ return 0;
+}
+#endif /* ENABLE_RME */
diff --git a/plat/qemu/common/qemu_io_storage.c b/plat/qemu/common/qemu_io_storage.c
index 4c61b14..59bba86 100644
--- a/plat/qemu/common/qemu_io_storage.c
+++ b/plat/qemu/common/qemu_io_storage.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,6 +33,7 @@
#define BL32_EXTRA1_IMAGE_NAME "bl32_extra1.bin"
#define BL32_EXTRA2_IMAGE_NAME "bl32_extra2.bin"
#define BL33_IMAGE_NAME "bl33.bin"
+#define RMM_IMAGE_NAME "rmm.bin"
#if TRUSTED_BOARD_BOOT
#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt"
@@ -96,6 +97,10 @@
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
+static const io_uuid_spec_t rmm_uuid_spec = {
+ .uuid = UUID_REALM_MONITOR_MGMT_FIRMWARE,
+};
+
#if TRUSTED_BOARD_BOOT
static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
.uuid = UUID_TRUSTED_BOOT_FW_CERT,
@@ -163,6 +168,10 @@
.path = BL33_IMAGE_NAME,
.mode = FOPEN_MODE_RB
},
+ [RMM_IMAGE_ID] = {
+ .path = RMM_IMAGE_NAME,
+ .mode = FOPEN_MODE_RB
+ },
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
.path = TRUSTED_BOOT_FW_CERT_NAME,
@@ -289,6 +298,12 @@
(uintptr_t)&bl33_uuid_spec,
open_fip
},
+ [RMM_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&rmm_uuid_spec,
+ open_fip
+ },
+
#if TRUSTED_BOARD_BOOT
[TRUSTED_BOOT_FW_CERT_ID] = {
&fip_dev_handle,
diff --git a/plat/qemu/common/qemu_plat_attest_token.c b/plat/qemu/common/qemu_plat_attest_token.c
new file mode 100644
index 0000000..cf3376d
--- /dev/null
+++ b/plat/qemu/common/qemu_plat_attest_token.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include <plat/common/platform.h>
+
+static const uint8_t sample_platform_token[] = {
+ 0xD2, 0x84, 0x44, 0xA1, 0x01, 0x38, 0x22, 0xA0,
+ 0x59, 0x02, 0x33, 0xA9, 0x19, 0x01, 0x09, 0x78,
+ 0x1C, 0x68, 0x74, 0x74, 0x70, 0x3A, 0x2F, 0x2F,
+ 0x61, 0x72, 0x6D, 0x2E, 0x63, 0x6F, 0x6D, 0x2F,
+ 0x43, 0x43, 0x41, 0x2D, 0x53, 0x53, 0x44, 0x2F,
+ 0x31, 0x2E, 0x30, 0x2E, 0x30, 0x0A, 0x58, 0x20,
+ 0xB5, 0x97, 0x3C, 0xB6, 0x8B, 0xAA, 0x9F, 0xC5,
+ 0x55, 0x58, 0x78, 0x6B, 0x7E, 0xC6, 0x7F, 0x69,
+ 0xE4, 0x0D, 0xF5, 0xBA, 0x5A, 0xA9, 0x21, 0xCD,
+ 0x0C, 0x27, 0xF4, 0x05, 0x87, 0xA0, 0x11, 0xEA,
+ 0x19, 0x09, 0x5C, 0x58, 0x20, 0x7F, 0x45, 0x4C,
+ 0x46, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x3E,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x50, 0x58, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x19, 0x01, 0x00,
+ 0x58, 0x21, 0x01, 0x07, 0x06, 0x05, 0x04, 0x03,
+ 0x02, 0x01, 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B,
+ 0x0A, 0x09, 0x08, 0x17, 0x16, 0x15, 0x14, 0x13,
+ 0x12, 0x11, 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B,
+ 0x1A, 0x19, 0x18, 0x19, 0x09, 0x61, 0x58, 0x21,
+ 0x01, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01,
+ 0x00, 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09,
+ 0x08, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11,
+ 0x10, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19,
+ 0x18, 0x19, 0x09, 0x5B, 0x19, 0x30, 0x03, 0x19,
+ 0x09, 0x62, 0x67, 0x73, 0x68, 0x61, 0x2D, 0x32,
+ 0x35, 0x36, 0x19, 0x09, 0x5F, 0x84, 0xA5, 0x01,
+ 0x62, 0x42, 0x4C, 0x05, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
+ 0x33, 0x2E, 0x34, 0x2E, 0x32, 0x02, 0x58, 0x20,
+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
+ 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
+ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
+ 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
+ 0x06, 0x74, 0x54, 0x46, 0x2D, 0x4D, 0x5F, 0x53,
+ 0x48, 0x41, 0x32, 0x35, 0x36, 0x4D, 0x65, 0x6D,
+ 0x50, 0x72, 0x65, 0x58, 0x49, 0x50, 0xA4, 0x01,
+ 0x62, 0x4D, 0x31, 0x05, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x63,
+ 0x31, 0x2E, 0x32, 0x02, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0xA4, 0x01,
+ 0x62, 0x4D, 0x32, 0x05, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x04, 0x65,
+ 0x31, 0x2E, 0x32, 0x2E, 0x33, 0x02, 0x58, 0x20,
+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
+ 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
+ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
+ 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
+ 0xA4, 0x01, 0x62, 0x4D, 0x33, 0x05, 0x58, 0x20,
+ 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
+ 0x0F, 0x0E, 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08,
+ 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10,
+ 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18,
+ 0x04, 0x61, 0x31, 0x02, 0x58, 0x20, 0x07, 0x06,
+ 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x0F, 0x0E,
+ 0x0D, 0x0C, 0x0B, 0x0A, 0x09, 0x08, 0x17, 0x16,
+ 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x1F, 0x1E,
+ 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x19, 0x09,
+ 0x60, 0x6C, 0x77, 0x68, 0x61, 0x74, 0x65, 0x76,
+ 0x65, 0x72, 0x2E, 0x63, 0x6F, 0x6D, 0x58, 0x60,
+ 0xE6, 0xB6, 0x38, 0x4F, 0xAE, 0x3F, 0x6E, 0x67,
+ 0xF5, 0xD4, 0x97, 0x4B, 0x3F, 0xFD, 0x0A, 0xFA,
+ 0x1D, 0xF0, 0x2F, 0x73, 0xB8, 0xFF, 0x5F, 0x02,
+ 0xC0, 0x0F, 0x40, 0xAC, 0xF3, 0xA2, 0x9D, 0xB5,
+ 0x31, 0x50, 0x16, 0x4F, 0xFA, 0x34, 0x3D, 0x0E,
+ 0xAF, 0xE0, 0xD0, 0xD1, 0x6C, 0xF0, 0x9D, 0xC1,
+ 0x01, 0x42, 0xA2, 0x3C, 0xCE, 0xD4, 0x4A, 0x59,
+ 0xDC, 0x29, 0x0A, 0x30, 0x93, 0x5F, 0xB4, 0x98,
+ 0x61, 0xBA, 0xE3, 0x91, 0x22, 0x95, 0x24, 0xF4,
+ 0xAE, 0x47, 0x93, 0xD3, 0x84, 0xA3, 0x76, 0xD0,
+ 0xC1, 0x26, 0x96, 0x53, 0xA3, 0x60, 0x3F, 0x6C,
+ 0x75, 0x96, 0x90, 0x6A, 0xF9, 0x4E, 0xDA, 0x30
+};
+
+/*
+ * Get the hardcoded platform attestation token as QEMU does not support
+ * RSS.
+ */
+int plat_rmmd_get_cca_attest_token(uintptr_t buf, size_t *len,
+ uintptr_t hash, size_t hash_size)
+{
+ (void)hash;
+ (void)hash_size;
+
+ if (*len < sizeof(sample_platform_token)) {
+ return -EINVAL;
+ }
+
+ (void)memcpy((void *)buf, (const void *)sample_platform_token,
+ sizeof(sample_platform_token));
+ *len = sizeof(sample_platform_token);
+
+ return 0;
+}
diff --git a/plat/qemu/common/qemu_realm_attest_key.c b/plat/qemu/common/qemu_realm_attest_key.c
new file mode 100644
index 0000000..abd569b
--- /dev/null
+++ b/plat/qemu/common/qemu_realm_attest_key.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include <plat/common/platform.h>
+
+static const uint8_t sample_delegated_key[] = {
+ 0x20, 0x11, 0xC7, 0xF0, 0x3C, 0xEE, 0x43, 0x25, 0x17, 0x6E,
+ 0x52, 0x4F, 0x03, 0x3C, 0x0C, 0xE1, 0xE2, 0x1A, 0x76, 0xE6,
+ 0xC1, 0xA4, 0xF0, 0xB8, 0x39, 0xAA, 0x1D, 0xF6, 0x1E, 0x0E,
+ 0x8A, 0x5C, 0x8A, 0x05, 0x74, 0x0F, 0x9B, 0x69, 0xEF, 0xA7,
+ 0xEB, 0x1A, 0x41, 0x85, 0xBD, 0x11, 0x7F, 0x68
+};
+
+/*
+ * Get the hardcoded delegated realm attestation key as QEMU
+ * does not support RSS.
+ */
+int plat_rmmd_get_cca_realm_attest_key(uintptr_t buf, size_t *len,
+ unsigned int type)
+{
+ if (*len < sizeof(sample_delegated_key)) {
+ return -EINVAL;
+ }
+
+ (void)memcpy((void *)buf, (const void *)sample_delegated_key,
+ sizeof(sample_delegated_key));
+ *len = sizeof(sample_delegated_key);
+
+ return 0;
+}
diff --git a/plat/qemu/common/trp/qemu_trp_setup.c b/plat/qemu/common/trp/qemu_trp_setup.c
new file mode 100644
index 0000000..0b914ee
--- /dev/null
+++ b/plat/qemu/common/trp/qemu_trp_setup.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/bl_common.h>
+#include <platform_def.h>
+#include <services/rmm_core_manifest.h>
+#include <services/rmmd_svc.h>
+#include <services/trp/platform_trp.h>
+#include <trp_helpers.h>
+
+#include "../qemu_private.h"
+
+/*******************************************************************************
+ * Received from boot manifest and populated here
+ ******************************************************************************/
+extern uint32_t trp_boot_manifest_version;
+
+static int qemu_trp_process_manifest(struct rmm_manifest *manifest)
+{
+ /* padding field on the manifest must be RES0 */
+ assert(manifest->padding == 0U);
+
+ /* Verify the Boot Manifest Version. Only the Major is considered */
+ if (RMMD_MANIFEST_VERSION_MAJOR !=
+ RMMD_GET_MANIFEST_VERSION_MAJOR(manifest->version)) {
+ return E_RMM_BOOT_MANIFEST_VERSION_NOT_SUPPORTED;
+ }
+
+ trp_boot_manifest_version = manifest->version;
+ flush_dcache_range((uintptr_t)manifest, sizeof(struct rmm_manifest));
+
+ return 0;
+}
+
+void trp_early_platform_setup(struct rmm_manifest *manifest)
+{
+ int rc;
+
+ rc = qemu_trp_process_manifest(manifest);
+ if (rc != 0) {
+ trp_boot_abort(rc);
+ }
+
+ qemu_console_init();
+}
diff --git a/plat/qemu/common/trp/trp-qemu-common.mk b/plat/qemu/common/trp/trp-qemu-common.mk
new file mode 100644
index 0000000..081ba55
--- /dev/null
+++ b/plat/qemu/common/trp/trp-qemu-common.mk
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# TRP source files common to QEMU platforms
+RMM_SOURCES += plat/qemu/common/trp/qemu_trp_setup.c \
+ plat/common/aarch64/platform_mp_stack.S \
+ plat/qemu/common/aarch64/plat_helpers.S
+
+INCLUDES += -Iinclude/services/trp
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index 903c809..4e0b50a 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -171,7 +171,8 @@
#define BL32_SRAM_BASE BL_RAM_BASE
#define BL32_SRAM_LIMIT BL31_BASE
#define BL32_DRAM_BASE SEC_DRAM_BASE
-#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE)
+#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE - \
+ RME_GPT_DRAM_SIZE)
#define SEC_SRAM_ID 0
#define SEC_DRAM_ID 1
@@ -199,7 +200,7 @@
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#define MAX_MMAP_REGIONS (11 + MAX_MMAP_REGIONS_SPMC)
+#define MAX_MMAP_REGIONS (13 + MAX_MMAP_REGIONS_SPMC)
#define MAX_XLAT_TABLES (6 + MAX_XLAT_TABLES_SPMC)
#define MAX_IO_DEVICES 4
#define MAX_IO_HANDLES 4
@@ -226,7 +227,7 @@
#define QEMU_FLASH1_SIZE 0x04000000
#define PLAT_QEMU_FIP_BASE 0x00040000
-#define PLAT_QEMU_FIP_MAX_SIZE 0x00400000
+#define PLAT_QEMU_FIP_MAX_SIZE (QEMU_FLASH0_SIZE - PLAT_QEMU_FIP_BASE)
#define DEVICE0_BASE 0x08000000
#define DEVICE0_SIZE 0x01000000
@@ -338,4 +339,72 @@
#define MAX_MMAP_REGIONS_SPMC 0
#define MAX_XLAT_TABLES_SPMC 0
#endif
+
+#if ENABLE_RME
+
+/*
+ * Reserve some space at the end of secure DRAM for the Granule Protection
+ * Tables
+ */
+#define PLAT_QEMU_L0_GPT_BASE (PLAT_QEMU_L1_GPT_BASE - \
+ PLAT_QEMU_L0_GPT_SIZE)
+#define PLAT_QEMU_L0_GPT_SIZE (2 * PAGE_SIZE)
+
+#define PLAT_QEMU_L1_GPT_BASE (SEC_DRAM_BASE + SEC_DRAM_SIZE - \
+ PLAT_QEMU_L1_GPT_SIZE)
+#define PLAT_QEMU_L1_GPT_END (PLAT_QEMU_L1_GPT_BASE + \
+ PLAT_QEMU_L1_GPT_SIZE - 1U)
+#define PLAT_QEMU_L1_GPT_SIZE UL(0x00100000) /* 1MB */
+
+#define RME_GPT_DRAM_BASE PLAT_QEMU_L0_GPT_BASE
+#define RME_GPT_DRAM_SIZE (PLAT_QEMU_L1_GPT_SIZE + \
+ PLAT_QEMU_L0_GPT_SIZE)
+
+#ifndef __ASSEMBLER__
+/* L0 table greater than 4KB must be naturally aligned */
+CASSERT((PLAT_QEMU_L0_GPT_BASE & (PLAT_QEMU_L0_GPT_SIZE - 1)) == 0,
+ assert_l0_gpt_naturally_aligned);
+#endif
+
+/* Reserved some DRAM space for RMM (24MB) */
+#define REALM_DRAM_BASE (NS_DRAM0_BASE + PLAT_QEMU_DT_MAX_SIZE)
+#define REALM_DRAM_SIZE 0x01800000
+
+#define PLAT_QEMU_RMM_SIZE (REALM_DRAM_SIZE - RMM_SHARED_SIZE)
+#define PLAT_QEMU_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */
+
+#define RMM_BASE (REALM_DRAM_BASE)
+#define RMM_LIMIT (RMM_BASE + PLAT_QEMU_RMM_SIZE)
+#define RMM_SHARED_BASE (RMM_LIMIT)
+#define RMM_SHARED_SIZE PLAT_QEMU_RMM_SHARED_SIZE
+
+#define MAP_GPT_L0_REGION MAP_REGION_FLAT( \
+ PLAT_QEMU_L0_GPT_BASE, \
+ PLAT_QEMU_L0_GPT_SIZE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#define MAP_GPT_L1_REGION MAP_REGION_FLAT( \
+ PLAT_QEMU_L1_GPT_BASE, \
+ PLAT_QEMU_L1_GPT_SIZE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+/*
+ * We add the RMM_SHARED size to RMM mapping to map the region as a block.
+ * Else we end up requiring more pagetables in BL2 for ROMLIB build.
+ */
+#define MAP_RMM_DRAM MAP_REGION_FLAT( \
+ RMM_BASE, \
+ (PLAT_QEMU_RMM_SIZE + \
+ RMM_SHARED_SIZE), \
+ MT_MEMORY | MT_RW | MT_REALM)
+
+#define MAP_RMM_SHARED_MEM MAP_REGION_FLAT( \
+ RMM_SHARED_BASE, \
+ RMM_SHARED_SIZE, \
+ MT_MEMORY | MT_RW | MT_REALM)
+#else /* !ENABLE_RME */
+
+#define RME_GPT_DRAM_SIZE 0
+
+#endif /* ENABLE_RME */
+
#endif /* PLATFORM_DEF_H */
diff --git a/plat/qemu/qemu/include/qemu_pas_def.h b/plat/qemu/qemu/include/qemu_pas_def.h
new file mode 100644
index 0000000..c108920
--- /dev/null
+++ b/plat/qemu/qemu/include/qemu_pas_def.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef QEMU_PAS_DEF_H
+#define QEMU_PAS_DEF_H
+
+#include <lib/gpt_rme/gpt_rme.h>
+#include "platform_def.h"
+
+/*****************************************************************************
+ * PAS regions used to initialize the Granule Protection Table (GPT)
+ ****************************************************************************/
+
+/*
+ * The PA space is initially mapped in the GPT as follows:
+ *
+ * ===========================================================================
+ * Base Addr | Size |L? GPT|PAS |Content |Comment
+ * ===========================================================================
+ * | 1GB |L0 GPT|ANY |Flash |
+ * 00000000 | | | |IO |
+ * ---------------------------------------------------------------------------
+ * 224MB | 1KB |L0 GPT|ANY |Secure RAM (EL3) |
+ * 0e000000 | | | | (shared) |
+ * ---------------------------------------------------------------------------
+ * | 1MB-1KB |L1 GPT|ROOT |Secure RAM (EL3) |
+ * 0e001000 | | | | |
+ * ---------------------------------------------------------------------------
+ * 225MB | 14MB |L1 GPT|SECURE|Secure RAM |
+ * 0e100000 | | | | (EL2, EL1) |
+ * ---------------------------------------------------------------------------
+ * | 1MB+8KB |L1 GPT|ROOT |L0 and L1 GPTs |
+ * 0eefe000 | | | | |
+ * ---------------------------------------------------------------------------
+ * 240MB | 800MB |L0 GPT|ANY |IO |
+ * 0f000000 | | | | |
+ * ---------------------------------------------------------------------------
+ * 1GB | 1MB |L1 GPT|NS |DRAM |
+ * 40000000 | | | | (device tree) |
+ * ---------------------------------------------------------------------------
+ * 1GB+1MB | 24MB |L1 GPT|REALM |DRAM (RMM) |
+ * 40100000 | | | | |
+ * ---------------------------------------------------------------------------
+ * 1GB+25MB | 3GB |L1 GPT|NS |DRAM (kernel) | Limit set by
+ * 41900000 | | | | | NS_DRAM0_SIZE
+ * ---------------------------------------------------------------------------
+ * 256GB | 512+GB |L0 GPT|ANY |IO | Floating. Higher
+ * 40000000000 | | | | | when RAM>256GB
+ * ----------------------------------------------------------------------------
+ */
+
+/* EL3 SRAM */
+#define QEMU_PAS_ROOT_BASE BL_RAM_BASE
+#define QEMU_PAS_ROOT_SIZE BL_RAM_SIZE
+
+/* Secure DRAM */
+#define QEMU_PAS_SEC_BASE SEC_DRAM_BASE
+#define QEMU_PAS_SEC_SIZE (SEC_DRAM_SIZE - RME_GPT_DRAM_SIZE)
+
+/* GPTs */
+#define QEMU_PAS_GPT_BASE RME_GPT_DRAM_BASE
+#define QEMU_PAS_GPT_SIZE RME_GPT_DRAM_SIZE
+
+/* RMM */
+#define QEMU_PAS_RMM_BASE RMM_BASE
+#define QEMU_PAS_RMM_SIZE PLAT_QEMU_RMM_SIZE
+
+/* Shared area between EL3 and RMM */
+#define QEMU_PAS_RMM_SHARED_BASE RMM_SHARED_BASE
+#define QEMU_PAS_RMM_SHARED_SIZE RMM_SHARED_SIZE
+
+#define QEMU_PAS_NS0_BASE NS_DRAM0_BASE
+#define QEMU_PAS_NS0_SIZE PLAT_QEMU_DT_MAX_SIZE
+#define QEMU_PAS_NS1_BASE (REALM_DRAM_BASE + REALM_DRAM_SIZE)
+#define QEMU_PAS_NS1_SIZE (NS_DRAM0_SIZE - \
+ (QEMU_PAS_NS0_SIZE + REALM_DRAM_SIZE))
+
+#define QEMU_PAS_ROOT GPT_MAP_REGION_GRANULE(QEMU_PAS_ROOT_BASE, \
+ QEMU_PAS_ROOT_SIZE, \
+ GPT_GPI_ROOT)
+
+#define QEMU_PAS_SECURE GPT_MAP_REGION_GRANULE(QEMU_PAS_SEC_BASE, \
+ QEMU_PAS_SEC_SIZE, \
+ GPT_GPI_SECURE)
+
+#define QEMU_PAS_GPTS GPT_MAP_REGION_GRANULE(QEMU_PAS_GPT_BASE, \
+ QEMU_PAS_GPT_SIZE, \
+ GPT_GPI_ROOT)
+
+#define QEMU_PAS_NS0 GPT_MAP_REGION_GRANULE(QEMU_PAS_NS0_BASE, \
+ QEMU_PAS_NS0_SIZE, \
+ GPT_GPI_NS)
+
+#define QEMU_PAS_NS1 GPT_MAP_REGION_GRANULE(QEMU_PAS_NS1_BASE, \
+ QEMU_PAS_NS1_SIZE, \
+ GPT_GPI_NS)
+
+#define QEMU_PAS_REALM GPT_MAP_REGION_GRANULE(QEMU_PAS_RMM_BASE, \
+ QEMU_PAS_RMM_SIZE + \
+ QEMU_PAS_RMM_SHARED_SIZE, \
+ GPT_GPI_REALM)
+
+/* GPT Configuration options */
+#define PLATFORM_L0GPTSZ GPCCR_L0GPTSZ_30BITS
+
+#endif /* QEMU_PAS_DEF_H */
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index e902c12..436e425 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -204,6 +204,10 @@
BL32_RAM_LOCATION := tdram
ifeq (${BL32_RAM_LOCATION}, tsram)
BL32_RAM_LOCATION_ID = SEC_SRAM_ID
+ ifeq (${ENABLE_RME},1)
+ # Avoid overlap between BL2 and BL32 to ease GPT partition
+ $(error "With RME, BL32 must use secure DRAM")
+ endif
else ifeq (${BL32_RAM_LOCATION}, tdram)
BL32_RAM_LOCATION_ID = SEC_DRAM_ID
else
diff --git a/plat/qemu/qemu/trp/trp-qemu.mk b/plat/qemu/qemu/trp/trp-qemu.mk
new file mode 100644
index 0000000..e0f530e
--- /dev/null
+++ b/plat/qemu/qemu/trp/trp-qemu.mk
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+include plat/qemu/common/trp/trp-qemu-common.mk
+