Fix MISRA Rule 5.3 Part 4
Use a _ prefix for macro arguments to prevent that argument from
hiding variables of the same name in the outer scope
Rule 5.3: An identifier declared in an inner scope shall not
hide an identifier declared in an outer scope
Fixed For:
make PLAT=fvp USE_COHERENT_MEM=0
Change-Id: If50c583d3b63799ee6852626b15be00c0f6b10a0
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
diff --git a/lib/locks/bakery/bakery_lock_normal.c b/lib/locks/bakery/bakery_lock_normal.c
index 37697f5..630226a 100644
--- a/lib/locks/bakery/bakery_lock_normal.c
+++ b/lib/locks/bakery/bakery_lock_normal.c
@@ -53,18 +53,18 @@
IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_SIZE__, PERCPU_BAKERY_LOCK_SIZE);
#endif
-#define get_bakery_info(cpu_ix, lock) \
- (bakery_info_t *)((uintptr_t)lock + cpu_ix * PERCPU_BAKERY_LOCK_SIZE)
+#define get_bakery_info(_cpu_ix, _lock) \
+ (bakery_info_t *)((uintptr_t)_lock + _cpu_ix * PERCPU_BAKERY_LOCK_SIZE)
-#define write_cache_op(addr, cached) \
+#define write_cache_op(_addr, _cached) \
do { \
- (cached ? dccvac((uintptr_t)addr) :\
- dcivac((uintptr_t)addr));\
+ (_cached ? dccvac((uintptr_t)_addr) :\
+ dcivac((uintptr_t)_addr));\
dsbish();\
} while (0)
-#define read_cache_op(addr, cached) if (cached) \
- dccivac((uintptr_t)addr)
+#define read_cache_op(_addr, _cached) if (_cached) \
+ dccivac((uintptr_t)_addr)
/* Helper function to check if the lock is acquired */
static inline int is_lock_acquired(const bakery_info_t *my_bakery_info,