intel: stratix10: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
diff --git a/plat/intel/soc/stratix10/include/stratix10_private.h b/plat/intel/soc/stratix10/include/stratix10_private.h
index f437202..85aff3a 100644
--- a/plat/intel/soc/stratix10/include/stratix10_private.h
+++ b/plat/intel/soc/stratix10/include/stratix10_private.h
@@ -10,9 +10,9 @@
#define S10_MMC_REG_BASE 0xff808000
#define EMMC_DESC_SIZE (1<<20)
-#define EMMC_INIT_PARAMS(base) \
+#define EMMC_INIT_PARAMS(base, clk) \
{ .bus_width = MMC_BUS_WIDTH_4, \
- .clk_rate = 50000000, \
+ .clk_rate = (clk), \
.desc_base = (base), \
.desc_size = EMMC_DESC_SIZE, \
.flags = 0, \