intel: stratix10: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
index 4500c6f..a67d689 100644
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ b/plat/intel/soc/stratix10/include/s10_system_manager.h
@@ -62,6 +62,9 @@
#define S10_SYSMGR_CORE(x) (0xffd12000 + (x))
#define SYSMGR_MMC 0x28
#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0)
+#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
+#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
+#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))