diff --git a/bl1/aarch64/bl1_arch_setup.c b/bl1/aarch64/bl1_arch_setup.c
index e82ad09..f9443aa 100644
--- a/bl1/aarch64/bl1_arch_setup.c
+++ b/bl1/aarch64/bl1_arch_setup.c
@@ -41,10 +41,10 @@
 	unsigned long tmp_reg = 0;
 
 	/* Enable alignment checks and set the exception endianess to LE */
-	tmp_reg = read_sctlr();
+	tmp_reg = read_sctlr_el3();
 	tmp_reg |= (SCTLR_A_BIT | SCTLR_SA_BIT);
 	tmp_reg &= ~SCTLR_EE_BIT;
-	write_sctlr(tmp_reg);
+	write_sctlr_el3(tmp_reg);
 
 	/*
 	 * Enable HVCs, route FIQs to EL3, set the next EL to be AArch64, route
@@ -67,11 +67,10 @@
  * Set the Secure EL1 required architectural state
  ******************************************************************************/
 void bl1_arch_next_el_setup(void) {
-	unsigned long current_sctlr, next_sctlr;
+	unsigned long next_sctlr;
 
 	/* Use the same endianness than the current BL */
-	current_sctlr = read_sctlr();
-	next_sctlr = (current_sctlr & SCTLR_EE_BIT);
+	next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT);
 
 	/* Set SCTLR Secure EL1 */
 	next_sctlr |= SCTLR_EL1_RES1;
diff --git a/bl1/aarch64/early_exceptions.S b/bl1/aarch64/early_exceptions.S
index d06e854..ee91a89 100644
--- a/bl1/aarch64/early_exceptions.S
+++ b/bl1/aarch64/early_exceptions.S
@@ -195,7 +195,7 @@
 	mov	x0, #SYNC_EXCEPTION_AARCH64
 	bl	plat_report_exception
 
-	bl	read_esr
+	bl	read_esr_el3
 	ubfx	x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
 	cmp	x1, #EC_AARCH64_SMC
 	b.ne	panic
@@ -224,9 +224,9 @@
 	 * ---------------------------------------------
 	 */
 	mov	x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
-	bl	read_sctlr
+	bl	read_sctlr_el3
 	bic	x0, x0, x1
-	bl	write_sctlr
+	bl	write_sctlr_el3
 	mov	x0, #DCCISW
 	bl	dcsw_op_all
 	bl	tlbialle3