Merge changes from topic "jc/detect_feat" into integration
* changes:
feat(trbe): add trbe under feature detection mechanism
feat(brbe): add brbe under feature detection mechanism
diff --git a/docs/change-log.md b/docs/change-log.md
index 1a65700..8a555ec 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md
@@ -3,7 +3,7 @@
This document contains a summary of the new features, changes, fixes and known
issues in each release of Trusted Firmware-A.
-## [2.7.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.6.0..refs/tags/v2.7.0) (2022-05-20)
+## [2.7.0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/v2.6..refs/tags/v2.7.0) (2022-05-20)
### New Features
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index c327e71..116afda 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -694,52 +694,6 @@
return size;
}
-static inline void mmc_rpmb_enable(void)
-{
- mmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
- PART_CFG_BOOT_PARTITION1_ENABLE |
- PART_CFG_BOOT_PARTITION1_ACCESS);
-}
-
-static inline void mmc_rpmb_disable(void)
-{
- mmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
- PART_CFG_BOOT_PARTITION1_ENABLE);
-}
-
-size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size)
-{
- size_t size_read;
-
- mmc_rpmb_enable();
- size_read = mmc_read_blocks(lba, buf, size);
- mmc_rpmb_disable();
-
- return size_read;
-}
-
-size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size)
-{
- size_t size_written;
-
- mmc_rpmb_enable();
- size_written = mmc_write_blocks(lba, buf, size);
- mmc_rpmb_disable();
-
- return size_written;
-}
-
-size_t mmc_rpmb_erase_blocks(int lba, size_t size)
-{
- size_t size_erased;
-
- mmc_rpmb_enable();
- size_erased = mmc_erase_blocks(lba, size);
- mmc_rpmb_disable();
-
- return size_erased;
-}
-
static int mmc_part_switch(unsigned int part_type)
{
uint8_t part_config = mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG];
@@ -755,29 +709,51 @@
return PART_CFG_CURRENT_BOOT_PARTITION(mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG]);
}
-size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size)
+int mmc_part_switch_current_boot(void)
{
- size_t size_read;
- int ret;
unsigned char current_boot_part = mmc_current_boot_part();
+ int ret;
if (current_boot_part != 1U &&
current_boot_part != 2U) {
ERROR("Got unexpected value for active boot partition, %u\n", current_boot_part);
- return 0;
+ return -EIO;
}
ret = mmc_part_switch(current_boot_part);
if (ret < 0) {
ERROR("Failed to switch to boot partition, %d\n", ret);
+ }
+
+ return ret;
+}
+
+int mmc_part_switch_user(void)
+{
+ int ret;
+
+ ret = mmc_part_switch(PART_CFG_BOOT_PARTITION_NO_ACCESS);
+ if (ret < 0) {
+ ERROR("Failed to switch to user partition, %d\n", ret);
+ }
+
+ return ret;
+}
+
+size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size)
+{
+ size_t size_read;
+ int ret;
+
+ ret = mmc_part_switch_current_boot();
+ if (ret < 0) {
return 0;
}
size_read = mmc_read_blocks(lba, buf, size);
- ret = mmc_part_switch(0);
+ ret = mmc_part_switch_user();
if (ret < 0) {
- ERROR("Failed to switch back to user partition, %d\n", ret);
return 0;
}
diff --git a/fdts/stm32mp13-bl2.dtsi b/fdts/stm32mp13-bl2.dtsi
index 41d6e2e..00bf1b5 100644
--- a/fdts/stm32mp13-bl2.dtsi
+++ b/fdts/stm32mp13-bl2.dtsi
@@ -101,7 +101,7 @@
/delete-node/ tamp@5c00a000;
/delete-node/ stgen@5c008000;
- pin-controller@50002000 {
+ pinctrl@50002000 {
#if !STM32MP_EMMC && !STM32MP_SDMMC
/delete-node/ sdmmc1-b4-0;
/delete-node/ sdmmc2-b4-0;
diff --git a/fdts/stm32mp131.dtsi b/fdts/stm32mp131.dtsi
index adf7a91..decd812 100644
--- a/fdts/stm32mp131.dtsi
+++ b/fdts/stm32mp131.dtsi
@@ -480,7 +480,7 @@
* Break node order to solve dependency probe issue between
* pinctrl and exti.
*/
- pinctrl: pin-controller@50002000 {
+ pinctrl: pinctrl@50002000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp135-pinctrl";
diff --git a/fdts/stm32mp15-bl2.dtsi b/fdts/stm32mp15-bl2.dtsi
index d00e35b..501b092 100644
--- a/fdts/stm32mp15-bl2.dtsi
+++ b/fdts/stm32mp15-bl2.dtsi
@@ -46,7 +46,7 @@
/delete-node/ i2c@5c009000;
/delete-node/ tamp@5c00a000;
- pin-controller@50002000 {
+ pinctrl@50002000 {
#if !STM32MP_RAW_NAND
/delete-node/ fmc-0;
#endif
diff --git a/fdts/stm32mp15-bl32.dtsi b/fdts/stm32mp15-bl32.dtsi
index ca4bb3e..31b24f6 100644
--- a/fdts/stm32mp15-bl32.dtsi
+++ b/fdts/stm32mp15-bl32.dtsi
@@ -27,7 +27,7 @@
/delete-node/ stgen@5c008000;
/delete-node/ i2c@5c009000;
- pin-controller@50002000 {
+ pinctrl@50002000 {
/delete-node/ fmc-0;
/delete-node/ qspi-clk-0;
/delete-node/ qspi-bk1-0;
diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi
index 63cc917..20071fe 100644
--- a/fdts/stm32mp151.dtsi
+++ b/fdts/stm32mp151.dtsi
@@ -532,7 +532,7 @@
* Break node order to solve dependency probe issue between
* pinctrl and exti.
*/
- pinctrl: pin-controller@50002000 {
+ pinctrl: pinctrl@50002000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp157-pinctrl";
@@ -663,7 +663,7 @@
};
};
- pinctrl_z: pin-controller-z@54004000 {
+ pinctrl_z: pinctrl@54004000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp157-z-pinctrl";
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
index 834a80f..c154ea5 100644
--- a/include/drivers/mmc.h
+++ b/include/drivers/mmc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -66,6 +66,7 @@
#define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0)
#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
#define PART_CFG_BOOT_PARTITION1_ACCESS (U(1) << 0)
+#define PART_CFG_BOOT_PARTITION_NO_ACCESS U(0)
#define PART_CFG_BOOT_PART_EN_MASK GENMASK(5, 3)
#define PART_CFG_BOOT_PART_EN_SHIFT 3
#define PART_CFG_CURRENT_BOOT_PARTITION(x) (((x) & PART_CFG_BOOT_PART_EN_MASK) >> \
@@ -233,9 +234,8 @@
size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size);
size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size);
size_t mmc_erase_blocks(int lba, size_t size);
-size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
-size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
-size_t mmc_rpmb_erase_blocks(int lba, size_t size);
+int mmc_part_switch_current_boot(void);
+int mmc_part_switch_user(void);
size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size);
int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
unsigned int width, unsigned int flags,
diff --git a/include/services/rmmd_svc.h b/include/services/rmmd_svc.h
index 2fbdddd..156d89c 100644
--- a/include/services/rmmd_svc.h
+++ b/include/services/rmmd_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,17 +10,18 @@
#include <lib/smccc.h>
#include <lib/utils_def.h>
-/* Construct RMM fastcall std FID from function number */
-#define RMM_FID(smc_cc, func_num) \
- ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \
- ((smc_cc) << FUNCID_CC_SHIFT) | \
- (OEN_STD_START << FUNCID_OEN_SHIFT) | \
- ((func_num) << FUNCID_NUM_SHIFT))
-
-/* The macros below are used to identify RMI calls from the SMC function ID */
+/* STD calls FNUM Min/Max ranges */
#define RMI_FNUM_MIN_VALUE U(0x150)
#define RMI_FNUM_MAX_VALUE U(0x18F)
+/* Construct RMI fastcall std FID from offset */
+#define SMC64_RMI_FID(_offset) \
+ ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \
+ (SMC_64 << FUNCID_CC_SHIFT) | \
+ (OEN_STD_START << FUNCID_OEN_SHIFT) | \
+ (((RMI_FNUM_MIN_VALUE + (_offset)) & FUNCID_NUM_MASK) \
+ << FUNCID_NUM_SHIFT))
+
#define is_rmi_fid(fid) __extension__ ({ \
__typeof__(fid) _fid = (fid); \
((GET_SMC_NUM(_fid) >= RMI_FNUM_MIN_VALUE) && \
@@ -31,13 +32,13 @@
((_fid & 0x00FE0000) == 0U)); })
/*
- * RMI_FNUM_REQ_COMPLETE is the only function in the RMI rnage that originates
+ * RMI_FNUM_REQ_COMPLETE is the only function in the RMI range that originates
* from the Realm world and is handled by the RMMD. The RMI functions are
* always invoked by the Normal world, forwarded by RMMD and handled by the
- * RMM
+ * RMM.
*/
-#define RMI_FNUM_REQ_COMPLETE U(0x18F)
-#define RMMD_RMI_REQ_COMPLETE RMM_FID(SMC_64, RMI_FNUM_REQ_COMPLETE)
+ /* 0x18F */
+#define RMMD_RMI_REQ_COMPLETE SMC64_RMI_FID(U(0x3F))
/* The SMC in the range 0x8400 0190 - 0x8400 01AF are reserved for RSIs.*/
@@ -50,6 +51,14 @@
#define RMMD_EL3_FNUM_MIN_VALUE U(0x1B0)
#define RMMD_EL3_FNUM_MAX_VALUE U(0x1CF)
+/* Construct RMM_EL3 fastcall std FID from offset */
+#define SMC64_RMMD_EL3_FID(_offset) \
+ ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \
+ (SMC_64 << FUNCID_CC_SHIFT) | \
+ (OEN_STD_START << FUNCID_OEN_SHIFT) | \
+ (((RMMD_EL3_FNUM_MIN_VALUE + (_offset)) & FUNCID_NUM_MASK) \
+ << FUNCID_NUM_SHIFT))
+
/* The macros below are used to identify GTSI calls from the SMC function ID */
#define is_rmmd_el3_fid(fid) __extension__ ({ \
__typeof__(fid) _fid = (fid); \
@@ -60,14 +69,9 @@
(GET_SMC_OEN(_fid) == OEN_STD_START) && \
((_fid & 0x00FE0000) == 0U)); })
-/* RMMD Service Function NUmbers */
-#define GTSI_DELEGATE U(0x1B0)
-#define GTSI_UNDELEGATE U(0x1B1)
-#define ATTEST_GET_REALM_KEY U(0x1B2)
-#define ATTEST_GET_PLAT_TOKEN U(0x1B3)
-
-#define RMMD_GTSI_DELEGATE RMM_FID(SMC_64, GTSI_DELEGATE)
-#define RMMD_GTSI_UNDELEGATE RMM_FID(SMC_64, GTSI_UNDELEGATE)
+ /* 0x1B0 - 0x1B1 */
+#define RMMD_GTSI_DELEGATE SMC64_RMMD_EL3_FID(U(0))
+#define RMMD_GTSI_UNDELEGATE SMC64_RMMD_EL3_FID(U(1))
/* Return error codes from RMM-EL3 SMCs */
#define RMMD_OK 0
@@ -77,21 +81,6 @@
#define RMMD_ERR_INVAL -5
#define RMMD_ERR_UNK -6
-/*
- * Retrieve Platform token from EL3.
- * The arguments to this SMC are :
- * arg0 - Function ID.
- * arg1 - Platform attestation token buffer Physical address. (The challenge
- * object is passed in this buffer.)
- * arg2 - Platform attestation token buffer size (in bytes).
- * arg3 - Challenge object size (in bytes). It has be one of the defined SHA hash
- * sizes.
- * The return arguments are :
- * ret0 - Status / error.
- * ret1 - Size of the platform token if successful.
- */
-#define RMMD_ATTEST_GET_PLAT_TOKEN RMM_FID(SMC_64, ATTEST_GET_PLAT_TOKEN)
-
/* Acceptable SHA sizes for Challenge object */
#define SHA256_DIGEST_SIZE 32U
#define SHA384_DIGEST_SIZE 48U
@@ -110,7 +99,24 @@
* ret0 - Status / error.
* ret1 - Size of the realm attestation key if successful.
*/
+ /* 0x1B2 */
+#define RMMD_ATTEST_GET_REALM_KEY SMC64_RMMD_EL3_FID(U(2))
+
+/*
+ * Retrieve Platform token from EL3.
+ * The arguments to this SMC are :
+ * arg0 - Function ID.
+ * arg1 - Platform attestation token buffer Physical address. (The challenge
+ * object is passed in this buffer.)
+ * arg2 - Platform attestation token buffer size (in bytes).
+ * arg3 - Challenge object size (in bytes). It has to be one of the defined
+ * SHA hash sizes.
+ * The return arguments are :
+ * ret0 - Status / error.
+ * ret1 - Size of the platform token if successful.
+ */
-#define RMMD_ATTEST_GET_REALM_KEY RMM_FID(SMC_64, ATTEST_GET_REALM_KEY)
+ /* 0x1B3 */
+#define RMMD_ATTEST_GET_PLAT_TOKEN SMC64_RMMD_EL3_FID(U(3))
/* ECC Curve types for attest key generation */
#define ATTEST_KEY_CURVE_ECC_SECP384R1 0
diff --git a/plat/imx/imx8m/imx8mq/gpc.c b/plat/imx/imx8m/imx8mq/gpc.c
index 367c941..fa83324 100644
--- a/plat/imx/imx8m/imx8mq/gpc.c
+++ b/plat/imx/imx8m/imx8mq/gpc.c
@@ -9,6 +9,7 @@
#include <stdbool.h>
#include <common/debug.h>
+#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <platform_def.h>
@@ -176,6 +177,13 @@
mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG1PHY_SCR, 0x1);
mmio_clrbits_32(IMX_SRC_BASE + SRC_OTG2PHY_SCR, 0x1);
- /* enable all the power domain by default */
- mmio_write_32(IMX_GPC_BASE + PU_PGC_UP_TRG, 0x3fcf);
+ /*
+ * for USB OTG, the limitation are:
+ * 1. before system clock config, the IPG clock run at 12.5MHz, delay time
+ * should be longer than 82us.
+ * 2. after system clock config, ipg clock run at 66.5MHz, delay time
+ * be longer that 15.3 us.
+ * Add 100us to make sure the USB OTG SRC is clear safely.
+ */
+ udelay(100);
}
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index a76e895..1dd22d9 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -126,7 +126,7 @@
#define OCRAM_S_SIZE U(0x8000)
#define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE)
-#define COUNTER_FREQUENCY 8000000 /* 8MHz */
+#define COUNTER_FREQUENCY 8333333 /* 25MHz / 3 */
#define DEBUG_CONSOLE 0
#define IMX_WDOG_B_RESET
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index b2038bc..94c36d9 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -122,6 +122,37 @@
return io_dev_init(storage_dev_handle, 0);
}
+#if STM32MP_EMMC_BOOT
+static uint32_t get_boot_part_fip_header(void)
+{
+ io_block_spec_t emmc_boot_fip_block_spec = {
+ .offset = STM32MP_EMMC_BOOT_FIP_OFFSET,
+ .length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */
+ };
+ uint32_t magic = 0U;
+ int io_result;
+ size_t bytes_read;
+ uintptr_t fip_hdr_handle;
+
+ io_result = io_open(storage_dev_handle, (uintptr_t)&emmc_boot_fip_block_spec,
+ &fip_hdr_handle);
+ assert(io_result == 0);
+
+ io_result = io_read(fip_hdr_handle, (uintptr_t)&magic, sizeof(magic),
+ &bytes_read);
+ if ((io_result != 0) || (bytes_read != sizeof(magic))) {
+ panic();
+ }
+
+ io_close(fip_hdr_handle);
+
+ VERBOSE("%s: eMMC boot magic at offset 256K: %08x\n",
+ __func__, magic);
+
+ return magic;
+}
+#endif
+
static void print_boot_device(boot_api_context_t *boot_context)
{
switch (boot_context->boot_interface_selected) {
@@ -195,7 +226,7 @@
panic();
}
- /* Open MMC as a block device to read GPT table */
+ /* Open MMC as a block device to read FIP */
io_result = register_io_dev_block(&mmc_dev_con);
if (io_result != 0) {
panic();
@@ -204,6 +235,25 @@
io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec,
&storage_dev_handle);
assert(io_result == 0);
+
+#if STM32MP_EMMC_BOOT
+ if (mmc_dev_type == MMC_IS_EMMC) {
+ io_result = mmc_part_switch_current_boot();
+ assert(io_result == 0);
+
+ if (get_boot_part_fip_header() != TOC_HEADER_NAME) {
+ WARN("%s: Can't find FIP header on eMMC boot partition. Trying GPT\n",
+ __func__);
+ io_result = mmc_part_switch_user();
+ assert(io_result == 0);
+ return;
+ }
+
+ VERBOSE("%s: FIP header found on eMMC boot partition\n",
+ __func__);
+ image_block_spec.offset = STM32MP_EMMC_BOOT_FIP_OFFSET;
+ }
+#endif
}
#endif /* STM32MP_SDMMC || STM32MP_EMMC */
@@ -385,8 +435,14 @@
switch (boot_itf) {
#if STM32MP_SDMMC || STM32MP_EMMC
- case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC:
+#if STM32MP_EMMC_BOOT
+ if (image_block_spec.offset == STM32MP_EMMC_BOOT_FIP_OFFSET) {
+ break;
+ }
+#endif
+ /* fallthrough */
+ case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD:
if (!gpt_init_done) {
/*
* With FWU Multi Bank feature enabled, the selection of
diff --git a/plat/st/stm32mp1/stm32mp1_fip_def.h b/plat/st/stm32mp1/stm32mp1_fip_def.h
index 7a277fd..2076175 100644
--- a/plat/st/stm32mp1/stm32mp1_fip_def.h
+++ b/plat/st/stm32mp1/stm32mp1_fip_def.h
@@ -98,8 +98,9 @@
#endif
/*******************************************************************************
- * STM32MP1 RAW partition offset for MTD devices
+ * STM32MP1 RAW partition offset for devices without GPT
******************************************************************************/
+#define STM32MP_EMMC_BOOT_FIP_OFFSET U(0x00040000)
#define STM32MP_NOR_FIP_OFFSET U(0x00080000)
#define STM32MP_NAND_FIP_OFFSET U(0x00200000)
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 1617afd..d6ad325 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -199,6 +199,8 @@
int stm32_get_gpio_bank_pinctrl_node(void *fdt, unsigned int bank)
{
+ const char *node_compatible = NULL;
+
switch (bank) {
case GPIO_BANK_A:
case GPIO_BANK_B:
@@ -209,18 +211,24 @@
case GPIO_BANK_G:
case GPIO_BANK_H:
case GPIO_BANK_I:
+#if STM32MP13
+ node_compatible = "st,stm32mp135-pinctrl";
+ break;
+#endif
#if STM32MP15
case GPIO_BANK_J:
case GPIO_BANK_K:
-#endif
- return fdt_path_offset(fdt, "/soc/pin-controller");
-#if STM32MP15
+ node_compatible = "st,stm32mp157-pinctrl";
+ break;
case GPIO_BANK_Z:
- return fdt_path_offset(fdt, "/soc/pin-controller-z");
+ node_compatible = "st,stm32mp157-z-pinctrl";
+ break;
#endif
default:
panic();
}
+
+ return fdt_node_offset_by_compatible(fdt, -1, node_compatible);
}
#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
diff --git a/services/std_svc/rmmd/trp/trp_private.h b/services/std_svc/rmmd/trp/trp_private.h
index 43a4a4b..4c5222e 100644
--- a/services/std_svc/rmmd/trp/trp_private.h
+++ b/services/std_svc/rmmd/trp/trp_private.h
@@ -30,19 +30,10 @@
#define write_trp_arg(args, offset, val) (((args)->regs[offset >> 3]) \
= val)
-
-/* RMI handled by TRP */
-#define RMI_FNUM_VERSION_REQ U(0x150)
-
-#define RMI_FNUM_GRANULE_DELEGATE U(0x151)
-#define RMI_FNUM_GRANULE_UNDELEGATE U(0x152)
-
-#define RMI_RMM_REQ_VERSION RMM_FID(SMC_64, RMI_FNUM_VERSION_REQ)
-
-#define RMI_RMM_GRANULE_DELEGATE RMM_FID(SMC_64, \
- RMI_FNUM_GRANULE_DELEGATE)
-#define RMI_RMM_GRANULE_UNDELEGATE RMM_FID(SMC_64, \
- RMI_FNUM_GRANULE_UNDELEGATE)
+/* RMI SMC64 FIDs handled by the TRP */
+#define RMI_RMM_REQ_VERSION SMC64_RMI_FID(U(0))
+#define RMI_RMM_GRANULE_DELEGATE SMC64_RMI_FID(U(1))
+#define RMI_RMM_GRANULE_UNDELEGATE SMC64_RMI_FID(U(2))
/* Definitions for RMI VERSION */
#define RMI_ABI_VERSION_MAJOR U(0x0)