diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c
index f617692..2a82e16 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.c
+++ b/drivers/marvell/comphy/phy-comphy-3700.c
@@ -450,7 +450,7 @@
 	 */
 	data = 0;
 	mask = PHY_REF_CLK_SEL;
-	reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask);
+	reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0, sd_ip_addr), data, mask);
 
 	/*
 	 * 9. Set correct reference clock frequency in COMPHY register
@@ -646,39 +646,38 @@
 	 */
 	mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |
 		CFG_TX_ALIGN_POS_MASK;
-	usb3_reg_set(reg_base, COMPHY_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK,
-		     mask);
+	usb3_reg_set(reg_base, COMPHY_LANE_CFG0, PRD_TXDEEMPH0_MASK, mask);
 
 	/*
 	 * 2. Set BIT0: enable transmitter in high impedance mode
 	 *    Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
 	 *    Set BIT6: Tx detect Rx at HiZ mode
 	 *    Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
-	 *            together with bit 0 of COMPHY_LANE_CFG0_ADDR register
+	 *            together with bit 0 of COMPHY_LANE_CFG0 register
 	 */
 	mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |
 		TX_ELEC_IDLE_MODE_EN;
 	data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
-	usb3_reg_set(reg_base, COMPHY_LANE_CFG1_ADDR, data, mask);
+	usb3_reg_set(reg_base, COMPHY_LANE_CFG1, data, mask);
 
 	/*
 	 * 3. Set Spread Spectrum Clock Enabled
 	 */
-	usb3_reg_set(reg_base, COMPHY_LANE_CFG4_ADDR,
+	usb3_reg_set(reg_base, COMPHY_LANE_CFG4,
 		     SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN);
 
 	/*
 	 * 4. Set Override Margining Controls From the MAC:
 	 *    Use margining signals from lane configuration
 	 */
-	usb3_reg_set(reg_base, COMPHY_TEST_MODE_CTRL_ADDR,
+	usb3_reg_set(reg_base, COMPHY_TEST_MODE_CTRL,
 		     MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK);
 
 	/*
 	 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
 	 *    set Mode Clock Source = PCLK is generated from REFCLK
 	 */
-	usb3_reg_set(reg_base, COMPHY_GLOB_CLK_SRC_LO_ADDR, 0x0,
+	usb3_reg_set(reg_base, COMPHY_GLOB_CLK_SRC_LO, 0x0,
 		     (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE |
 		      BUNDLE_SAMPLE_CTRL | PLL_READY_DLY));
 
@@ -721,19 +720,19 @@
 	mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
 		CFG_PM_RXDLOZ_WAIT_MASK;
 	data = CFG_PM_RXDEN_WAIT_1_UNIT  | cfg;
-	usb3_reg_set(reg_base, COMPHY_PWR_MGM_TIM1_ADDR, data, mask);
+	usb3_reg_set(reg_base, COMPHY_PWR_MGM_TIM1, data, mask);
 
 	/*
 	 * 9. Enable idle sync
 	 */
 	data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN;
-	usb3_reg_set(reg_base, COMPHY_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK);
+	usb3_reg_set(reg_base, COMPHY_UNIT_CTRL, data, REG_16_BIT_MASK);
 
 	/*
 	 * 10. Enable the output of 500M clock
 	 */
 	data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN;
-	usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK);
+	usb3_reg_set(reg_base, COMPHY_MISC_REG0, data, REG_16_BIT_MASK);
 
 	/*
 	 * 11. Set 20-bit data width
@@ -777,14 +776,13 @@
 	 * 16. Release SW reset
 	 */
 	data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
-	usb3_reg_set(reg_base, COMPHY_GLOB_PHY_CTRL0_ADDR, data,
-		     REG_16_BIT_MASK);
+	usb3_reg_set(reg_base, COMPHY_GLOB_PHY_CTRL0, data, REG_16_BIT_MASK);
 
 	/* Wait for > 55 us to allow PCLK be enabled */
 	udelay(PLL_SET_DELAY_US);
 
 	if (comphy_index == COMPHY_LANE2) {
-		data = COMPHY_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET;
+		data = COMPHY_LANE_STATUS1 + USB3PHY_LANE2_REG_BASE_OFFSET;
 		mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET,
 			      data);
 
diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index 9bc1a5d..1d24a0c 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -121,36 +121,36 @@
 #define RSVD_PH03FH_6_0_MASK		(((1 << RSVD_PH03FH_6_0_LEN) - 1) << \
 					 RSVD_PH03FH_6_0_OFF)
 
-#define COMPHY_UNIT_CTRL_ADDR		0x48
-#define UNIT_CTRL_ADDR(unit)		(COMPHY_UNIT_CTRL_ADDR * PHY_SHFT(unit))
+#define COMPHY_UNIT_CTRL		0x48
+#define UNIT_CTRL_ADDR(unit)		(COMPHY_UNIT_CTRL * PHY_SHFT(unit))
 #define IDLE_SYNC_EN			BIT(12)
 #define UNIT_CTRL_DEFAULT_VALUE		0x60
 
-#define COMPHY_MISC_REG0_ADDR		0x4F
-#define MISC_REG0_ADDR(unit)		(COMPHY_MISC_REG0_ADDR * PHY_SHFT(unit))
+#define COMPHY_MISC_REG0		0x4F
+#define MISC_REG0_ADDR(unit)		(COMPHY_MISC_REG0 * PHY_SHFT(unit))
 #define CLK100M_125M_EN			BIT(4)
 #define TXDCLK_2X_SEL			BIT(6)
 #define CLK500M_EN			BIT(7)
 #define PHY_REF_CLK_SEL			BIT(10)
 #define MISC_REG0_DEFAULT_VALUE		0xA00D
 
-#define COMPHY_MISC_REG1_ADDR		0x73
-#define MISC_REG1_ADDR(unit)		(COMPHY_MISC_REG1_ADDR * PHY_SHFT(unit))
+#define COMPHY_MISC_REG1		0x73
+#define MISC_REG1_ADDR(unit)		(COMPHY_MISC_REG1 * PHY_SHFT(unit))
 #define SEL_BITS_PCIE_FORCE		BIT(15)
 
 #define COMPHY_GEN2_SETTINGS_3		0x112
 #define COMPHY_GEN_FFE_CAP_SEL_MASK	0xF
 #define COMPHY_GEN_FFE_CAP_SEL_VALUE	0xF
 
-#define COMPHY_LANE_CFG0_ADDR		0x180
-#define LANE_CFG0_ADDR(unit)		(COMPHY_LANE_CFG0_ADDR * PHY_SHFT(unit))
+#define COMPHY_LANE_CFG0		0x180
+#define LANE_CFG0_ADDR(unit)		(COMPHY_LANE_CFG0 * PHY_SHFT(unit))
 #define PRD_TXDEEMPH0_MASK		BIT(0)
 #define PRD_TXMARGIN_MASK		(BIT(1) | BIT(2) | BIT(3))
 #define PRD_TXSWING_MASK		BIT(4)
 #define CFG_TX_ALIGN_POS_MASK		(BIT(5) | BIT(6) | BIT(7) | BIT(8))
 
-#define COMPHY_LANE_CFG1_ADDR		0x181
-#define LANE_CFG1_ADDR(unit)		(COMPHY_LANE_CFG1_ADDR * PHY_SHFT(unit))
+#define COMPHY_LANE_CFG1		0x181
+#define LANE_CFG1_ADDR(unit)		(COMPHY_LANE_CFG1 * PHY_SHFT(unit))
 #define PRD_TXDEEMPH1_MASK		BIT(15)
 #define USE_MAX_PLL_RATE_EN		BIT(9)
 #define TX_DET_RX_MODE			BIT(6)
@@ -158,18 +158,16 @@
 #define GEN2_TX_DATA_DLY_DEFT		(2 << 3)
 #define TX_ELEC_IDLE_MODE_EN		BIT(0)
 
-#define COMPHY_LANE_STATUS1_ADDR	0x183
-#define LANE_STATUS1_ADDR(unit)		(COMPHY_LANE_STATUS1_ADDR * \
-					 PHY_SHFT(unit))
+#define COMPHY_LANE_STATUS1		0x183
+#define LANE_STATUS1_ADDR(unit)		(COMPHY_LANE_STATUS1 * PHY_SHFT(unit))
 #define TXDCLK_PCLK_EN				BIT(0)
 
-#define COMPHY_LANE_CFG4_ADDR		0x188
-#define LANE_CFG4_ADDR(unit)		(COMPHY_LANE_CFG4_ADDR * PHY_SHFT(unit))
+#define COMPHY_LANE_CFG4		0x188
+#define LANE_CFG4_ADDR(unit)		(COMPHY_LANE_CFG4 * PHY_SHFT(unit))
 #define SPREAD_SPECTRUM_CLK_EN		BIT(7)
 
-#define COMPHY_GLOB_PHY_CTRL0_ADDR	0x1C1
-#define GLOB_PHY_CTRL0_ADDR(unit)	(COMPHY_GLOB_PHY_CTRL0_ADDR * \
-					 PHY_SHFT(unit))
+#define COMPHY_GLOB_PHY_CTRL0		0x1C1
+#define GLOB_PHY_CTRL0_ADDR(unit)	(COMPHY_GLOB_PHY_CTRL0 * PHY_SHFT(unit))
 #define SOFT_RESET			BIT(0)
 #define MODE_CORE_CLK_FREQ_SEL		BIT(9)
 #define MODE_PIPE_WIDTH_32		BIT(3)
@@ -178,13 +176,12 @@
 #define MODE_REFDIV_MASK		(0x3 << MODE_REFDIV_OFFSET)
 #define MODE_REFDIV_BY_4		(0x2 << MODE_REFDIV_OFFSET)
 
-#define COMPHY_TEST_MODE_CTRL_ADDR	0x1C2
-#define TEST_MODE_CTRL_ADDR(unit)	(COMPHY_TEST_MODE_CTRL_ADDR * \
-					 PHY_SHFT(unit))
+#define COMPHY_TEST_MODE_CTRL		0x1C2
+#define TEST_MODE_CTRL_ADDR(unit)	(COMPHY_TEST_MODE_CTRL * PHY_SHFT(unit))
 #define MODE_MARGIN_OVERRIDE		BIT(2)
 
-#define COMPHY_GLOB_CLK_SRC_LO_ADDR	0x1C3
-#define GLOB_CLK_SRC_LO_ADDR(unit)	(COMPHY_GLOB_CLK_SRC_LO_ADDR * \
+#define COMPHY_GLOB_CLK_SRC_LO		0x1C3
+#define GLOB_CLK_SRC_LO_ADDR(unit)	(COMPHY_GLOB_CLK_SRC_LO * \
 					 PHY_SHFT(unit))
 #define MODE_CLK_SRC			BIT(0)
 #define BUNDLE_PERIOD_SEL		BIT(1)
@@ -193,9 +190,8 @@
 #define PLL_READY_DLY			(BIT(5) | BIT(6) | BIT(7))
 #define CFG_SEL_20B			BIT(15)
 
-#define COMPHY_PWR_MGM_TIM1_ADDR	0x1D0
-#define PWR_MGM_TIM1_ADDR(unit)		(COMPHY_PWR_MGM_TIM1_ADDR * \
-					 PHY_SHFT(unit))
+#define COMPHY_PWR_MGM_TIM1		0x1D0
+#define PWR_MGM_TIM1_ADDR(unit)		(COMPHY_PWR_MGM_TIM1 * PHY_SHFT(unit))
 #define CFG_PM_OSCCLK_WAIT_OFF		12
 #define CFG_PM_OSCCLK_WAIT_LEN		4
 #define CFG_PM_OSCCLK_WAIT_MASK		(((1 << CFG_PM_OSCCLK_WAIT_LEN) - 1) \