fix(drivers/rcar3): fix CPG registers redefinition
This commit deletes the value of the redefined CPG register.
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Change-Id: I05cf4a449ae28adb2ddd59593971a7d0cbcb21de
diff --git a/drivers/renesas/common/emmc/emmc_init.c b/drivers/renesas/common/emmc/emmc_init.c
index 9c2ec47..c0ec600 100644
--- a/drivers/renesas/common/emmc/emmc_init.c
+++ b/drivers/renesas/common/emmc/emmc_init.c
@@ -88,11 +88,11 @@
SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
SETR_32(SD_CLK_CTRL, 0x00000000U); /* MMC clock stop */
- dataL = mmio_read_32(CPG_SMSTPCR3);
+ dataL = mmio_read_32(SMSTPCR3);
if ((dataL & CPG_MSTP_MMC) == 0U) {
dataL |= (CPG_MSTP_MMC);
mmio_write_32(CPG_CPGWPR, (~dataL));
- mmio_write_32(CPG_SMSTPCR3, dataL);
+ mmio_write_32(SMSTPCR3, dataL);
}
return result;
@@ -101,7 +101,7 @@
static EMMC_ERROR_CODE emmc_dev_init(void)
{
/* Enable clock supply to eMMC. */
- mstpcr_write(CPG_SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC);
+ mstpcr_write(SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC);
/* Set SD clock */
mmio_write_32(CPG_CPGWPR, ~((uint32_t) (BIT9 | BIT0))); /* SD phy 200MHz */