feat(cpufeat): add support for FEAT_FGWTE3
Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.
Excluded Registers:
MDCR_EL3 and MPAM3_EL3: Not trapped as they are part of the EL3 context.
SCTLR_EL3: Not trapped since it is overwritten during
powerdown sequence(Included when HW_ASSISTED_COHERENCY=1)
TPIDR_EL3: Excluded due to its use in crash reporting(It is included
when CRASH_REPORTING=0)
Reference:
https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/FGWTE3-EL3--Fine-Grained-Write-Traps-EL3
Change-Id: Idcb32aaac7d65a0b0e5c90571af00e01a4e9edb1
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index a178f48..e188f74 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -671,6 +671,9 @@
sme_init_el3();
}
+ if (is_feat_fgwte3_supported()) {
+ write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL);
+ }
pmuv3_init_el3();
}
@@ -1161,6 +1164,14 @@
init_nonsecure_el2_unused(ctx);
}
}
+
+ if (is_feat_fgwte3_supported()) {
+ /*
+ * TCR_EL3 and ACTLR_EL3 could be overwritten
+ * by platforms and hence is locked a bit late.
+ */
+ write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL);
+ }
}
#if (!CTX_INCLUDE_EL2_REGS)
/* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */