feat(cpufeat): add support for FEAT_FGWTE3
Enable write traps for key EL3 system registers as per FEAT_FGWTE3,
ensuring their values remain unchanged after boot.
Excluded Registers:
MDCR_EL3 and MPAM3_EL3: Not trapped as they are part of the EL3 context.
SCTLR_EL3: Not trapped since it is overwritten during
powerdown sequence(Included when HW_ASSISTED_COHERENCY=1)
TPIDR_EL3: Excluded due to its use in crash reporting(It is included
when CRASH_REPORTING=0)
Reference:
https://developer.arm.com/documentation/ddi0601/2025-06/AArch64-Registers/FGWTE3-EL3--Fine-Grained-Write-Traps-EL3
Change-Id: Idcb32aaac7d65a0b0e5c90571af00e01a4e9edb1
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index f99840b..8a607ac 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -375,6 +375,23 @@
This flag can take the values 0 to 2, to align with the ``ENABLE_FEAT``
mechanism. Default value is ``0``.
+- ``ENABLE_FEAT_FGWTE3``: Numeric value to enable support for
+ Fine Grained Write Trap EL3 (FEAT_FGWTE3), a feature that allows EL3 to
+ restrict overwriting certain EL3 registers after boot.
+ This lockdown is established by setting individual trap bits for
+ system registers that are not expected to be overwritten after boot.
+ This feature is an optional architectural feature and is available from
+ Armv9.4 onwards. This flag can take values from 0 to 2, aligning with
+ the ``ENABLE_FEAT`` mechanism. The default value is 0.
+
+ .. note::
+ This feature currently traps access to all EL3 registers in
+ ``FGWTE3_EL3``, except for ``MDCR_EL3``, ``MPAM3_EL3``,
+ ``TPIDR_EL3``(when ``CRASH_REPORTING=1``), and
+ ``SCTLR_EL3``(when ``HW_ASSISTED_COHERENCY=0``).
+ If additional traps need to be disabled for specific platforms,
+ please contact the Arm team on `TF-A public mailing list`_.
+
- ``ENABLE_FEAT_HCX``: Numeric value to set the bit SCR_EL3.HXEn in EL3 to
allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as
well as adding HCRX_EL2 to the EL2 context save/restore operations. Its a
@@ -1567,3 +1584,4 @@
.. _Firmware Handoff specification: https://github.com/FirmwareHandoff/firmware_handoff/releases/tag/v0.9
.. _PSA Crypto API specification: https://armmbed.github.io/mbed-crypto/html/
.. _Platform Initialization specification: https://uefi.org/specs/PI/1.8/index.html
+.. _TF-A public mailing list: https://lists.trustedfirmware.org/mailman3/lists/tf-a.lists.trustedfirmware.org/